DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-3, 5-13 and 15-20 are pending in this application. Claims 4 and 14 are cancelled.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 03/15/24 and 07/10/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on 03/15/2024. These drawing are acceptable. The objection of the previous office action dated 01/30/26 regarding claims 4 and 14 are withdrawn.
Response to Amendment
Applicant’s amendments, see Remarks, filed 04/29/26, with respect to minor informality of the specification are sufficient to overcome the objection, accordingly the objection has been withdrawn. The applicants argument to the claim objection of claim 20 has been fully considered and is persuasive. The claim objection has been withdrawn.
Response to Arguments
Applicant argues on page 9, “Demange fails to teach or suggest "a current-steering circuit coupled to the current replicator and configured to replicate and reverse a polarity of the fractional aggressor current to generate a reversed fractional aggressor current" as recited in claim 7.
Examiner respectfully disagreed. Demange’s Power supply device 100 of figure 1 clearly discloses what is claimed in claim 7 and those skilled in the art would readily recognize the equivalence. The topology shown in figure 1 of Demange is a classic approach for sensing load-induced current spikes (the "aggressor current") and generating an equal-but-opposite current to stabilize the primary supply rail. LDO Regulator (120) is clearly identified by the error amplifier (122) and PMOS pass transistor (T121) regulating the VDD node for the load (110). “Current Replicator” (Stage 120/124) where transistor (T123) acts as a sense transistor, mirroring a fraction of the current passing through the main LDO pass transistor, configured to replicate a scaled version of the load current (I2) to generate a fractional/scaled version aggressor current (I1). “Current-Steering/Polarity reversal circuit” (174) including current mirror components (146, 174, and T145, T160) and steering logic (using amplifier 178) is configured to replicate and reverse the polarity of the fractional current, resulting in a reversed fractional aggressor current (I3). The current mirror (146) formed by T127 and T145 takes the sensed current and pulls it from node 150, effectively "reversing the polarity" for the next stage. Because I1’ is pulled away from node 150, the net current delivered to the steering branch is I3 = I4 - I1'. An increase in the aggressor current results in a decrease in I3, effectively reversing the AC polarity of the transient current achieved using Kirchhoff's Current Law (KCL) via a subtraction mechanism at node 150. The op-amp 178 and the current mirror 174 (comprising T160 and T172) work to balance the currents at node 150. By pulling current from this node via T160 and mirroring it through T172, the circuit effectively "reverses" the direction of the fractional current relative to the power supply node (130). Final Current Mirror/Sink (170) stage uses the processed signal to drive T175, which sinks a proportional "adjustment current" (I5) directly from the main power supply node (VCC). The description of Demange does not include the language of the claim, though those skilled in the art would recognize the reversal is not a simple physical flip but a current-summing operation. The circuit mirrors the load current, converts it to a sinking current via NMOS transistors (T127/T145), and then uses a second mirror stage (174) to sink a proportional "adjustment current" from the supply rail, thereby cancelling out fluctuations (the "aggressor" current) caused by the load circuit.
Therefore, the examiner believes that all claim limitations of claim 7 are taught in single reference Demange.
Applicant further argues that “the Examiner has not properly characterized the teachings of the references and, as a result, has failed to ascertain differences between the claimed invention and the references. Accordingly, a prima facie case of obviousness has not been established. Applicant respectfully submits that Demange in view of Lin fails to teach or suggest "a second amplifier including... an output coupled to a gate of the third transistor; [and] a fourth transistor including... a gate coupled to... the output of the second amplifier" as recited in claim 1.” Applicant also alleges “The Examiner refers to transistor MN2 in FIG. 9 of Lin as corresponding to the claimed fourth transistor”.
Examiner disagrees and the rejection of claim 1 remains. In the previous office action dated 1/30/26 page 10 lines 12-14 examiner references Demange to disclose the fourth transistor “a fourth transistor (fig 1, T145) including a source coupled to the reference potential node (fig 1, T145 source S coupled to GND) and a gate coupled to the gate of the third transistor and the output of the second amplifier (fig 1, T145 gate coupled to gate of T127 and output of 126 via T125 drain)”. T145 is connected indirectly through a current mirror configuration (block 146). The gate of T145 is tied to the gate and drain of T127, which connects to the drain of transistor T125 driven directly by the output of amplifier 126. When referring to prior art reference Lin, Examiner mentioned the existence of a fourth transistor as a reason to combine references, however Examiner references on page 11 of the office action and lines 6-8 “a second amplifier (fig 9, A2) with an output coupled to a gate of the third transistor (fig 9, A2 output coupled to gate of MN1)”, without referencing MN2 of Lin as disclosing the claimed limitation. Therefore, Examiner believes the 35 USC § 103 rejection is proper.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7-13 and 15-20 are rejected under 35 U.S.C. 102(a)(1) and 102 (a)(2) as being anticipated by Demange et al. (US 20220066488 A1), hereinafter Demange.
Regarding claims 7 and 15, Demange discloses a power supply circuit (fig 1, power supply device 100) comprising: a low-dropout (LDO) regulator (fig 1, amplifier 122 and transistor T121; these components are what is disclosed as an LDO in the instant application) including an input coupled to a power supply node (fig 1, input shown coupled to VCC) and an output coupled to a load circuit (fig 1, output shown coupled to circuit 110); a current replicator (fig 1, T123, amplifier 126, and T127) coupled to the output of the LDO regulator (fig 1, T121 drain D coupled to + input of amplifier 126) and configured to replicate a scaled version of an aggressor current (par [0066] describes the potential of the drain of transistor T123 is equal to that of the drain of transistor T121. Transistor T123’s current I1 having a value by a constant ratio with a current I2 of transistor T121. Current I1 is an image of current I2 with equality I1=I2/K124, where K124 designates a constant. Constant K124 is in the range from 5 to 200, preferably equal to 100 which is larger than 1), configured to be generated by the load circuit (fig 1, I2 current from circuit 110) and pass through the LDO regulator to the power supply node (fig 1, VCC), to generate a fractional aggressor current (fig 1, current I1’ par [0066] and [0078]); a current-steering circuit (fig 1, current source 155, amplifier 178, T145, and T160) coupled to the current replicator (fig 1, see gate connection between T127 and T145) and configured to replicate and reverse a polarity of the fractional aggressor current to generate a reversed fractional aggressor current (par [0078] and [0079] describe current I1′ is the image of current I1 or replica. Transistors T160 and T172 are provided so that current I5 has with current I3 a ratio K that is the inverse of ratio 1/K between current I1′ and current I0, I3 being the “reversed fractional aggressor current”); and a current mirror (fig 1, T160 and T172 within block 174 and block 170) including an input coupled to the current-steering circuit (fig 1, T160 drain D connected to output of 155 at node 150) and an output coupled to the power supply node (fig 1, output of T172 drain D coupled to VCC via T175), the current mirror being configured to sink an aggressor adjustment current from the power supply node based on the reversed fractional aggressor current (fig 1, T160 and T172 function as current-sinking transistors, they sink current to ground from the circuit nodes they are connected to. T160 sinks current I3 and T172 sinks current I5).
Regarding claims 8 and 16, Demange discloses the power supply circuit of claim 7, wherein the current mirror (fig 1, T160 and T172 within block 174) is configured to replicate a scaled version of the reversed fractional aggressor current to generate the aggressor adjustment current for sinking from the power supply node (see pars [0066] [0078] [0079]).
Regarding claims 9 and 17, Demange discloses the power supply circuit of claim 8, wherein the current replicator (fig 1, T123, amplifier 126, and T127) is configured to provide the fractional aggressor current to the power supply node, wherein the aggressor current is N times higher than the fractional aggressor current, and wherein the aggressor adjustment current is (N+1)/N times higher than the aggressor current, N being a number larger than 1 (see pars [0066] [0078] [0079]).
Regarding claims 10 and 18, Demange discloses the power supply circuit of claim 7, wherein the current-steering circuit (fig 1, current source 155, amplifier 178, T145, and T160) comprises a common node (fig 1, node 150) and wherein to replicate and reverse the polarity of the fractional aggressor current, the current-steering circuit is configured to: replicate the fractional aggressor current (pars [0066] [0078] [0079] fig 1, I1’) in a first path from a reference potential node for the power supply circuit to the common node (fig 1, path I1’ from GND through T145 to node 150); and steer the replicated fractional aggressor current from the common node (fig 1, I1’ to node 150 through T160) to the reference potential node in a second path (fig 1, I3), wherein the replicated fractional aggressor current in the second path is the reversed fractional aggressor current (par [0079] ratio K between the values of currents I5 and I3 is equal to the sum of unity 1 and of ratio K124 between the values of current I2 consumed by circuit 110 and I1′ in transistor T145).
Regarding claim 11, Demange discloses the power supply circuit of claim 10, wherein the current-steering circuit further comprises a DC current source (fig 1, current source 155 and VCC is a known DC voltage source; par [0058] “The chip power supply voltage VCC is typically in the range from 3.3 V to 5 V” though DC is not specified, it is well known in low voltage electronics circuits VCC refers to DC) coupled between the power supply node and the common node (fig 1, 155 is coupled between VCC and node 150).
Regarding claims 12 and 19, Demange discloses the power supply circuit of claim 7, wherein by sinking the aggressor adjustment current from the power supply node, the current mirror is configured to reduce at least one of: injection of a portion of the aggressor current into one or more other circuits via the power supply node (par [0079] describes the current mirror 174 with transistors T160 and T172 so that the sum I0+I4+I5 of the currents I0, I4, and I5 supplied by terminal 130 VCC remains constant, equal to a value (K+1)*I4, whatever the variations of the current I2 consumed by electronic circuit 110); or inductive coupling of the aggressor current to the one or more other circuits.
Regarding claim 13, Demange discloses the power supply circuit of claim 7, wherein the power supply node (fig 1, VCC) is coupled to the current replicator, the current-steering circuit, and the current mirror (fig 1, see VCC and coupling nodes 130 connecting each of the current replicator, the current-steering circuit, and the current mirror through T121, T123, current source 155, and T175).
Regarding claim 20, Demange discloses the method of claim 15, wherein the circuit includes a clock signal or an oscillating signal contributing to the aggressor current (Demange pars [0046], [0052], and [0053] describe circuit 110 as an electronic chip; it is well known that nearly all complex electronic chip circuits, especially digital ones like CPUs and microcontrollers, rely heavily on clock signals (oscillating signals) to synchronize operations).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Demange et al. (US 20220066488 A1), hereinafter Demange and further in view of Lin (US 20120038332 A1).
Regarding claim 1, Demange discloses a power supply circuit (fig 1, power supply device 100), comprising: a low-dropout (LDO) regulator (fig 1, amplifier 122 and transistor T121; these components are what is disclosed as an LDO in the instant application) including a first amplifier and a first transistor (fig 1, amplifier 122 and transistor T121), wherein the first transistor includes a gate coupled to an output of the first amplifier (fig 1, T121 gate coupled to output of 122), a source coupled to a power supply node (fig 1, T121 source S coupled to VCC node 130), and a drain coupled to an input of the first amplifier and to a load circuit (fig 1, T121 drain D coupled to + input of amplifier 122 and circuit 110); a second transistor (fig 1, T123) including a source coupled to the power supply node (fig 1, T123 source S coupled to VCC node 130) and a gate coupled to the gate of the first transistor and the output of the first amplifier (fig 1, T123 gate coupled to output of 122 through gate of T121); a third transistor (fig 1, T127) including a drain coupled to a drain of the second transistor (fig 1, T127 drain D coupled to T123 drain D via T125) and a source coupled to a reference potential node for the power supply circuit (fig 1, T127 source S coupled to GND); a second amplifier (fig 1, amplifier 126) including a first input coupled to the drain of the first transistor and the input of the first amplifier (fig 1, 126 + input coupled to D of T121 and + input of 122), a second input coupled to the drain of the second transistor and to the drain of the third transistor (fig 1, 126 - input coupled to D of T123 and to D of T127 via T125); a fourth transistor (fig 1, T145) including a source coupled to the reference potential node (fig 1, T145 source S coupled to GND) and a gate coupled to the gate of the third transistor and the output of the second amplifier (fig 1, T145 gate coupled to gate of T127 and output of 126 via T125 drain); a current source (fig 1, current source 155) coupled between the power supply node and a drain of the fourth transistor (fig 1, 155 shown coupled between VCC and D of T145); and a current mirror (fig 1, current mirror 174 including T160 and T172) including an input coupled to the current source and to the drain of the fourth transistor (fig 1, drain D of T160 connected to 155 or node 150 and to drain D of T145) and an output coupled to the power supply node (fig 1, drain D of T160 connected to VCC via T175).
Demange fails to disclose a second amplifier with an output coupled to a gate of the third transistor although the output is coupled to the gate of transistor T125 which is connected to the third transistor T127.
Lin discloses a low drop-out (LDO) linear regulator circuit see fig 9 including first amplifier A1, second amplifier A2, first transistor MNS, second transistor MNO, third transistor MN1, and fourth transistor MN2. Lin discloses a second amplifier (fig 9, A2) with an output coupled to a gate of the third transistor (fig 9, A2 output coupled to gate of MN1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Demange and incorporate the transistor/amplifier configuration as taught by Lin. The advantage of this design is that the output of the amplifier is connected to the gates of gates of transistors MN1 and MN2 to control the current flowing through them and is part of a design to achieve a pole-zero tracking or compensation technique designed to stabilize the circuit's performance.
Regarding claim 2, Demange and Lin disclose the power supply circuit of claim 1, wherein the current mirror (Demange fig 1, current mirror 174 including T160 and T172) comprises: a fifth transistor (Demange fig 1, T160) including a drain coupled to the current source and the drain of the fourth transistor (Demange fig 1, T160 drain D coupled to 155 and drain D of T145), and a source coupled to the reference potential node (Demange fig 1, T160 source S coupled to GND); and a sixth transistor (Demange fig 1, T172) including a gate coupled to the gate of the fifth transistor (Demange fig 1, T160 gate connected to gate of T172), a drain coupled to the power supply node (Demange fig 1, T172 drain D connected to VCC via T175), and a source coupled to the reference potential node (Demange fig 1, T172 source S coupled to GND).
Demange fails to disclose a fifth transistor with a gate coupled to the drain of the fifth transistor likely due to the connection to a third amplifier 178. However, you can see the gate to drain connection is present in current mirror 146 transistor T127.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Demange and incorporate the alternative gate to drain connection current mirror as taught by Demange current mirror 146. The advantage of this design is that the drain-to-gate connection of the transistor ensures that the transistor acts as a diode-connected transistor, which establishes a specific voltage reference and sets the bias for the current mirror.
Regarding claim 3, Demange and Lin disclose the power supply circuit of claim 2, wherein: a first size ratio between the first transistor and the second transistor is N:1, N being a number larger than 1 (Demange par [0063] describes the dimension ratio between the transistors; par [0066] describes the potential of the drain of transistor T123 is equal to that of the drain of transistor T121. Transistor T123’s current I1 having a value by a constant ratio with a current I2 of transistor T121. Current I1 is an image of current I2 with equality I1=I2/K124, where K124 designates a constant. Constant K124 is in the range from 5 to 200, preferably equal to 100 which is larger than 1); a second size ratio between the third transistor and the fourth transistor is 1:1 (Demange par [0078] discloses current I1′ is the image of current I1 by current mirror 146, transistors T127 and T145. Due to the fact that current I1 is an image of currents I2 and I0, current I1′ is an image of currents I0 and I2 and has with current I0 a value ratio 1/K, in other words, current I1′ verifies relation I1′=I0/K. As an example, current mirror 146 has a current ratio equal to 1. Ratio 1/K may be equal to 1/(K124+1), for example, equal to 1/101); and a third size ratio between the fifth transistor and the sixth transistor is 1:N+1 (Demange par [0079] discloses the ratio between transistors T160 and T172. Current I5 through transistor T172 has with current I3 through transistor T160, a ratio K that is the inverse of ratio 1/K between current I1′ and current I0. Ratio K between the values of currents I5 and I3 is equal to the sum of unity 1 and of ratio K124 between the values of current I2 consumed by circuit 110 and I1′ in transistor T145. Accordingly, the sum I0+I4+I5 of the currents I0, I4, and I5 supplied by terminal 130 remains constant, equal to a value (K+1)*I4, whatever the variations of the current I2 consumed by electronic circuit 110).
Regarding claim 5, Demange and Lin disclose the power supply circuit of claim 1, wherein the load circuit (Demange fig 1, circuit 110) is configured to operate with a clock signal or an oscillating signal (Demange pars [0046], [0052], and [0053] describe circuit 110 as an electronic chip; it is well knows that nearly all complex electronic chip circuits, especially digital ones like CPUs and microcontrollers, rely heavily on clock signals (oscillating signals) to synchronize operations) that contributes to an aggressor current provided to the power supply node (the signals by default, create noise (current fluctuations) that back-propagates to the power supply) and wherein the current mirror is configured to sink an aggressor adjustment current from the power supply node to reduce at least one of: injection of a portion of the aggressor current into one or more other circuits via the power supply node (Demange par [0079] describes the current mirror 174 with transistors T160 and T172 so that the sum I0+I4+I5 of the currents I0, I4, and I5 supplied by terminal 130 VCC remains constant, equal to a value (K+1)*I4, whatever the variations of the current I2 consumed by electronic circuit 110); or inductive coupling of the aggressor current to the one or more other circuits.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Demange et al. (US 20220066488 A1), hereinafter Demange and further in view of Lin (US 20120038332 A1) and Demange et al. (US 10054973 B2) hereinafter Demange2.
Regarding claim 6, Demange and Lin disclose the power supply circuit of claim 1. Demange and Lin fail disclose wherein the current source is an adjustable DC current source.
Demange2 discloses an integrated circuit and power supply similar to Demange. Demange2 discloses a current source (Demange2 fig 1, current source 61) is an adjustable DC current source (col 5 lines 40-45 describe the control input 62 to current source 61 designed to receive a control signal SC allowing the second fraction to be chosen making the current source adjustable).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Demange and Lin and incorporate the use a controllable/adjustable current source as taught by Demange2. The advantage of this design is that the current source can be adjusted to be a fraction of the reference current.
Conclusion
THIS ACTION IS MADE FINAL.
Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren A Shaw whose telephone number is (571)272-3074. The examiner can normally be reached Mon-Fri 7-5 EST.
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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