Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10, 15 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rinne et al. (US 11201619 and Rinne hereinafter.).
Regarding claim 1, Rinne discloses an isolated gate driver IC package [fig. 3 and 11] for driving a transistor [switch 12 of fig. 3], comprising: an isolated first communication channel [fig. 11, primary winding of 34 coupled to Q1/Q3] connecting a first die [32] configured for a low voltage [Vdrv] and a second die [36] configured for a high voltage [signal Gx of fig. 11 corresponding to Gx of fig. 3 wherein VHV is the high voltage], wherein the IC package includes an isolation barrier between the first and second die [col 9 lines 5-13]; an isolated second communication channel [secondary winding of 34] connecting the first and second die [as shown]; a signal generator on the first die to generate control signals to a converter [PWM into 110], wherein the converter is configured to generate a signal for energizing a primary of a transformer [col 13, lines 10-34, Q1, Q2, Q3, Q4 providing signals on 34]; and a positive voltage rail terminal [Gx] and a negative voltage rail terminal [Sx] that define a bias voltage for the transistor based on signals from a secondary of the transformer [Gx and Sx bias 12 of fig. 3].
Regarding claim 10, Rinne discloses further wherein the control signals comprise PWM signals for driving one or more switches [Col 13 lines 26-34, 110 accepting signal PWM and controlling switches Q1, Q2, Q3 and Q4].
Regarding claim 15, Rinne discloses a method, comprising: providing an isolated first communication channel [primary winding of 34 coupled to Q1/Q3] connecting a first die [32] configured for a low voltage [Vdrv] and a second die [36] configured for a high voltage [signal GX of fig. 11 corresponding to Gx of fig. 3 wherein VHV is the high voltage], wherein the first and second die comprise circuitry for an isolated gate driver IC package [ABSTRACT] for driving a transistor [fig. 3, transistor 12], wherein the IC package includes an isolation barrier [via 34] between the first and second die [col 9 lines 5-13]; connecting the first and second die with an isolated second communication channel [secondary winding of 34]; generating, on the first die, control signals to a converter [PWM into 110], wherein the converter is configured to generate a signal for energizing a primary of a transformer [col 13, lines 10-34, Q1, Q2, Q3, Q4 providing signals on 34]; and providing a positive voltage rail terminal [Gx] and a negative voltage rail terminal [Sx] that define a bias voltage for the transistor based on signals from a secondary of the transformer [Gx and Sx from secondary windings of 34 providing biasing voltages for 12 of fig. 3].
Regarding claim 24, Rinne discloses further wherein the control signals comprise PWM signals for driving one or more switches [Col 13 lines 26-34, 110 accepting signal PWM and controlling switches Q1, Q2, Q3 and Q4].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 4, 11, 16, 18, 25 rejected under 35 U.S.C. 103 as being unpatentable over Rinne in view of Guo et al. (CN 214337812 U and Guo hereinafter.).
Regarding claim 2, Rinne discloses all the features regarding claim 1 as indicated above. Rinne discloses further the second communication channel comprises an inductive channel via a transformer [inherent property of transformers]. Rinne does not explicitly disclose the first communication channel includes a capacitor to provide an isolated capacitive channel across the isolation barrier.
However, Guo discloses [fig. 7] the first communication channel [left side of fig. 7] includes a capacitor [top capacitor] to provide an isolated capacitive channel [inherent property of capacitors blocking DC voltage] across the isolation barrier [right side of fig. 7]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne to include the first communication channel includes a capacitor to provide an isolated capacitive channel across the isolation barrier as taught by Guo to improve communication stability in a circuit.
Regarding claim 4, Rinne in view of Guo discloses further including an isolated third communication channel between the first [Guo, fig. 5 and 7, 21 comprising 30] and second die [Guo, 22 comprising 40], wherein the communication channel comprises a capacitive channel [Guo, bottom capacitor shown in fig 7 between 30 and 40 of fig. 5].
Regarding claim 11, Rinne discloses all the features regarding claim 1 as indicated above. Rinne discloses further wherein the second communication channel comprises an inductive channel via a transformer [inherent property of transformer]. Rinne does not explicitly disclose wherein the first communication channel includes a capacitor to provide an isolated capacitive channel across the isolation barrier, wherein a data rate of the first communication channel is greater than a data rate of the second communication channel.
However, Guo discloses [fig. 7] the first communication channel [left side of fig. 7] includes a capacitor [top capacitor] to provide an isolated capacitive channel [inherent property of capacitors blocking DC voltage] across the isolation barrier [right side of fig. 7]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne to include the first communication channel includes a capacitor to provide an isolated capacitive channel across the isolation barrier, wherein a data rate of the first communication channel is greater than a data rate of the second communication channel as taught by Guo to improve communication stability in a circuit. Rinne in view of Guo does not explicitly disclose a data rate of the first communication channel is greater than a data rate of the second communication channel. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a higher data for an error detector so as to react in time, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 16, Rinne discloses all the features regarding claim 15 as indicated above. Rinne discloses further the second communication channel comprises an inductive channel via a transformer [inherent property of transformers]. Rinne does not explicitly disclose the first communication channel includes a capacitor to provide an isolated capacitive channel across the isolation barrier.
However, Guo discloses [fig. 5 and 7] the first communication channel [left side of fig. 7] includes a capacitor [top capacitor] to provide an isolated capacitive channel [inherent property of capacitors blocking DC voltage] across the isolation barrier [right side of fig. 7]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne to include the first communication channel includes a capacitor to provide an isolated capacitive channel across the isolation barrier as taught by Guo to improve communication stability in a circuit.
Regarding claim 18, Rinne in view of Guo discloses further including providing an isolated third communication channel between the first [Guo, 21 comprising 30] and second die [Guo, 22 comprising 40], wherein the communication channel comprises a capacitive channel [Guo, capacitors shown in fig 7 between 30 and 40 of fig. 5].
Regarding claim 25, Rinne discloses all the features regarding claim 1 as indicated above. Rinne discloses further wherein the second communication channel comprises an inductive channel via a transformer [inherent property of transformer]. Rinne does not explicitly disclose wherein the first communication channel includes a capacitor to provide an isolated capacitive channel across the isolation barrier, wherein a data rate of the first communication channel is greater than a data rate of the second communication channel.
However, Guo discloses [fig. 7] the first communication channel [left side of fig. 7] includes a capacitor [top capacitor] to provide an isolated capacitive channel [inherent property of capacitors blocking DC voltage] across the isolation barrier [right side of fig. 7]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne to include the first communication channel includes a capacitor to provide an isolated capacitive channel across the isolation barrier, wherein a data rate of the first communication channel is greater than a data rate of the second communication channel as taught by Guo to improve communication stability in a circuit. Rinne in view of Guo does not explicitly disclose a data rate of the first communication channel is greater than a data rate of the second communication channel. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a higher data for an error detector so as to react in time, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 3, 5-6, 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Rinne in view of Guo further in view of Haas et al. (US 10380879 B2 and Haas hereinafter.).
Regarding claim 3, Rinne in view of Guo discloses all the features regarding claim 2 as indicated above. Rinne in view of Guo does not explicitly disclose wherein the first and second communication channels provide heterogenous ASIL communication channels.
However, Hass discloses wherein the first and second communication channels provide heterogenous ASIL communication channels [col 1 lines 35-36]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne in view of Guo to include the first and second communication channels provide heterogenous ASIL communication channels as taught by Haas to improve data accuracy mismatch is a circuit.
Regarding claim 5, Rinne in view of Guo discloses all the features regarding claim 4 as indicated above. Rinne in view of Guo does not explicitly disclose wherein the second die includes a comparator to monitor voltage levels on signals on the second die.
However, Haas discloses [col lines 31-45] wherein the second die includes a comparator to monitor voltage levels on signals on the second die [350 of fig. 3A comprising comparator 380 wherein 350 corresponds to ADC 26B of fig. 1B, wherein 1B comprises checker circuit 34]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne in view of Guo to include the second die includes a comparator to monitor voltage levels on signals on the second die as taught by Haas to improve data accuracy mismatch is a circuit.
Regarding claim 6, Rinne in view of Guo further in view of Haas discloses further wherein a signal corresponding to an output of the comparator is transmitted to the signal generator [Haas, fig. 3A, output of 380 into controller 392 where in 392 outputs signals onto 394].
Regarding claim 17, Rinne in view of Guo discloses all the features regarding claim 16 as indicated above. Rinne in view of Guo does not explicitly disclose wherein the first and second communication channels provide heterogenous ASIL communication channels.
However, Hass discloses wherein the first and second communication channels provide heterogenous ASIL communication channels [col 1 lines 35-36]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne in view of Guo to include the first and second communication channels provide heterogenous ASIL communication channels as taught by Haas to improve data accuracy mismatch is a circuit.
Regarding claim 19, Rinne in view of Guo discloses all the features regarding claim 18 as indicated above. Rinne in view of Guo does not explicitly disclose wherein the second die includes a comparator to monitor voltage levels on signals on the second die.
However, Haas discloses [col lines 31-45] wherein the second die includes a comparator to monitor voltage levels on signals on the second die [350 of fig. 3A comprising comparator 380 wherein 350 corresponds to ADC 26B of fig. 1B, wherein 1B comprises checker circuit 34]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne in view of Guo to include the second die includes a comparator to monitor voltage levels on signals on the second die as taught by Haas to improve data accuracy mismatch is a circuit.
Regarding claim 20, Rinne in view of Guo further in view of Haas discloses further wherein a signal corresponding to an output of the comparator is transmitted to the signal generator [Haas, fig. 3A, output of 380 into controller 392 where in 392 outputs signals onto 394].
Claims 7 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Rinne in view of Vinciarelli et al. (US 10014798 B1 and Vinciarelli hereinafter.).
Regarding claim 7, Rinne discloses all the features regarding claim 1 as indicated above. Rinne does not explicitly disclose further including transmitting a fault signal on the first and second communication channels.
However, Vinciarelli discloses further including transmitting a fault signal on the first and second communication channels [col 18 lines 6-25]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne to include transmitting a fault signal on the first and second communication channels as taught by Vinciarelli to improve fault tolerance in a circuit.
Regarding claim 21, Rinne discloses all the features regarding claim 15 as indicated above. Rinne does not explicitly disclose further including transmitting a fault signal on the first and second communication channels.
However, Vinciarelli discloses further including transmitting a fault signal on the first and second communication channels [col 18 lines 6-25]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne to include transmitting a fault signal on the first and second communication channels as taught by Vinciarelli to improve fault tolerance in a circuit.
Claims 8-9 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Rinne in view of Haas.
Regarding claim 8, Rinne in view of Guo discloses all the features regarding claim 1 as indicated above. Rinne in view of Guo does not explicitly disclose further including an ADC and a comparator to detect signal level faults and generate ASIL signals.
However, Haas discloses [col lines 31-45] further including an ADC and a comparator to detect signal level faults [350 of fig. 3A comprising comparator 380 wherein 350 corresponds to ADC 26B of fig. 1B, wherein 1B comprises checker circuit 34] and generate ASIL signals [col 1 lines 35-36]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne in view of Guo to include an ADC and a comparator to detect signal level faults and generate ASIL signals as taught by Haas to data accuracy mismatch is a circuit.
Regarding claim 9, Rinne in view of Haas discloses the claimed except for the ASIL signals comprise a slew rate error signal. It would have been obvious to one having ordinary skill in the art before the effective filing date to have this feature because fig. 3A, col 15 lines 6-31, shows integrator comprising 368 and 372 and outputting a signal into 380. It is well known in the art that integrators act as lowpass filters and therefore increase the slew rate of a signal.
Regarding claim 22, Rinne discloses all the features regarding claim 15 as indicated above. Rinne does not explicitly disclose further including providing an ADC and a comparator to detect signal level faults and generate ASIL signals.
However, Haas discloses [col lines 31-45] further including providing an ADC and a comparator to detect signal level faults [350 of fig. 3A comprising comparator 380 wherein 350 corresponds to ADC 26B of fig. 1B, wherein 1B comprises checker circuit 34] and generate ASIL signals [col 1 lines 35-36]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne to include further including providing an ADC and a comparator to detect signal level faults and generate ASIL signals as taught by Haas to improve data accuracy mismatch is a circuit.
Regarding claim 23, Rinne in view of Haas discloses the claimed except for the ASIL signals comprise a slew rate error signal. It would have been obvious to one having ordinary skill in the art before the effective filing date to have this feature because fig. 3A, col 15 lines 6-31, shows integrator comprising 368 and 372 and outputting a signal into 380. It is well known in the art that integrators act as lowpass filters and therefore increase the slew rate of a signal.
Claims 12-13 and 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Rinne in view of Guo further in view of Liu et al. (CN 114204784 A and Liu hereinafter.).
Regarding claim 12, Rinne in view of Guo discloses all the features regarding claim 11 as indicated above. Rinne in view of Guo does not explicitly discloser wherein the second communication channel is configured to transmit a fault flag.
However, Liu discloses wherein the second communication channel [primary second channel winding of 11] is configured to transmit a fault flag [fig. 2, via 12]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne in view of Guo to include the second communication channel is configured to transmit a fault flag as taught by Liu to improve safety and reliability of a voltage monitoring protection circuit.
Regarding claim 13, Rinne in view of Guo further in view of Liu discloses further wherein the first communication channel is configured to transmit information [Liu, K3 turned on or of] regarding the fault flag transmitted via the second communication channel [Liu, via 11 and 12].
Regarding claim 26, Rinne in view of Guo discloses all the features regarding claim 25 as indicated above. Rinne does not explicitly discloser wherein the second communication channel is configured to transmit a fault flag.
However, Liu discloses wherein the second communication channel [primary second channel winding of 11] is configured to transmit a fault flag [fig. 2, via 12]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne in view of Guo to include the second communication channel is configured to transmit a fault flag as taught by Liu to improve safety and reliability of a voltage monitoring protection circuit.
Regarding claim 27, Rinne in view of Guo further in view of Liu discloses further wherein the first communication channel is configured to transmit information [Liu, K3 turned on or of] regarding the fault flag transmitted via the second communication channel [Liu, via 11 and 12].
Claims 14 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Rinne in view of Guo further in view of Xu et al. (US 20220376629 A1 and Xu hereinafter.).
Regarding claim 14, Rinne discloses all the features regarding claim 1 as indicated above. Rinne does not explicitly disclose wherein the first communication channel includes a first capacitor to provide an isolated capacitive channel across the isolation barrier, the second communication channel includes a second capacitor to provide an isolated capacitive channel across the isolation barrier and a third communication channel comprises an inductive channel via a transformer, wherein the first capacitor has a larger capacitance than the second capacitor, wherein the first capacitor is configured to boost a gate driver circuit and the second capacitor is configured to transmit data in the second communication channel.
However, Guo discloses [fig. 5 and 7] wherein the first communication channel includes a first capacitor to provide an isolated capacitive channel across the isolation barrier [top capacitor shown in fig. 7], the second communication channel includes a second capacitor to provide an isolated capacitive channel across the isolation barrier [bottom capacitor shown in fig. 7]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne to include the first communication channel includes a first capacitor to provide an isolated capacitive channel across the isolation barrier, the second communication channel includes a second capacitor to provide an isolated capacitive channel across the isolation barrier as taught by Guo to improve communication stability in a circuit.
Rinne in view of Guo does not explicitly disclose a third communication channel comprises an inductive channel via a transformer, wherein the first capacitor has a larger capacitance than the second capacitor, wherein the first capacitor is configured to boost a gate driver circuit and the second capacitor is configured to transmit data in the second communication channel.
However, Xu discloses [fig. 2] wherein the first capacitor [C2] is configured to boost a gate driver circuit [C2 part of amplifying circuit, para. 94]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne in view of Guo to include the first capacitor is configured to boost a gate driver circuit as taught by Xu to improve performance of a driving circuit an isolation device.
Rinne in view of Guo further in view of Xu discloses the claimed invention except a third communication channel comprises an inductive channel via a transformer. It would have been obvious to one having ordinary skill in the art before the effective filing date to have this feature due to transformer channels inherently being inductive in nature is well known in the art.
Rinne in view of Guo further in view of Xu discloses the claimed invention except for the first capacitor has a larger capacitance than the second capacitor. It would have been obvious to one having ordinary skill in the art before the effective filing date to have a capacitor being larger in value than a second, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 28, Rinne discloses all the features regarding claim 1 as indicated above. Rinne does not explicitly disclose wherein the first communication channel includes a first capacitor to provide an isolated capacitive channel across the isolation barrier, the second communication channel includes a second capacitor to provide an isolated capacitive channel across the isolation barrier and a third communication channel comprises an inductive channel via a transformer, wherein the first capacitor has a larger capacitance than the second capacitor, wherein the first capacitor is configured to boost a gate driver circuit and the second capacitor is configured to transmit data in the second communication channel.
However, Guo discloses [fig. 5 and 7] wherein the first communication channel includes a first capacitor to provide an isolated capacitive channel across the isolation barrier [top capacitor shown in fig. 7], the second communication channel includes a second capacitor to provide an isolated capacitive channel across the isolation barrier [bottom capacitor shown in fig. 7]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne to include the first communication channel includes a first capacitor to provide an isolated capacitive channel across the isolation barrier, the second communication channel includes a second capacitor to provide an isolated capacitive channel across the isolation barrier as taught by Guo to improve communication stability in a circuit. Rinne in view of Guo does not explicitly disclose a third communication channel comprises an inductive channel via a transformer, wherein the first capacitor has a larger capacitance than the second capacitor, wherein the first capacitor is configured to boost a gate driver circuit and the second capacitor is configured to transmit data in the second communication channel.
However, Xu discloses [fig. 2] wherein the first capacitor [C2] is configured to boost a gate driver circuit [C2 part of amplifying circuit, para. 94]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Rinne in view of Guo to include wherein the first capacitor is configured to boost a gate driver circuit and the second capacitor is configured to transmit data in the second communication channel as taught by Xu to improve performance of a driving circuit an isolation device.
Rinne in view of Guo further in view of Xu discloses the claimed invention except a third communication channel comprises an inductive channel via a transformer. It would have been obvious to one having ordinary skill in the art before the effective filing date to have this feature due to transformer channels inherently being inductive in nature is well known in the art.
Rinne in view of Guo further in view of Xu discloses the claimed invention except for the first capacitor has a larger capacitance than the second capacitor. It would have been obvious to one having ordinary skill in the art before the effective filing date to have a capacitor being larger in value than a second, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Response to Arguments
Applicant's arguments filed 5/15/2026 have been fully considered but they are not persuasive. Regarding claim 1 and similarly claim 15, applicant argues [pg. 3 of Remarks] Rinne does not explicitly disclose an isolated second communication channel, examiner respectfully disagrees.
Applicants claim 1 language reads “an isolated first communication channel connecting a first die … and a second die … wherein the IC package includes an isolation barrier between the first and second die; an isolated second communication channel connecting the first and second die”. Examiner is reading this as two communication channels separated by a single isolation barrier. A communication channel transfers information from one area to another. Rinne discloses transformer 34 [fig. 11] with a primary winding transferring information between Q1/Q2 and Q3/Q4, this primary winding is a single channel that is isolated from die 2 shown in fig. 11 with a first isolation barrier. The secondary winding, coupled to nodes Gx/Sx and level detector 120 is a secondary channel transferring information between nodes Gx and Sx and is isolated from the primary side of 34 with the first isolation barrier.
Similarly with claim 15 reading “providing an isolated first communication channel connecting a first die … and a second die … wherein the IC package includes an isolation barrier between the first and second die”. Examiner is reading this as two communication channels separated by a single isolation barrier. A communication channel transfers information from one area to another. Rinne discloses transformer 34 [fig. 11] with a primary winding transferring information between Q1/Q2 and Q3/Q4, this primary winding is a single channel that is isolated from die 2 shown in fig. 11 with a first isolation barrier. The secondary winding, coupled to nodes Gx/Sx and level detector 120 is a secondary channel transferring information between nodes Gx and Sx and is isolated from the primary side of 34 with the first isolation barrier.
Applicant has provided no claim language for claims 1 and 15 regarding a second isolation barrier that would constitute the second isolation channel they are suggesting. Therefore, Rinne reads on the claims and the rejection still stands.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
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/JAMES G YEAMAN/ Examiner, Art Unit 2836
/TAELOR KIM/ Supervisory Patent Examiner, Art Unit 2836
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