DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-19 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 8-11, 13-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshikawa et al. (“Yoshikawa”, US 2010/0002120) in view of Ejiri (US 2025/0155283) and further in view of Yoshida (US 2012/0228682).
Regarding claim 1, Yoshikawa discloses an analog-to-digital converter of an image sensor, the analog-to-digital converter comprising:
a pixel load connected to a column line connected to a plurality of pixels (Yoshikawa: see fig. 2 and par. [0042], wherein a pixel load connected to a vertical signal line connected to a plurality of pixels);
a pixel signal input terminal configured to receive a pixel signal through the column line (Yoshikawa: see fig. 2 and par. [0046], in which a pixel signal input terminal configured to receive a pixel signal through the column line);
a ramp signal input terminal configured to receive a ramp signal (Yoshikawa: see fig. 2 and par. [0042], note that a ramp signal input terminal configured to receive a ramp signal);
a core amplifier configured to compare the pixel signal with the ramp signal, and output the pixel signal based on a comparison result (Yoshikawa: see fig. 8 and par. [0163], wherein a core amplifier 200 configured to compare the pixel signal with the ramp signal, and output the pixel signal based on a comparison result); and
an auto-zero switching unit configured to initialize the core amplifier (Yoshikawa: see par. [0129], in which an auto-zero switching unit AZ configured to initialize the core amplifier 200),
wherein the core amplifier (200) comprises:
a first comparator configured to compare the pixel signal with the ramp signal (Yoshikawa: see fig. 8 and pars. [0163]-[0164], note that a first comparator 210 configured to compare the pixel signal with the ramp signal), the first comparator (210) comprising:
a first input transistor configured to receive the pixel signal (Yoshikawa: see fig. 8 and par. [0170], wherein the first input transistor NT212 configured to receive the pixel signal VSL); and
a second input transistor configured to receive the ramp signal (Yoshikawa: see fig. 8 and par. [0169], in which a second input transistor NT211 configured to receive the ramp signal RAMP); and
a first load transistor and a second load transistor configured to be connected to the first input transistor and the second input transistor, respectively (Yoshikawa: see fig. 8 and pars. [0166]-[0167], note that a first load transistor PT212 and a second load transistor PT211 configured to be connected to the first input transistor NT 212 and the second input transistor NT211, respectively); and
a second comparator comprising a third input transistor configured to receive an output signal of the first comparator and a third load transistor configured to amplify the output signal (Yoshikawa: see fig. 8 and pars. [0180]-[0181], wherein a second comparator 220 comprising a third input transistor PT221 configured to receive an output signal of the first comparator 210 and a third load transistor NT221 configured to amplify the output signal), and
wherein each of the first load transistor, the second load transistor, the third input transistor, and the third load transistor comprises a planar transistor (Yoshikawa: see fig. 8 and pars. [0002], [0165]-[0166], [0180]-[0182], wherein each of the first load transistor PT212, the second load transistor PT211 , the third input transistor PT221 and the third load transistor NT221 comprises a planar transistor as CMOS transistors).
Yoshikawa does not explicitly disclose that each of the first input transistor and the second input transistor comprises a fin field-effect transistor (FinFET).
However, Ejiri teaches that each of the first input transistor and the second input transistor comprises a fin field-effect transistor (FinFET) (Ejiri: see par. [0185], wherein each of the first input transistor Tn2 and the second input transistor Tn1 comprises a fin field effect transistor in the comparator 210).
One would have been modified to include the first input transistor and the second input transistor as taught by Ejiri in the apparatus of Yoshikawa to have noise characteristic deterioration is suppressed become possible (Ejiri: see par. [0202]).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teaching of Ejiri with the Yoshikawa’s system to include that each of the first input transistor and the second input transistor comprises a fin field-effect transistor.
Yoshidawa in the combination with Ejiri does not explicitly disclose that the planar transistor comprises a gate region, a source region on a substrate, and a drain region, and wherein the gate region faces the source region and the drain region along a single plane parallel to a surface of the substrate.
On the other hand, Yoshida teaches that the planar transistor comprises a gate region, a source region on a substrate, and a drain region, and wherein the gate region faces the source region and the drain region along a single plane parallel to a surface of the substrate (Yoshida: see fig. 17 and par. [0003]).
One would have been modified to include the planar transistor as taught by Yoshida in the apparatus of Yoshikawa and Ejiri to have low cost, simple design and excellent integration.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teaching of Yoshida with the Yoshikawa and Ejiri’s system to include that the planar transistor comprises a gate region, a source region on a substrate, and a drain region, and wherein the gate region faces the source region and the drain region along a single plane parallel to a surface of the substrate.
Regarding claim 3, Yoshikawa in the combination with Ejiri and Yoshida discloses the analog-to-digital converter of claim 1.
Yoshikawa in the combination with Ejiri and Yoshida does not explicitly disclose that the pixel signal input terminal comprises:
a multiplexer connected to a plurality of column lines, and configured to select one of a plurality of pixel signals received through the plurality of column lines;
a pixel signal input transistor configured to operate as a capacitor; and
a first switch connected to an output of the multiplexer and the pixel signal input transistor and configured to provide the pixel signal selected by the multiplexer to the pixel signal input transistor, wherein the first switch comprises the planar transistor.
The Examiner takes Official Notice that “the pixel signal input terminal comprises:
a multiplexer connected to a plurality of column lines, and configured to select one of a plurality of pixel signals received through the plurality of column lines;
a pixel signal input transistor configured to operate as a capacitor; and
a first switch connected to an output of the multiplexer and the pixel signal input transistor and configured to provide the pixel signal selected by the multiplexer to the pixel signal input transistor, wherein the first switch comprises the planar transistor” is well known in the art.
Therefore, it would have been obvious to one of ordinary skill in the art to incorporate that teaching into Yoshikawa, Ejiri and Yoshida’s system to transmit the signal.
The rational to do to is to select which pixel signal to be processed.
Regarding claim 4, Yoshikawa in the combination with Ejiri and Yoshida discloses the analog-to-digital converter of claim 1, wherein the ramp signal input terminal comprises an amplifier, and the amplifier comprises a planar transistor (Yoshikawa: see fig. 8, wherein the ramp signal input terminal comprises an amplifier NT211 and the amplifier comprises a planar transistor).
Regarding claim 5, Yoshikawa in the combination with Ejiri and Yoshida discloses the analog-to-digital converter of claim 1, wherein each of the first load transistor and the second load transistor is a P-channel metal oxide semiconductor (PMOS) transistor (Yoshikawa: see par. [0164], in which each of the first load transistor PT212 and the second load transistor PT211 is a P-channel metal oxide semiconductor transistor).
Regarding claim 6, Yoshikawa in the combination with Ejiri and Yoshida discloses the analog-to-digital converter of claim 1, wherein the third input transistor is a P-channel metal oxide semiconductor (PMOS) transistor and wherein the third load transistor is an N-channel metal oxide semiconductor (NMOS) transistor (Yoshikawa: see fig. 8, wherein the third input transistor PT221 is a P channel metal oxide semiconductor transistor and wherein the third load transistor NT221 is an N-channel metal oxide semiconductor transistor).
Regarding claim 8, Yoshikawa in the combination with Ejiri and Yoshida discloses the analog-to-digital converter of claim 1, wherein the first comparator of the core amplifier is connected to a second switch for adjusting an input of the ramp signal (Yoshikawa: see fig. 8, wherein the first comparator of the core amplifier 200 is connected to a second switch PT 213 for adjusting an input of the ramp signal).
Regarding claim 9, Yoshikawa in the combination with Ejiri and Yoshida discloses the analog-to-digital converter of claim 1, wherein the auto-zero switching unit comprises:
a third switch configured to perform a first initialization operation on the first comparator of the core amplifier (Yoshikawa: see fig. 8 and par. [0236], wherein a third switch PT214 configured to perform a first initialization operation on the first comparator 210 of the core amplifier 200); and
a fourth switch configured to perform a second initialization operation on the second comparator of the core amplifier (Yoshikawa: see fig. 8 and par. [0236], in which a fourth switch NT222 configured to perform a second initialization operation on the second comparator 220 of the core amplifier 200).
Regarding claim 10, Yoshikawa in the combination with Ejiri and Yoshida discloses the analog-to-digital converter of claim 9, wherein each of the third switch and the fourth switch comprises a planar transistor (Yoshikawa: see par. [0093]).
Regarding claim 11, Yoshikawa in the combination with Ejiri and Yoshida discloses an image sensor comprising:
a pixel array connected to a plurality of column lines and comprising a plurality of pixels (Yoshikawa: see par. [0010], wherein the main stream of CMOS image sensors is column-parallel output type sensors which have an FD amplifier at each pixel and which provides an output by selecting a certain row of pixels of the pixel array and simultaneously reading the pixels in the column direction.); and
an analog-to-digital converter configured to convert a plurality of pixel signals output through the plurality of column lines (Yoshikawa: see par. [0034], wherein an analog-to-digital converter configured to convert a plurality of pixel signals output through the plurality of column lines),
wherein the analog-to-digital converter comprises:
a pixel load configured to receive a pixel signal from at least one of the plurality of pixels (Yoshikawa: see fig. 2 and par. [0042], wherein a pixel load configured to receive a pixel signal from at least one of the plurality of pixels);
a pixel signal input terminal configured to select at least one pixel signal, and receive the selected at least one pixel signal (Yoshikawa: see fig. 2 and par. [0046], in which a pixel signal input terminal configured to select at least one pixel signal, and receive the selected at least one pixel signal),
a ramp signal input terminal configured to receive a ramp signal (Yoshikawa: see fig. 2 and par. [0042], note that a ramp signal input terminal configured to receive a ramp signal),
a core amplifier configured to compare the pixel signal with the ramp signal, and output the pixel signal based on a comparison result (Yoshikawa: see fig. 8 and par. [0163], wherein a core amplifier 200 configured to compare the pixel signal with the ramp signal, and output the pixel signal based on a comparison result), and
an auto-zero switching unit configured to perform an initialization operation on the core amplifier (Yoshikawa: see par. [0129], in which an auto-zero switching unit AZ configured to perform an initialization operation on the core amplifier),
wherein the core amplifier comprises:
a first comparator configured to compare the pixel signal with the ramp signal, the first comparator comprising:
a first input transistor configured to receive the pixel signal;
a second input transistor configured to receive the ramp signal; and
a first load transistor and a second load transistor configured to be connected to the first input transistor and the second input transistor, respectively; and
a second comparator comprising a third input transistor configured to receive an output signal of the first comparator and a third load transistor configured to amplify the output signal,
wherein each of the first input transistor and the second input transistor comprises a fin field-effect transistor (FinFET), and
wherein each of the first load transistor, the second load transistor, the third input transistor, and the third load transistor comprises a planar transistor, wherein the planar transistor comprises a gate region, a source region on a substrate, and a drain region, and wherein the gate region faces the source region and the drain region along a single plane parallel to a surface of the substrate (see the analysis of claim 1).
Regarding claim 13, claim 13 recites the similar subject matter as previously discussed in claim 3.
Regarding claim 14, Yoshikawa in the combination with Ejiri and Yoshida discloses the image sensor of claim 11, wherein the ramp signal input terminal comprises an amplifier, and the amplifier comprises a planar transistor (Yoshikawa: see fig. 8, wherein the ramp signal input terminal comprises an amplifier NT211 and the amplifier comprises a planar transistor).
Regarding claim 15, Yoshikawa in the combination with Ejiri and Yoshida discloses the image sensor of claim 11, wherein each of the first load transistor and the second load transistor is a P-channel metal oxide semiconductor (PMOS) transistor (Yoshikawa: see par. [0164], in which each of the first load transistor PT212 and the second load transistor PT211 is a P-channel metal oxide semiconductor transistor).
Regarding claim 16, Yoshikawa in the combination with Ejiri and Yoshida discloses the image sensor of claim 11, wherein the third input transistor is a P-channel metal oxide semiconductor (PMOS) transistor (Yoshikawa: see fig. 8, wherein the third input transistor PT221 is a P channel metal oxide semiconductor transistor).
Regarding claim 17, Yoshikawa in the combination with Ejiri and Yoshida discloses the image sensor of claim 11, wherein the third load transistor is an N-channel metal oxide semiconductor (NMOS) transistor (Yoshikawa: see fig. 8, wherein the third load transistor NT221 is an N-channel metal oxide semiconductor transistor).
Regarding claim 18, Yoshikawa in the combination with Ejiri and Yoshida discloses the analog-to-digital converter of claim 1, wherein the first comparator of the core amplifier is connected to a second switch for adjusting an input of the ramp signal (Yoshikawa: see fig. 8, wherein the first comparator of the core amplifier 200 is connected to a second switch PT 213 for adjusting an input of the ramp signal).
Regarding claim 19, Yoshikawa in the combination with Ejiri and Yoshida discloses the image sensor of claim 11, wherein the auto-zero switching unit comprises:
a third switch configured to perform a first initialization operation on the first comparator (Yoshikawa: see fig. 8 and par. [0236], wherein a third switch PT214 configured to perform a first initialization operation on the first comparator 210 of the core amplifier 200); and
a fourth switch configured to perform a second initialization operation on the second comparator (Yoshikawa: see fig. 8 and par. [0236], in which a fourth switch NT222 configured to perform a second initialization operation on the second comparator 220 of the core amplifier 200).
Regarding claim 21, claim 21 recites the similar subject matter as previously discussed in claim 1. In addition, a pixel signal input terminal configured to select at least one pixel signal, and receive the selected at least one pixel signal can be read on Yoshikawa, fig. 2 and par. [0046].
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshikawa et al. (“Yoshikawa”, US 2010/0002120) in view of Ejiri (US 2025/0155283), Yoshida (US 2012/0228682) and further in view of Sakuma et al. (“Sakuma”, US 2024/0406602).
Regarding claim 2, Yoshikawa in the combination with Ejiri and Yoshida discloses the analog-to-digital converter of claim 1, wherein the pixel load comprises a current source (Yoshikawa: see fig. 1, current source 16).
Yoshikawa in the combination with Ejiri and Yoshida does not explicitly disclose a current source comprising at least one planar transistor.
However, Sakuma teaches a current source comprising at least one planar transistor (Sakuma: see figs. 1-2 and par. [0047], The constant current source section 13 includes a plurality of load current sources I, which includes MOS transistors which is planar transistor).
One would have been modified to include a planar transistor as taught by Sakuma in the apparatus of Yoshikawa, Ejiri and Yoshida to have tiny switches or amplifier with major advances.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teaching of Sakuma with the Yoshikawa, Ejiri and Yoshida’s system to include that a current source comprising at least one planar transistor.
Regarding claim 12, Yoshikawa in the combination with Ejiri and Yoshida discloses the image sensor of claim 11, wherein the pixel load comprises a current source (Yoshikawa: see fig. 1, current source 16).
Yoshikawa in the combination with Ejiri and Yoshida does not explicitly disclose a current source comprising at least one planar transistor.
However, Sakuma teaches a current source comprising at least one planar transistor (Sakuma: see figs. 1-2 and par. [0047], The constant current source section 13 includes a plurality of load current sources I, which includes MOS transistors which is planar transistor).
One would have been modified to include a planar transistor as taught by Sakuma in the apparatus of Yoshikawa, Ejiri and Yoshida to have tiny switches or amplifier with major advances.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teaching of Sakuma with the Yoshikawa, Ejiri and Yoshida’s system to include that a current source comprising at least one planar transistor.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshikawa et al. (“Yoshikawa”, US 2010/0002120) in view of Ejiri (US 2025/0155283), Yoshida (US 2012/0228682) and further in view of He et al. (“He”, US 2003/0183891).
Regarding claim 7, Yoshikawa in the combination with Ejiri and Yoshida discloses the analog-to-digital converter of claim 1, wherein the pixel signal input terminal comprises a first planar input transistor (Yoshikawa: see fig. 8, wherein the pixel signal input terminal comprises a first planar input transistor NT212).
Yoshikawa in the combination with Ejiri and Yoshida does not explicitly disclose the transistor configured to operate as a capacitor.
On the other hand, He teaches that the transistor configured to operate as a capacitor (He: see fig. 1 and par. [0020], wherein the pixel signal input terminal comprises a first planar input transistor 119a/119b configured to operate as a capacitor).
One would have been modified to include a capacitor as taught by He in the apparatus of Yoshikawa, Ejiri and Yoshida to have high capacitance density for space efficiency, low cost and intrinsic integration into CMOS processes.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teaching of He with the Yoshikawa, Ejiri and Yoshida’s system to include a first planar input transistor configured to operate as a capacitor.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAN T H NGUYEN whose telephone number is (571)272-3452. The examiner can normally be reached M-F 8AM-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached at 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHAN T NGUYEN/Patent Examiner, Art Unit 2638
/LIN YE/Supervisory Patent Examiner, Art Unit 2638
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