Prosecution Insights
Last updated: October 02, 2026
Application No. 18/606,609

LANGUAGE MODELS FOR AUTOMATIC MICROBENCHMARK GENERATION

Non-Final OA §101
Filed
Mar 15, 2024
Priority
Mar 31, 2023 — EU 23165987.1
Examiner
DO, AN H
Art Unit
Tech Center
Assignee
Collins Aerospace
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
1322 granted / 1461 resolved
+30.5% vs TC avg
Moderate +7% lift
Without
With
+7.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
26 currently pending
Career history
1474
Total Applications
across all art units

Statute-Specific Performance

§101
11.0%
-29.0% vs TC avg
§103
26.1%
-13.9% vs TC avg
§102
40.3%
+0.3% vs TC avg
§112
4.5%
-35.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1461 resolved cases

Office Action

§101
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 15 March 2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-10 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claim 1 (and dependent claims 2-7) recite “A computer-implemented method comprising: providing a corpus of training data, the corpus of training data comprising a plurality of code portions, each of the plurality of code portions being designed to perform a specific performance testing task for testing performance of a specific processing circuitry within an electronic system having a particular microarchitecture, each of the plurality of code portions being associated with a particular microarchitecture characteristic of a set of microarchitecture characteristics, and wherein each of the plurality of code portions is annotated with respective information indicative of the specific performance testing task that the respective code portion is designed to perform; and training a language model using the provided corpus of training data; receiving as an input to the trained language model a prompt requesting software code for testing the performance of the specific performance testing task of the specific processing circuitry within the electronic system having the particular microarchitecture; generating one or more software portions using the trained language model, wherein the generated one or more software code portions when executed by a processor within the electronic system are configured to perform the specific processing performance testing task for testing performance of the specific processing circuitry within the electronic system.” Claims 1-7, in view of the claim limitations, recite the abstract idea of “providing a corpus of training data, the corpus of training data comprising a plurality of code portions, each of the plurality of code portions being designed to perform a specific performance testing task for testing performance of a specific processing circuitry within an electronic system having a particular microarchitecture, each of the plurality of code portions being associated with a particular microarchitecture characteristic of a set of microarchitecture characteristics, and wherein each of the plurality of code portions is annotated with respective information indicative of the specific performance testing task that the respective code portion is designed to perform; and training a language model using the provided corpus of training data; receiving as an input to the trained language model a prompt requesting software code for testing the performance of the specific performance testing task of the specific processing circuitry within the electronic system having the particular microarchitecture; generating one or more software portions using the trained language model, wherein the generated one or more software code portions when executed by a processor within the electronic system are configured to perform the specific processing performance testing task for testing performance of the specific processing circuitry within the electronic system.” As a whole, in view of the claim limitations, but for the computer components and systems performing the claimed functions, the broadest reasonable interpretation of the recited “providing a corpus of training data, the corpus of training data comprising a plurality of code portions, each of the plurality of code portions being designed to perform a specific performance testing task for testing performance of a specific processing circuitry within an electronic system having a particular microarchitecture, each of the plurality of code portions being associated with a particular microarchitecture characteristic of a set of microarchitecture characteristics, and wherein each of the plurality of code portions is annotated with respective information indicative of the specific performance testing task that the respective code portion is designed to perform; training a language model using the provided corpus of training data; receiving as an input to the trained language model a prompt requesting software code for testing the performance of the specific performance testing task of the specific processing circuitry within the electronic system having the particular microarchitecture; and generating one or more software portions using the trained language model, wherein the generated one or more software code portions when executed by a processor within the electronic system are configured to perform the specific processing performance testing task for testing performance of the specific processing circuitry within the electronic system.”; therefore, the claims recite using machine learning/AI to generate software based on training data and a prompt; and thus, the claims recite an abstract idea under the first prong of Step 2A. Regarding claims 2-4, they do not introduce particular microarchitecture characteristics to generate software code portions as a technical improvement to integrate the abstract idea. Regarding claims 5-7, software code portions are annotated with natural language information and merely provide additional information to a generic AI model. Hence, they do not transform the claims into a technical improvement. Regarding claims 8 and 9, they recite using machine learning/AI to generate software based on training data and a prompt. Hence, they do not transform the claims into a practical application. Regarding claim 10, it recites using machine learning/AI to generate software based on training data and a prompt. It merely provides additional information to a generic AI model. Hence, it does not transform the claim into a practical application. This judicial exception is not integrated into a practical application under the second prong of Step 2A. In particular, the claims recite the additional elements beyond the recited abstract idea of“[a] computer- implemented method” and “the method is carried out by one or more physical processors configured by machine-readable instructions” as recited in claim 10, individually and when viewed as an ordered combination, and pursuant to the broadest reasonable interpretation, each of the additional elements are computing elements recited at high level of generality implementing the abstract idea on a computer (i.e. apply it), and thus, are no more than applying the abstract idea with generic computer components. Moreover, aside from the aforementioned additional elements, the remaining elements of dependent claims 2-7 and 9 do not integrate the abstract idea into a practical application because these claims merely recite further limitations that provide no more than simply narrowing the recited abstract idea. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception under Step 2B. As noted above, the aforementioned additional elements beyond the recited abstract idea, as an order combination, are no more than mere instructions to implement the idea using generic computer components (i.e. apply it), and further, generally link the abstract idea to a field of use, which is not sufficient to amount to significantly more than an abstract idea; therefore, the additional elements are not sufficient to amount to significantly more than an abstract idea. Moreover, aside from the aforementioned additional elements, the remaining elements of dependent claims 2-7 and 9 do not transform the recited abstract idea into a patent eligible invention because these claims merely recite further limitations that provide no more than simply narrowing the recited abstract idea. Looking at these limitations as an ordered combination adds nothing additional that is sufficient to amount to significantly more than the recited abstract idea because they simply provide instructions to use a generic arrangement of generic computer components and recitations of generic computer structure that perform well-understood, routine, and conventional computer functions that are used to “apply” the recited abstract idea. Thus, the elements of the claims, considered both individually and as an ordered combination, are not sufficient to ensure that the claim as a whole amounts to significantly more than the abstract idea itself. Since there are no limitations in these claims that transform the exception into a patent eligible application such that these claims amount to significantly more than the exception itself, claims 1-10 are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bird et al (US 11,715,006) disclose a natural language code search service that provides idioms or frequently-occurring code patterns for a code fragment based on similar type usage and method/API invocation usage. Trim et al (US 11,455,148) disclose a method that includes: receiving a natural language command from an operator; determining a programming language in which to program the task by analyzing a plurality of factors; and outputting code in the programming language that executes the task. Waltenberg et al (US 10,956,137) disclose a method that includes: receiving a source code and architecture information for at least one data processing environment in which a first executable program code compiled from the source code is to be configured to be executed; compiling the source code to generate the first executable program code; selecting, using a processor, from a plurality of source code transformations, a source code transformation to apply to compile a portion of the source code based on a plurality of sets of benchmark data, each of the sets of benchmark data including data indicating an efficiency of a portion of another executable program code compiled using a respective source code transformation at executing in the at least one data processing environment. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to AN H DO whose telephone number is (571)272-2143. The examiner can normally be reached on M-F 7:00am-4:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ricardo Magallanes can be reached on 571-272-5960. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AN H DO/Primary Examiner, Art Unit 2853
Read full office action

Prosecution Timeline

Mar 15, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §101 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
98%
With Interview (+7.0%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1461 resolved cases by this examiner. Grant probability derived from career allowance rate.

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