DETAILED ACTION
This Office Action, based on application 18/606,742 filed 15 March 2024, is filed in response to applicant’s amendment and remarks filed 13 November 2025. Claims 1-20 are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks, filed 13 November 2025 in response to the Office Action mailed 1 October 2025, have been fully considered below.
Claim Rejections under 35 U.S.C. § 103
The applicant traverses the prior art rejection to the claims alleging cited prior art does not teach or suggest each and every element of the independent claims as amended (however, the Office respectfully notes no amendment appears to have been presented in the response filed 13 November 2025).
On Pages 7-8, the applicant alleges the following:
From Applicant's review, Wu merely describes "different termination times or different durations" (Paragraph [0134]; Wu) of an erase pulse, which is simultaneously applied to all world lines of an erase block (See Paragraph [0126] of WU stating "Generally, during an erase operation, an erase pulse is initiated on the word lines of an erase block at about the same time. In certain embodiments, the length or duration of the word line erase pulse 906 varies per word line or per group of word lines."). Moreover, Wu explicitly states, at paragraph [0042], that "[t]he memory block, in some implementations, may be the smallest erasable unit of the memory device, as shown in FIG. 1", which indicates that all word lines within the block are subject to the same erase operation as Applicant previously argued. Wu expressly states that every word line in an erase block is subjected to a single, common erase operation. Therefore, there is no evidence that Wu can erase only a subset of those word lines while leaving others untouched during that same operation-such selective erasure would require non-overlapping erase pulse timings that Wu does not disclose.
In response, the Office maintains applicant’s remarks are renewed remarks previously addressed in the ‘Response to Arguments’ section of the Office Action mailed 1 October 2025. The Office remains unpersuaded by applicant’s remarks and maintains the previous response.
On Pages 8-12, the applicant alleges cited prior art fails to disclose the limitation “applying the relatively high voltage to the source line” as recited (or similarly recited in the independent claims. Applicant’s remarks allege the following:
“However, YANG does not instruct the controller to pump the common source-line (SL 454 shown in Figure 4). Alternatively speaking, in YANG, SL is mentioned only in structural descriptions and in program-mode pre-charge discussions. During erase the SL simply floats or follows the channel potential set by the p-well, so its voltage is incidental, not an actively driven node.”
Regarding the teachings of WU particularly at Paragraph [0071], the applicant alleges the following: “Here, WU does not explicitly state a voltage level of a voltage applied to a source line during an erase operation. However, even assuming arguendo that “the erase voltage/erase pulse 908” applied “to the memory channel 530” is generally analogous to the voltage applied to the source line (alternatively referred to as source line voltage), Paragraph [0071] clearly states that “[t]he erase pulse 908 may have a higher maximum value than the WL sel pulse 906. For example, during the erase operation, the erase pulse 908 could reach a maximum value of 12.6V whereas the WL_sel pulse 906 could reach only 0.5V”.
In response to (1), the applicant first asserts YANG is silent in regards to what happens to SL during erasures since the source line is only mentioned in structural descriptions and programming. Then, the applicant asserts how SL behaves during erasures without any basis for the assertion; the Office is not persuaded by applicant’s remarks that suggest SL’s behavior during erasures due to lack of evidence. Even if applicant’s assertion were true, prior art including HEMINK (US PGPub 2008/0117684) states at ¶[0064] that during an erase operation of a flash memory, “Each word line is grounded and while the source line … are {is} allowed to float. An erase voltage Verase (e.g. 20V) is applied to the p-well. Due to capacitive coupling … the source line are {is} also raised to a high positive potential (e.g. 20V).”. In response to (2), the Office notes the rejection of record does not rely on WU to explicitly state a voltage level; instead the rejection of record relies on YANG’s teachings at Fig 9 and ¶[0120-0121] stating that an erase voltage may be 20V and the erase voltage may be applied to the NAND channels during an erase. While the Office concedes YANG may not explicitly disclose the source of the erase voltage applied to the NAND channels during an erase, the Office notes WU at ¶[0038] further states “the substrate voltage may be supplied via the source line to the memory channel of a set of memory cells, such as a memory string” further providing evidence the source line may provide the voltage to the channels. While the applicant notes a statement from ¶[0071] of WU, the Office notes the statement is a mere embodiment of WU and does not provide evidence that contradicts the limitation. The Office maintains the combination of WU and YANG’s teachings teach or suggest the cited claim element.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-11, 13, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over WU et al (US PGPub 2020/0211652) in further view of BERT (US PGPub 2021/0405898) and YANG et al (US PGPub 2024/0055051).
With respect to Claim 1, WU discloses an apparatus, comprising:
a memory array comprising a plurality of strings of memory cells coupled between a bit line and a source line (Fig 1, Memory Structure 126; ¶[0058] – “The memory die 108 includes a memory structure 126 of memory cells such as an array of memory cells”; ¶[0060] – “the memory structure 126 may comprise a set of memory cells comprising a memory channel … the set of memory cells may comprise a memory string”; ¶[0038] – “memory cells may be joined to one another such as in NAND strings in a block or sub-block”; Fig 4 illustrates BL0-3 {‘bit lines’} and SL0-3 {‘source lines’}; ¶[0110-0112] describe the bit lines and source lines), wherein each string of the plurality of strings comprises:
a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block (¶[0134] – “the word lines {‘a first group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘first group of memory cells’} that can be selectively erased … as discussed above using different word lines”); and
a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block (¶[0134] – “the word lines {‘a second group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a second set of word lines coupled to the memory channel may be grouped into a second zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘second group of memory cells’} that can be selectively erased … as discussed above using different word lines”);
wherein the first erase block is configured as a first zone of one or more zones independently of the second erase block (¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘first zone’} that can be selectively {thus, ‘independently’} erased … as discussed above using different word lines”).
WU may not explicitly disclose wherein the one or more zones correspond to a zoned namespace (ZNS) and wherein each erase block of the first and second erase blocks of each string is selectable to be erased independently of the other erase block by: applying a relatively low voltage to the first group of access lines of the first erase block that is selected to be erased; applying a relatively high voltage greater than the relatively low voltage to the second group of access lines of the second erase block that is not selected to be erased; and applying the relatively high voltage to the source line.
However, BERT discloses wherein the one or more zones correspond to a zone namespace (ZNS) (¶[0013] – “Certain memory devices are also configured with a zone namespace. In a zone namespace, the address space of the memory device is divided into zones”).
WU and BERT are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU and BERT before him or her, to modify the zone groupings of the memory array of WU to include associating the zones with a namespace as taught by BERT. A motivation for doing so would have been to allow for more efficient management of data as the capacity of the memory device increases (¶[0013]). Therefore, it would have been obvious to combine WU and BERT to obtain the invention as specified in the instant claims.
WU and BERT may not explicitly disclose wherein each erase block of the first and second erase blocks of each string is selectable to be erased independently of the other erase block by: applying a relatively low voltage to the first group of access lines of the first erase block that is selected to be erased; applying a relatively high voltage greater than the relatively low voltage to the second group of access lines of the second erase block that is not selected to be erased; and applying the relatively high voltage to the source line..
However, YANG discloses wherein each erase block of the first and second erase blocks of each string is selectable to be erased independently of the other erase block (¶[0153] – “The method comprises operating a block having NAND strings and word lines in a half NAND string mode in which a group of word lines in the block provide electrical isolation between a first set of data word lines connected to memory cells on a bottom section of the NAND strings and a second set of data word lines connected to memory cells on a top section of the NAND strings, including erasing the memory cells connected to the first set of data word lines independent of erasing the memory cells connected to the second set of data word lines while biasing the group of the word lines to provide electrical isolation between the first set and the second set of data word lines”) by: applying a relatively low voltage to the first group of access lines of the first erase block that is selected to be erased (Fig 9, Step 920 – “Apply erase enable voltage on all data WLs in selected sub-block”; ¶[0119] – “the erase of a memory cell includes applying an erase voltage (e.g. 0V) to the control gate of the memory cell”); applying a relatively high voltage greater than the relatively low voltage to the second group of access lines of the second erase block that is not selected to be erased (Fig 9, Step 922 – “Apply erase inhibit voltage on all data WLs in unselected sub-block”; ¶[0119] – “A memory cell that has the erase voltage applied to its channel (body) may be inhibited from erase by applying an erase inhibit voltage (e.g. the erase voltage or about 20V) to its control gate”); and applying the relatively high voltage to the source line (Fig 9, Step 918 – “Apply erase voltage to NAND channels”; ¶[0121] – “Another approach to erasing memory cells is to generate gate induced drain leakage (GIDL) current to charge up the NAND string channel. An erase enable voltage is applied to control gates of the memory cells, while maintaining the string channel potential to erase the memory cells”; ¶[0120] – an erase voltage may be 20V; WU at ¶[0065] states “The source line driver may be configured to raise a voltage of the substrate in relation to a change in the voltage of the bit line controlled by the bit line driver, which charges up the memory channel to an erase voltage threshold.”).
WU, BERT, and YANG are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU, BERT, and YANG before him or her, to modify the control circuits of the combination of WU and BERT to operate a block in half NAND string mode as taught by YANG. A motivation for doing so would have been to prevent over-erasing of memory cells of the string. Therefore, it would have been obvious to combine WU, BERT, and YANG to obtain the invention as specified in the instant claims.
With respect to Claim 9, WU discloses an apparatus, comprising:
a memory array comprising a plurality of first strings of memory cells coupled between a bit line and a source line and corresponding at least to a first block (Fig 1, Memory Structure 126; ¶[0058] – “The memory die 108 includes a memory structure 126 of memory cells such as an array of memory cells”; ¶[0060] – “the memory structure 126 may comprise a set of memory cells comprising a memory channel … the set of memory cells may comprise a memory string”; ¶[0038] – “memory cells may be joined to one another such as in NAND strings in a block or sub-block”; Fig 4 illustrates BL0-3 {‘bit lines’} and SL0-3 {‘source lines’}; ¶[0110-0112] describe the bit lines and source lines), the first block further comprises:
a first erase block configured as a first zone and comprising a first group of memory cells coupled to a first group of access lines (¶[0134] – “the word lines {‘a first group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘first group of memory cells’} that can be selectively erased … as discussed above using different word lines”); and
a second erase block configured as not being part of the first zone and comprising a second group of access lines and corresponding to a second erase block (¶[0134] – “the word lines {‘a second group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a second set of word lines coupled to the memory channel may be grouped into a second zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘second group of memory cells’} that can be selectively erased … as discussed above using different word lines”).
WU may not explicitly disclose wherein the memory array is organized as a zoned namespace (ZNS) with the first zone corresponding to the ZNS, and wherein each erase block of the first and second erase blocks of the first block is selectable to be erased independently of the other erase block by: applying a relatively low voltage to the first group of access lines of the first erase block that is selected to be erased; applying a relatively high voltage greater than the relatively low voltage to the second group of access lines of the second erase block that is not selected to be erased; and applying the relatively high voltage to the source line.
However, BERT discloses wherein the memory array is organized as a zoned namespace (ZNS) with the first zone corresponding to the ZNS (¶[0013] – “Certain memory devices are also configured with a zone namespace. In a zone namespace, the address space of the memory device is divided into zones”).
WU and BERT are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU and BERT before him or her, to modify the zone groupings of the memory array of WU to include associating the zones with a namespace as taught by BERT. A motivation for doing so would have been to allow for more efficient management of data as the capacity of the memory device increases (¶[0013]). Therefore, it would have been obvious to combine WU and BERT to obtain the invention as specified in the instant claims.
WU and BERT may not explicitly disclose wherein each erase block of the first and second erase blocks of the first block is selectable to be erased independently of the other erase block by: applying a relatively low voltage to the first group of access lines of the first erase block that is selected to be erased; applying a relatively high voltage greater than the relatively low voltage to the second group of access lines of the second erase block that is not selected to be erased; and applying the relatively high voltage to the source line.
However, YANG discloses wherein each erase block of the first and second erase blocks of the first block is selectable to be erased independently of the other erase block (¶[0153] – “The method comprises operating a block having NAND strings and word lines in a half NAND string mode in which a group of word lines in the block provide electrical isolation between a first set of data word lines connected to memory cells on a bottom section of the NAND strings and a second set of data word lines connected to memory cells on a top section of the NAND strings, including erasing the memory cells connected to the first set of data word lines independent of erasing the memory cells connected to the second set of data word lines while biasing the group of the word lines to provide electrical isolation between the first set and the second set of data word lines”) by: applying a relatively low voltage to the first group of access lines of the first erase block that is selected to be erased (Fig 9, Step 920 – “Apply erase enable voltage on all data WLs in selected sub-block”; ¶[0119] – “the erase of a memory cell includes applying an erase voltage (e.g. 0V) to the control gate of the memory cell”); applying a relatively high voltage greater than the relatively low voltage to the second group of access lines of the second erase block that is not selected to be erased (Fig 9, Step 922 – “Apply erase inhibit voltage on all data WLs in unselected sub-block”; ¶[0119] – “A memory cell that has the erase voltage applied to its channel (body) may be inhibited from erase by applying an erase inhibit voltage (e.g. the erase voltage or about 20V) to its control gate”); and applying the relatively high voltage to the source line (Fig 9, Step 918 – “Apply erase voltage to NAND channels”; ¶[0121] – “Another approach to erasing memory cells is to generate gate induced drain leakage (GIDL) current to charge up the NAND string channel. An erase enable voltage is applied to control gates of the memory cells, while maintaining the string channel potential to erase the memory cells”; ¶[0120] – an erase voltage may be 20V; WU at ¶[0065] states “The source line driver may be configured to raise a voltage of the substrate in relation to a change in the voltage of the bit line controlled by the bit line driver, which charges up the memory channel to an erase voltage threshold.”).
WU, BERT, and YANG are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU, BERT, and YANG before him or her, to modify the control circuits of the combination of WU and BERT to operate a block in half NAND string mode as taught by YANG. A motivation for doing so would have been to prevent over-erasing of memory cells of the string. Therefore, it would have been obvious to combine WU, BERT, and YANG to obtain the invention as specified in the instant claims.
With respect to Claim 18, WU discloses a method, comprising:
configuring a first erase block of a memory array as a first zone of the memory array, wherein the first erase block comprises a first group of memory cells coupled to a first group of access lines and at least to a first string of a plurality of strings of the memory array coupled between a bit line and a source line (¶[0134] – “the word lines {‘a first group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘first group of memory cells’} that can be selectively erased … as discussed above using different word lines”; Fig 4 illustrates BL0-3 {‘bit lines’} and SL0-3 {‘source lines’}; ¶[0110-0112] describe the bit lines and source lines); and
configuring a second erase block of the memory array as a second zone of the memory array, wherein the second erase block comprises a second group of memory cells coupled to a second group of access lines and at least to the first string of the plurality of strings of the memory array (¶[0134] – “the word lines {‘a second group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a second set of word lines coupled to the memory channel may be grouped into a second zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘second group of memory cells’} that can be selectively erased … as discussed above using different word lines”).
WU may not explicitly disclose wherein the memory array is organized as a zoned namespace (ZNS) and wherein the first zone and the second zone correspond to the ZNS, and wherein each erase block of the first and second erase blocks that are coupled to the first string is selectable to be erased independently of the other erase block by: applying a relatively low voltage to the first group of access lines of the first erase block that is selected to be erased; applying a relatively high voltage greater than the relatively low voltage to the second group of access lines of the second erase block that is not selected to be erased; and applying the relatively high voltage to the source line.
However, BERT discloses wherein the memory array is organized as a zoned namespace (ZNS) (¶[0013] – “Certain memory devices are also configured with a zone namespace. In a zone namespace, the address space of the memory device is divided into zones”).
WU and BERT are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU and BERT before him or her, to modify the zone groupings of the memory array of WU to include associating the zones with a namespace as taught by BERT. A motivation for doing so would have been to allow for more efficient management of data as the capacity of the memory device increases (¶[0013]). Therefore, it would have been obvious to combine WU and BERT to obtain the invention as specified in the instant claims.
WU and BERT may not explicitly disclose wherein each erase block of the first and second erase blocks that are coupled to the first string is selectable to be erased independently of the other erase block by: applying a relatively low voltage to the first group of access lines of the first erase block that is selected to be erased; applying a relatively high voltage greater than the relatively low voltage to the second group of access lines of the second erase block that is not selected to be erased; and applying the relatively high voltage to the source line.
However, YANG discloses wherein each erase block of the first and second erase blocks of each string is selectable to be erased independently of the other erase block (¶[0153] – “The method comprises operating a block having NAND strings and word lines in a half NAND string mode in which a group of word lines in the block provide electrical isolation between a first set of data word lines connected to memory cells on a bottom section of the NAND strings and a second set of data word lines connected to memory cells on a top section of the NAND strings, including erasing the memory cells connected to the first set of data word lines independent of erasing the memory cells connected to the second set of data word lines while biasing the group of the word lines to provide electrical isolation between the first set and the second set of data word lines”) by: applying a relatively low voltage to the first group of access lines of the first erase block that is selected to be erased (Fig 9, Step 920 – “Apply erase enable voltage on all data WLs in selected sub-block”; ¶[0119] – “the erase of a memory cell includes applying an erase voltage (e.g. 0V) to the control gate of the memory cell”); applying a relatively high voltage greater than the relatively low voltage to the second group of access lines of the second erase block that is not selected to be erased (Fig 9, Step 922 – “Apply erase inhibit voltage on all data WLs in unselected sub-block”; ¶[0119] – “A memory cell that has the erase voltage applied to its channel (body) may be inhibited from erase by applying an erase inhibit voltage (e.g. the erase voltage or about 20V) to its control gate”); and applying the relatively high voltage to the source line (Fig 9, Step 918 – “Apply erase voltage to NAND channels”; ¶[0121] – “Another approach to erasing memory cells is to generate gate induced drain leakage (GIDL) current to charge up the NAND string channel. An erase enable voltage is applied to control gates of the memory cells, while maintaining the string channel potential to erase the memory cells”; ¶[0120] – an erase voltage may be 20V; WU at ¶[0065] states “The source line driver may be configured to raise a voltage of the substrate in relation to a change in the voltage of the bit line controlled by the bit line driver, which charges up the memory channel to an erase voltage threshold.”).
WU, BERT, and YANG are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU, BERT, and YANG before him or her, to modify the control circuits of the combination of WU and BERT to operate a block in half NAND string mode as taught by YANG. A motivation for doing so would have been to prevent over-erasing of memory cells of the string. Therefore, it would have been obvious to combine WU, BERT, and YANG to obtain the invention as specified in the instant claims.
With respect to Claim 2, the combination of WU, BERT, and YANG disclose the apparatus of claim 1.
WU further discloses wherein the memory array comprises a plurality of blocks, each block of the plurality of blocks is configured as at least two different zones (¶[0098] – “each block can be divided into sub-blocks, and each sub-block includes multiple NAND strings”; the word lines and memory cells of a string may be grouped into multiple zones per ¶[0134-0135] as noted above).
BERT further discloses wherein the memory array is organized as the ZNS (¶[0013] – “Certain memory devices are also configured with a zone namespace. In a zone namespace, the address space of the memory device is divided into zones”).
With respect to Claim 3, the combination of WU, BERT, and YANG disclose the apparatus of claim 1.
WU further discloses wherein at least one zone of the one or more zones corresponds to a block size, wherein memory cells corresponding to more than one erase blocks are configured as the at least one zone (¶[0134] – “the word lines of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {the number of memory cells in a unit or a unit itself may be characterized as a ‘block size’} that can be selectively erased … as discussed above using different word lines”).
With respect to Claim 4, the combination of WU, BERT, and YANG disclose the apparatus of claim 1.
WU further discloses wherein the second erase block is configured as a second zone of the one or more zones (¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘second zone’} that can be selectively erased … as discussed above using different word lines”).
BERT further discloses wherein the one or more zones correspond to the ZNS (¶[0013] – “Certain memory devices are also configured with a zone namespace. In a zone namespace, the address space of the memory device is divided into zones”).
With respect to Claim 5, the combination of WU, BERT, and YANG disclose the apparatus of claim 1.
WU further discloses wherein each zone of the one or more zones comprises at least two erase blocks of the memory array (¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells that can be selectively erased … as discussed above using different word lines”).
With respect to Claim 6, the combination of WU, BERT, and YANG disclose the apparatus of claim 1.
WU further discloses wherein the memory array further comprises a third group of access lines located between the respective first groups of access lines and the respective second groups of access lines (¶[0134] – “a third set of word lines coupled to the memory channel may also be grouped into a third zone, etc.”).
With respect to Claim 7, the combination of WU, BERT, and YANG disclose the apparatus of claim 6.
WU further discloses wherein the third group of access lines are dummy access lines coupled to memory cells that are not used to store user data (¶[0041] – memory cells can include … dummy or non-data memory cells which are ineligible to store user data. A dummy word line is connected to a dummy word cell”).
With respect to Claim 8, the combination of WU, BERT, and YANG disclose the apparatus of claim 1, wherein the memory array is a three dimensional (3D) array (¶[0059] – “The memory structure 126 can be multidimensional e.g. 2D or 3D”) of NAND flash memory cells (¶[0002-0003] reference 3D-NAND devices as flash storage) with the first group of memory cells and the second group of memory cells of each string sharing a common channel region (¶[0134] – “the word lines of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone; a second set of word lines coupled to the memory channel may in turn be grouped into a second zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells that can be selectively erased … as discussed above using different word lines”).
With respect to Claim 10, the combination of WU, BERT, and YANG disclose the apparatus of claim 9.
WU further discloses wherein the second erase block is configured as a second zone (¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘second zone’} that can be selectively erased … as discussed above using different word lines”).
BERT further discloses wherein the second zone corresponds to the ZNS (¶[0098] – “each block can be divided into sub-blocks, and each sub-block includes multiple NAND strings”; the word lines and memory cells of a string may be grouped into multiple zones per ¶[0134-0135] as noted above).
With respect to Claim 11, the combination of WU, BERT, and YANG disclose the apparatus of claim 10.
WU further discloses wherein the plurality of first strings corresponds to a first plane of the memory array (¶[0092] – “in a 3D NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g. x-y) memory device level”; Fig 4 depicts strings 401n, 411n, 421n, and 431n all on the same level or plane; ¶[0110]), and wherein the memory array further comprises: a plurality of second strings of memory cells coupled between a bit line and a source line and corresponding to a second plane of the memory array (¶[0092] – “in a 3D NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g. x-y) memory device level”; Fig 4 depicts strings 402n, 412n, 422n, and 432n all on the same level or plane; Fig 4 illustrates BL0-3 {‘bit lines’} and SL0-3 {‘source lines’}; ¶[0110-0112] describe the bit lines and source lines) and a second block, the second block further comprises: a third erase block configured as the first zone and comprising a third group of memory cells coupled to a third group of access lines (Fig 1, Memory Structure 126; ¶[0058] – “The memory die 108 includes a memory structure 126 of memory cells such as an array of memory cells”; ¶[0060] – “the memory structure 126 may comprise a set of memory cells comprising a memory channel … the set of memory cells may comprise a memory string”; ¶[0038] – “memory cells may be joined to one another such as in NAND strings in a block or sub-block”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘first zone’} that can be selectively {thus, ‘independently’} erased … as discussed above using different word lines”); and a fourth erase block configured as the second zone and comprising a fourth group of memory cells coupled to a fourth group of access lines (Fig 1, Memory Structure 126; ¶[0058] – “The memory die 108 includes a memory structure 126 of memory cells such as an array of memory cells”; ¶[0060] – “the memory structure 126 may comprise a set of memory cells comprising a memory channel … the set of memory cells may comprise a memory string”; ¶[0038] – “memory cells may be joined to one another such as in NAND strings in a block or sub-block”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘second zone’} that can be selectively {thus, ‘independently’} erased … as discussed above using different word lines”);
BERT further discloses wherein the first zone and the second zone correspond to the ZNS (¶[0098] – “each block can be divided into sub-blocks, and each sub-block includes multiple NAND strings”; the word lines and memory cells of a string may be grouped into multiple zones per ¶[0134-0135] as noted above).
With respect to Claim 13, the combination of WU, BERT, and YANG disclose the apparatus of claim 11.
WU further discloses a controller coupled to the memory array (Fig 1 illustrates Control Circuit 110 coupled to Memory Array 126), the controller configured to access the first erase block and the third erase block configured as the first zone substantially simultaneously (¶[0125] – “Three example groups of word lines (top WLs, middle WLs, and bottom WLs) are depicted. The erase circuit respectively applies different erase pulses to the different groups of word lines, while simultaneously applying an erase voltage to the bit line of the memory channel during the erase operation {all blocks of a zone may be said to be accessed ‘substantially simultaneously’ since a voltage may be applied to a group of word lines while applying a voltage to the bit line of the memory channel}).
With respect to Claim 17, the combination of WU, BERT, and YANG disclose the apparatus of claim 9.
WU further discloses wherein the first group of access lines corresponding to the first erase block is physically separated from the second group of access lines corresponding to the second erase block (¶[0134] – “the word lines of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone, a second set of word lines coupled to the memory channel may be grouped into a second zone {the first set and second set of word lines may be ‘physically separated’ since they may be selectively erased}”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells that can be selectively erased … as discussed above using different word lines”) by a number of access lines (¶[0134] – “a third set of word lines coupled to the memory channel may also be grouped into a third zone, etc.”) coupled to memory cells that are not used to store data (¶[0041] – memory cells can include … dummy or non-data memory cells which are ineligible to store user data. A dummy word line is connected to a dummy word cell”).
With respect to Claim 19, the combination of WU, BERT, and YANG disclose the method of claim 18.
WU further discloses configuring a third erase block of the memory array as the first zone of the memory array, wherein the third erase block comprises a third group of memory cells coupled to a third group of access lines and at least to a second string of the plurality of strings of the memory array (Fig 1, Memory Structure 126; ¶[0058] – “The memory die 108 includes a memory structure 126 of memory cells such as an array of memory cells”; ¶[0060] – “the memory structure 126 may comprise a set of memory cells comprising a memory channel … the set of memory cells may comprise a memory string”; ¶[0038] – “memory cells may be joined to one another such as in NAND strings in a block or sub-block”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘first zone’} that can be selectively {thus, ‘independently’} erased … as discussed above using different word lines”); and accessing the first zone by accessing the first and third erase blocks substantially simultaneously (¶[0125] – “Three example groups of word lines (top WLs, middle WLs, and bottom WLs) are depicted. The erase circuit respectively applies different erase pulses to the different groups of word lines, while simultaneously applying an erase voltage to the bit line of the memory channel during the erase operation {all blocks of a zone may be said to be accessed ‘substantially simultaneously’ since a voltage may be applied to a group of word lines while applying a voltage to the bit line of the memory channel}).
BERT further discloses wherein the first zone corresponds to the ZNS (¶[0098] – “each block can be divided into sub-blocks, and each sub-block includes multiple NAND strings”; the word lines and memory cells of a string may be grouped into multiple zones per ¶[0134-0135] as noted above).
With respect to Claim 20, the combination of WU, BERT, and YANG disclose the method of claim 18.
WU further discloses configuring a fourth erase block of the memory array as the second zone of the memory array, wherein the fourth erase block comprises a fourth group of memory cells coupled to a fourth group of access lines and at least to a second string of the plurality of strings of the memory array (Fig 1, Memory Structure 126; ¶[0058] – “The memory die 108 includes a memory structure 126 of memory cells such as an array of memory cells”; ¶[0060] – “the memory structure 126 may comprise a set of memory cells comprising a memory channel … the set of memory cells may comprise a memory string”; ¶[0038] – “memory cells may be joined to one another such as in NAND strings in a block or sub-block”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘second zone’} that can be selectively {thus, ‘independently’} erased … as discussed above using different word lines”); and accessing the second zone by accessing the second and fourth erase blocks substantially simultaneously (¶[0125] – “Three example groups of word lines (top WLs, middle WLs, and bottom WLs) are depicted. The erase circuit respectively applies different erase pulses to the different groups of word lines, while simultaneously applying an erase voltage to the bit line of the memory channel during the erase operation {all blocks of a zone may be said to be accessed ‘substantially simultaneously’ since a voltage may be applied to a group of word lines while applying a voltage to the bit line of the memory channel}).
BERT further discloses wherein the second zone corresponds to the ZNS (¶[0098] – “each block can be divided into sub-blocks, and each sub-block includes multiple NAND strings”; the word lines and memory cells of a string may be grouped into multiple zones per ¶[0134-0135] as noted above).
Claim(s) 12 and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over WU in further view of BERT, YANG, and CARIELLO (US PGPub 2020/0333976).
With respect to Claim 12, the combination of WU, BERT, and YANG disclose the apparatus of claim 11.
WU, BERT, and YANG may not explicitly disclose wherein the memory array is organized as a plurality of logical units (LUNs), and wherein the first, second, third, and fourth erase blocks are included in a same LUN of the plurality of LUNs.
However, CARIELLO discloses wherein the memory array is organized as a plurality of logical units (LUNs) (¶[0003] – “A storage system, such as a solid-state drive (SSD), can include a memory controller and one or more memory devices, including a number of (e.g.. multiple) dies or logical units (LUNs)”; ¶[0025] – “the non-volatile memory device can include a number of non-volatile memory devices (e.g. dies or LUNs) such as one or more stacked flash memory devices, each including non-volatile memory (NVM) and a device controller or other periphery circuitry thereon (e.g. device logic, etc.) and controlled by the memory controller over an internal storage-system communication interface”), and wherein the first, second, third, and fourth erase blocks are included in a same LUN of the plurality of LUNs (¶[0003], ¶[0025]; ¶[0017] – “multiple zones (e.g. sub-groups of memory cells, or one or more groups of memory cells from a block, a window, a plane, a memory devices, etc) can be determined based on temperature uniformity, such that operations in a specific zone or range of zones can be performed with a high degree of uniformity, such that a single (or small number) of temperature compensations can apply across groups of memory cells within the zone”).
WU, BERT, YANG, and CARIELLO are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU, BERT, YANG, and CARIELLO before him or her, to modify the memory device of the combination of WU, BERT, and YANG to include flash memory device stacking as taught by CARIELLO. A motivation for doing so would have been to increase capacity of the storage device. Therefore, it would have been obvious to combine WU, BERT, YANG, and CARIELLO to obtain the invention as specified in the instant claims.
With respect to Claim 14, the combination of WU, BERT, and YANG disclose the apparatus of claim 11.
WU, BERT, and YANG may not explicitly disclose wherein the memory array is organized as a plurality of logical units (LUNs), and wherein the first and third erase blocks are included in different LUNs of the plurality of LUNs.
However, CARIELLO discloses wherein the memory array is organized as a plurality of logical units (LUNs) (¶[0003] – “A storage system, such as a solid-state drive (SSD), can include a memory controller and one or more memory devices, including a number of (e.g.. multiple) dies or logical units (LUNs)”; ¶[0025] – “the non-volatile memory device can include a number of non-volatile memory devices (e.g. dies or LUNs) such as one or more stacked flash memory devices, each including non-volatile memory (NVM) and a device controller or other periphery circuitry thereon (e.g. device logic, etc.) and controlled by the memory controller over an internal storage-system communication interface”), and wherein the first and third erase blocks are included in different LUNs of the plurality of LUNs (¶[0003], ¶[0025]; ¶[0017] – “multiple zones (e.g. sub-groups of memory cells, or one or more groups of memory cells from a block, a window, a plane, a memory devices, etc) can be determined based on temperature uniformity, such that operations in a specific zone or range of zones can be performed with a high degree of uniformity, such that a single (or small number) of temperature compensations can apply across groups of memory cells within the zone”).
WU, BERT, YANG, and CARIELLO are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU, BERT, YANG, and CARIELLO before him or her, to modify the memory device of the combination of WU, BERT, and YANG to include flash memory device stacking as taught by CARIELLO. A motivation for doing so would have been to increase capacity of the storage device. Therefore, it would have been obvious to combine WU, BERT, YANG, and CARIELLO to obtain the invention as specified in the instant claims.
With respect to Claim 15, the combination of WU, BERT, YANG, and CARIELLO disclose the apparatus of claim 14.
CARIELLO further discloses wherein the second and fourth erase blocks are included in different LUNs of the plurality of LUNs (¶[0003], ¶[0025]; ¶[0017] – “multiple zones (e.g. sub-groups of memory cells, or one or more groups of memory cells from a block, a window, a plane, a memory devices, etc) can be determined based on temperature uniformity, such that operations in a specific zone or range of zones can be performed with a high degree of uniformity, such that a single (or small number) of temperature compensations can apply across groups of memory cells within the zone”).
With respect to Claim 16, the combination of WU, BERT, YANG, and CARIELLO disclose the apparatus of claim 14.
CARIELLO further discloses wherein the second and fourth erase blocks are included in a same LUN of the plurality of LUNs (¶[0003], ¶[0025]; ¶[0017] – “multiple zones (e.g. sub-groups of memory cells, or one or more groups of memory cells from a block, a window, a plane, a memory devices, etc) can be determined based on temperature uniformity, such that operations in a specific zone or range of zones can be performed with a high degree of uniformity, such that a single (or small number) of temperature compensations can apply across groups of memory cells within the zone”).
Conclusion
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/ERIC T LOONAN/Examiner, Art Unit 2137