DETAILED ACTION
This Office Action, based on application 18/606,742 filed 15 March 2024, is filed in response to applicant’s amendment and remarks filed 14 April 2026. Claims 1-10, 12, 14-18, and 20 are currently pending and have been fully considered below.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 26 May 2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks, filed 14 April 2026 in response to the Office Action mailed 25 February 2026, have been fully considered below.
Claim Rejections under 35 U.S.C. § 103
The applicant traverses the prior art rejection to the claims alleging cited prior art does not teach or suggest each and every element of the independent claims as amended. Specifically, on Page 9 of applicant’s remarks, the applicant alleges cited prior art fails to disclose “the first erase block and the third erase block of different physical blocks substantially simultaneously to erase the first zone” since the pulses are allegedly not directed to different physical blocks. The Office has reviewed applicant’s remarks on Pages 8-9 discussing applicant’s interpretation of a physical block of the claims and prior art teachings; however, is not persuaded and maintains cited prior art teaches the limitation for reasons now presented in the rejection of record. The Office submits the broadest reasonable interpretation of a ‘physical block’ is merely a collection or group of storage units in a storage device. What may be referred to as a ‘block’ by one person may be referred to as a “page’, ‘sector’, ‘plane’, ‘partition’, ‘device’, ‘zone’, ‘chip’, ‘array’, ‘sub-block’, ‘super block’, etc. (or even generic terms like ‘unit’ or ‘group’). The Office presents new grounds of rejection responsive to applicant’s amendment below. The Office further notes applicant’s filing is non-responsive to the remarks presented in the Advisory Action posted 29 April 2026 noting inconsistences in terms of memory units between independent claims; the Office has presented indefiniteness rejections and objections for the applicant to clarify the inconsistencies in used claim language.
Claim Objections
The following claim(s) is/are objected to due to informalities:
Claim 1: “the controller configured to, to selectable erase …” should simply be “the controller configured to selectable erase …”. Change “to, to” => “to”.
Claim 6: The claim references “a third group of access lines”; however, Claim 1 was amended to include the same term. If the terms are meant to be the same, then the term should recite “the third group of access lines”; otherwise, the terms should be distinguished. Note Claim 7 further limits “the third group of access lines” to be dummy lines which may be inconsistent with parent Claim 1’s ‘second physical block’.
Claim 9: “the controller configured to, to selectable erase …” should simply be “the controller configured to selectable erase …”. Change “to, to” => “to”.
Claim 9: Both Lines 4 and 11 recite “a second plane”. The Office notes the claim isn’t limited to “a first plane”. If the planes on Lines 4 and 11 are the same plane, then “a second plane” on Line 11 should be “the second plane” to properly reflect antecedent basis of the term.
Claim 9: Lack of antecedent basis of the term “the second zone”. (Line 15)
Claim 18: Independent Claims 1 and 9 are directed to “a first physical block comprising a first erase block and a second erase block” and “a second physical block comprising a third erase block and a fourth erase block”. Claim 18 is directed to “a first erase block of a first physical block”, “a second erase block of a second physical block” and “a third erase block of a third physical block”. Does the originally filed specification support both organizations? Why the difference? Shouldn’t the first physical block of Claim 18 comprise the first erase block and the second erase block?
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10, 12, and 14-17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 (and similarly Claim 9) recites the limitation “the controller configured to selectably erase each erase block of the first and second erase blocks of each string independently of the other erase block”. There is lack of antecedent basis of the following terms: (1) “the first and second erase blocks of each string” and (2) “the other erase block”. Regarding (1), while antecedent basis exists for a first portion of the plurality of strings comprising a first physical block comprising a first erase block and a second erase block, antecedent basis does not exist for more than one first erase block or more than one second erase block. Term (1) recites more than one first erase block and more than one second erase block since the blocks correspond to ‘each string’ and the claim is limited to ‘a plurality of strings’. Regarding (2), “the other erase block” could refer to any erase block including “a third erase block”.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-10 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over WU et al (US PGPub 2020/0211652) in further view of BERT (US PGPub 2021/0405898), YANG et al (US PGPub 2024/0055051), and AGRAWAL (US PGPub 2022/0334747).
With respect to Claim 1, WU discloses an apparatus, comprising:
a memory array comprising a plurality of strings of memory cells coupled between a bit line and a source line (Fig 1, Memory Structure 126; ¶[0058] – “The memory die 108 includes a memory structure 126 of memory cells such as an array of memory cells”; ¶[0060] – “the memory structure 126 may comprise a set of memory cells comprising a memory channel … the set of memory cells may comprise a memory string”; ¶[0038] – “memory cells may be joined to one another such as in NAND strings in a block or sub-block”; Fig 4 illustrates BL0-3 {‘bit lines’} and SL0-3 {‘source lines’}; ¶[0110-0112] describe the bit lines and source lines), wherein:
a first portion of the plurality of strings (Fig 4 depicts multiple strings 401n, 402n, etc.) comprises a first physical block comprising:
a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block (¶[0134] – “the word lines {‘a first group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘first group of memory cells’} that can be selectively erased … as discussed above using different word lines”); and
a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block (¶[0134] – “the word lines {‘a second group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a second set of word lines coupled to the memory channel may be grouped into a second zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘second group of memory cells’} that can be selectively erased … as discussed above using different word lines”);
a second portion of the plurality of strings (Fig 4 depicts multiple strings 401n, 402n, etc.) comprises a second physical block comprising:
a third group of memory cells coupled to a third group of access lines and corresponding to a third erase block (¶[0134] – “the word lines {‘a third group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘third group of memory cells’} that can be selectively erased … as discussed above using different word lines”); and
a fourth group of memory cells coupled to a fourth group of access lines and corresponding to a fourth erase block (¶[0134] – “the word lines {‘a fourth group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a second set of word lines coupled to the memory channel may be grouped into a second zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘fourth group of memory cells’} that can be selectively erased … as discussed above using different word lines”),
wherein the first erase block and the third erase block are configured as a first zone of one or more zones independently of the second erase block. (¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘first zone’} that can be selectively {thus, ‘independently’} erased … as discussed above using different word lines”).
WU may not explicitly disclose wherein the one or more zones correspond to a zoned namespace (ZNS), a controller coupled to the memory array, the controller configured to, to selectably erase each erase block of the first and second erase blocks of each string independently of the other erase block, and wherein the controller is further configured to access the first erase block and the third erase block of different physical blocks substantially simultaneously to erase the first zone.
However, BERT discloses wherein the one or more zones correspond to a zone namespace (ZNS) (¶[0013] – “Certain memory devices are also configured with a zone namespace. In a zone namespace, the address space of the memory device is divided into zones”).
WU and BERT are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU and BERT before him or her, to modify the zone groupings of the memory array of WU to include associating the zones with a namespace as taught by BERT. A motivation for doing so would have been to allow for more efficient management of data as the capacity of the memory device increases (¶[0013]). Therefore, it would have been obvious to combine WU and BERT to obtain the invention as specified in the instant claims.
WU and BERT may not explicitly disclose a controller coupled to the memory array, the controller configured to, to selectably erase each erase block of the first and second erase blocks of each string independently of the other erase block, and wherein the controller is further configured to access the first erase block and the third erase block of different physical blocks substantially simultaneously to erase the first zone.
However, YANG discloses a controller coupled to the memory array, the controller configured to, to selectably erase each erase block of the first and second erase blocks of each string independently of the other erase block (¶[0153] – “The method comprises operating a block having NAND strings and word lines in a half NAND string mode in which a group of word lines in the block provide electrical isolation between a first set of data word lines connected to memory cells on a bottom section of the NAND strings and a second set of data word lines connected to memory cells on a top section of the NAND strings, including erasing the memory cells connected to the first set of data word lines independent of erasing the memory cells connected to the second set of data word lines while biasing the group of the word lines to provide electrical isolation between the first set and the second set of data word lines”).
WU, BERT, and YANG are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU, BERT, and YANG before him or her, to modify the control circuits of the combination of WU and BERT to operate a block in half NAND string mode as taught by YANG. A motivation for doing so would have been to prevent over-erasing of memory cells of the string. Therefore, it would have been obvious to combine WU, BERT, and YANG to obtain the invention as specified in the instant claims.
WU, BERT, and YANG may not explicitly disclose wherein the controller is further configured to access the first erase block and the third erase block of different physical blocks substantially simultaneously to erase the first zone.
However, AGRAWAL discloses wherein the controller is further configured to access the first erase block and the third erase block of different physical blocks substantially simultaneously to erase the first zone (¶[0037] – “the present disclosure provides for the provisioning of a first partition in flash memory having multiple dies as channels that is allocated to very low-sized zones to perform storage operations across all dies in parallel, where each block (or sub-block) in a die is allocated as a lowest level of erase unit for the first partition”; ¶[0101] – “the controller 123 may write data across multiple dies in parallel that are allocated to the first zone”).
WU, BERT, YANG, and AGRAWAL are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU, BERT, YANG, and AGRAWAL before him or her, to modify the control circuits of the combination of WU, BERT, and YANG to enable erasure of multiple blocks of a zone in parallel as taught by AGRAWAL. A motivation for doing so would have been to achieve maximum performance of the storage operations shortening the time window for performing the collective operations on the blocks (¶[0033]). Therefore, it would have been obvious to combine WU, BERT, YANG, and AGRAWAL to obtain the invention as specified in the instant claims.
With respect to Claim 9, WU discloses an apparatus, comprising:
a memory array comprising:
a plurality of first strings of memory cells coupled between a bit line and a source line and corresponding to a second plane of the memory array (¶[0092] – “in a 3D NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g. x-y) memory device level”; Fig 4 depicts strings 401n, 411n, 421n, and 431n all on the same level or plane; ¶[0110]) and a first block (Fig 1, Memory Structure 126; ¶[0058] – “The memory die 108 includes a memory structure 126 of memory cells such as an array of memory cells”; ¶[0060] – “the memory structure 126 may comprise a set of memory cells comprising a memory channel … the set of memory cells may comprise a memory string”; ¶[0038] – “memory cells may be joined to one another such as in NAND strings in a block or sub-block”; Fig 4 illustrates BL0-3 {‘bit lines’} and SL0-3 {‘source lines’}; ¶[0110-0112] describe the bit lines and source lines), the first block further comprises:
a first erase block configured as a first zone and comprising a first group of memory cells coupled to a first group of access lines (¶[0134] – “the word lines {‘a first group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘first group of memory cells’} that can be selectively erased … as discussed above using different word lines”); and
a second erase block configured as not being part of the first zone and comprising a second group of access lines and corresponding to a second erase block (¶[0134] – “the word lines {‘a second group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a second set of word lines coupled to the memory channel may be grouped into a second zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘second group of memory cells’} that can be selectively erased … as discussed above using different word lines”);
a plurality of second strings of memory cells coupled between a bit line and a source line and corresponding to a second plane of the memory array (¶[0092] – “in a 3D NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g. x-y) memory device level”; Fig 4 depicts strings 401n, 411n, 421n, and 431n all on the same level or plane; ¶[0110]) and a second block (Fig 1, Memory Structure 126; ¶[0058] – “The memory die 108 includes a memory structure 126 of memory cells such as an array of memory cells”; ¶[0060] – “the memory structure 126 may comprise a set of memory cells comprising a memory channel … the set of memory cells may comprise a memory string”; ¶[0038] – “memory cells may be joined to one another such as in NAND strings in a block or sub-block”; Fig 4 illustrates BL0-3 {‘bit lines’} and SL0-3 {‘source lines’}; ¶[0110-0112] describe the bit lines and source lines), the second block further comprises:
a third erase block configured as the first zone and comprising a third group of memory cells coupled to a third group of access lines (¶[0134] – “the word lines {‘a third group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘third group of memory cells’} that can be selectively erased … as discussed above using different word lines”); and
a fourth erase block configured as the second zone and comprising a fourth group of access lines coupled to a fourth group of access lines (¶[0134] – “the word lines {‘a fourth group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a second set of word lines coupled to the memory channel may be grouped into a second zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘fourth group of memory cells’} that can be selectively erased … as discussed above using different word lines”).
WU may not explicitly disclose wherein the memory array is organized as a zoned namespace (ZNS) with the first zone and the second zone corresponding to the ZNS, a controller coupled to the memory array, the controller configured to, to selectably erase each erase block of the first and second erase blocks of each string independently of the other erase block, and wherein the controller is further configured to access the first erase block and the third erase block of different planes and configured as the first zone substantially simultaneously.
However, BERT discloses wherein the memory array is organized as a zoned namespace (ZNS) with the first zone and the second zone corresponding to the ZNS (¶[0013] – “Certain memory devices are also configured with a zone namespace. In a zone namespace, the address space of the memory device is divided into zones”).
WU and BERT are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU and BERT before him or her, to modify the zone groupings of the memory array of WU to include associating the zones with a namespace as taught by BERT. A motivation for doing so would have been to allow for more efficient management of data as the capacity of the memory device increases (¶[0013]). Therefore, it would have been obvious to combine WU and BERT to obtain the invention as specified in the instant claims.
WU and BERT may not explicitly disclose a controller coupled to the memory array, the controller configured to, to selectably erase each erase block of the first and second erase blocks of each string independently of the other erase block, and wherein the controller is further configured to access the first erase block and the third erase block of different planes and configured as the first zone substantially simultaneously.
However, YANG discloses a controller coupled to the memory array, the controller configured to, to selectably erase each erase block of the first and second erase blocks of each string independently of the other erase block (¶[0153] – “The method comprises operating a block having NAND strings and word lines in a half NAND string mode in which a group of word lines in the block provide electrical isolation between a first set of data word lines connected to memory cells on a bottom section of the NAND strings and a second set of data word lines connected to memory cells on a top section of the NAND strings, including erasing the memory cells connected to the first set of data word lines independent of erasing the memory cells connected to the second set of data word lines while biasing the group of the word lines to provide electrical isolation between the first set and the second set of data word lines”).
WU, BERT, and YANG are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU, BERT, and YANG before him or her, to modify the control circuits of the combination of WU and BERT to operate a block in half NAND string mode as taught by YANG. A motivation for doing so would have been to prevent over-erasing of memory cells of the string. Therefore, it would have been obvious to combine WU, BERT, and YANG to obtain the invention as specified in the instant claims.
WU, BERT, and YANG may not explicitly disclose wherein the controller is further configured to access the first erase block and the third erase block of different planes and configured as the first zone substantially simultaneously.
However, AGRAWAL discloses wherein the controller is further configured to access the first erase block and the third erase block of different planes and configured as the first zone substantially simultaneously (¶[0037] – “the present disclosure provides for the provisioning of a first partition in flash memory having multiple dies as channels that is allocated to very low-sized zones to perform storage operations across all dies in parallel, where each block (or sub-block) in a die is allocated as a lowest level of erase unit for the first partition”; ¶[0101] – “the controller 123 may write data across multiple dies in parallel that are allocated to the first zone”).
WU, BERT, YANG, and AGRAWAL are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU, BERT, YANG, and AGRAWAL before him or her, to modify the control circuits of the combination of WU, BERT, and YANG to enable erasure of multiple blocks of a zone in parallel as taught by AGRAWAL. A motivation for doing so would have been to achieve maximum performance of the storage operations shortening the time window for performing the collective operations on the blocks (¶[0033]). Therefore, it would have been obvious to combine WU, BERT, YANG, and AGRAWAL to obtain the invention as specified in the instant claims.
With respect to Claim 2, the combination of WU, BERT, YANG, and AGRAWAL disclose the apparatus of claim 1.
WU further discloses wherein the memory array comprises a plurality of blocks, each block of the plurality of blocks is configured as at least two different zones (¶[0098] – “each block can be divided into sub-blocks, and each sub-block includes multiple NAND strings”; the word lines and memory cells of a string may be grouped into multiple zones per ¶[0134-0135] as noted above).
BERT further discloses wherein the memory array is organized as the ZNS (¶[0013] – “Certain memory devices are also configured with a zone namespace. In a zone namespace, the address space of the memory device is divided into zones”).
With respect to Claim 3, the combination of WU, BERT, YANG, and AGRAWAL disclose the apparatus of claim 1.
WU further discloses wherein at least one zone of the one or more zones corresponds to a block size, wherein memory cells corresponding to more than one erase blocks are configured as the at least one zone (¶[0134] – “the word lines of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {the number of memory cells in a unit or a unit itself may be characterized as a ‘block size’} that can be selectively erased … as discussed above using different word lines”).
With respect to Claim 4, the combination of WU, BERT, YANG, and AGRAWAL disclose the apparatus of claim 1.
WU further discloses wherein the second erase block is configured as a second zone of the one or more zones (¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘second zone’} that can be selectively erased … as discussed above using different word lines”).
BERT further discloses wherein the one or more zones correspond to the ZNS (¶[0013] – “Certain memory devices are also configured with a zone namespace. In a zone namespace, the address space of the memory device is divided into zones”).
With respect to Claim 5, the combination of WU, BERT, YANG, and AGRAWAL disclose the apparatus of claim 1.
WU further discloses wherein each zone of the one or more zones comprises at least two erase blocks of the memory array (¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells that can be selectively erased … as discussed above using different word lines”).
With respect to Claim 6, the combination of WU, BERT, YANG, and AGRAWAL disclose the apparatus of claim 1.
WU further discloses wherein the memory array further comprises a third group of access lines located between the respective first groups of access lines and the respective second groups of access lines (¶[0134] – “a third set of word lines coupled to the memory channel may also be grouped into a third zone, etc.”).
With respect to Claim 7, the combination of WU, BERT, YANG, and AGRAWAL disclose the apparatus of claim 6.
WU further discloses wherein the third group of access lines are dummy access lines coupled to memory cells that are not used to store user data (¶[0041] – memory cells can include … dummy or non-data memory cells which are ineligible to store user data. A dummy word line is connected to a dummy word cell”).
With respect to Claim 8, the combination of WU, BERT, YANG, and AGRAWAL disclose the apparatus of claim 1, wherein the memory array is a three dimensional (3D) array (¶[0059] – “The memory structure 126 can be multidimensional e.g. 2D or 3D”) of NAND flash memory cells (¶[0002-0003] reference 3D-NAND devices as flash storage) with the first group of memory cells and the second group of memory cells of each string sharing a common channel region (¶[0134] – “the word lines of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone; a second set of word lines coupled to the memory channel may in turn be grouped into a second zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells that can be selectively erased … as discussed above using different word lines”).
With respect to Claim 10, the combination of WU, BERT, YANG, and AGRAWAL disclose the apparatus of claim 9.
WU further discloses wherein the second erase block is configured as a second zone (¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘second zone’} that can be selectively erased … as discussed above using different word lines”).
BERT further discloses wherein the second zone corresponds to the ZNS (¶[0098] – “each block can be divided into sub-blocks, and each sub-block includes multiple NAND strings”; the word lines and memory cells of a string may be grouped into multiple zones per ¶[0134-0135] as noted above).
With respect to Claim 17, the combination of WU, BERT, YANG, and AGRAWAL disclose the apparatus of claim 9.
WU further discloses wherein the first group of access lines corresponding to the first erase block is physically separated from the second group of access lines corresponding to the second erase block (¶[0134] – “the word lines of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone, a second set of word lines coupled to the memory channel may be grouped into a second zone {the first set and second set of word lines may be ‘physically separated’ since they may be selectively erased}”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells that can be selectively erased … as discussed above using different word lines”) by a number of access lines (¶[0134] – “a third set of word lines coupled to the memory channel may also be grouped into a third zone, etc.”) coupled to memory cells that are not used to store data (¶[0041] – memory cells can include … dummy or non-data memory cells which are ineligible to store user data. A dummy word line is connected to a dummy word cell”).
Claim(s) 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over WU in further view of BERT and AGRAWAL.
With respect to Claim 18, WU discloses a method, comprising:
configuring a first erase block of a first physical block of a memory array as a first zone of the memory array, wherein the first erase block comprises a first group of memory cells coupled to a first group of access lines and to a first string of a plurality of strings of the memory array coupled between a bit line and a source line (¶[0134] – “the word lines {‘a first group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘first group of memory cells’} that can be selectively erased … as discussed above using different word lines”; Fig 4 illustrates BL0-3 {‘bit lines’} and SL0-3 {‘source lines’}; ¶[0110-0112] describe the bit lines and source lines);
configuring a second erase block of a second physical block of the memory array as a second zone of the memory array, wherein the second erase block comprises a second group of memory cells coupled to a second group of access lines and to the first string of the plurality of strings of the memory array (¶[0134] – “the word lines {‘a second group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a second set of word lines coupled to the memory channel may be grouped into a second zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘second group of memory cells’} that can be selectively erased … as discussed above using different word lines”); and
configuring a third erase block of a third physical block of the memory array as the first zone of the memory array, wherein the third erase block comprises a third group of memory cells coupled to a third group of access lines and to a second string of the plurality of strings of the memory array (¶[0134] – “the word lines {‘a third group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a first set of word lines coupled to the memory channel may be grouped into a first zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘third group of memory cells’} that can be selectively erased … as discussed above using different word lines”).
WU may not explicitly disclose wherein the memory array is organized as a zoned namespace (ZNS) and wherein the first zone and the second zone correspond to the ZNS, and erasing the first zone by accessing the first zone by accessing the first and third erase blocks of different physical blocks substantially simultaneously.
However, BERT discloses wherein the memory array is organized as a zoned namespace (ZNS) and wherein the first zone and the second zone correspond to the ZNS (¶[0013] – “Certain memory devices are also configured with a zone namespace. In a zone namespace, the address space of the memory device is divided into zones”).
WU and BERT are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU and BERT before him or her, to modify the zone groupings of the memory array of WU to include associating the zones with a namespace as taught by BERT. A motivation for doing so would have been to allow for more efficient management of data as the capacity of the memory device increases (¶[0013]). Therefore, it would have been obvious to combine WU and BERT to obtain the invention as specified in the instant claims.
WU and BERT may not explicitly disclose erasing the first zone by accessing the first zone by accessing the first and third erase blocks of different physical blocks substantially simultaneously.
However, AGRAWAL discloses wherein the controller is further configured to access the first erase block and the third erase block of different planes and configured as the first zone substantially simultaneously (¶[0037] – “the present disclosure provides for the provisioning of a first partition in flash memory having multiple dies as channels that is allocated to very low-sized zones to perform storage operations across all dies in parallel, where each block (or sub-block) in a die is allocated as a lowest level of erase unit for the first partition”; ¶[0101] – “the controller 123 may write data across multiple dies in parallel that are allocated to the first zone”).
WU, BERT, and AGRAWAL are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU, BERT, and AGRAWAL before him or her, to modify the control circuits of the combination of WU and BERT to enable erasure of multiple blocks of a zone in parallel as taught by AGRAWAL. A motivation for doing so would have been to achieve maximum performance of the storage operations shortening the time window for performing the collective operations on the blocks (¶[0033]). Therefore, it would have been obvious to combine WU, BERT, and AGRAWAL to obtain the invention as specified in the instant claims.
With respect to Claim 20, the combination of WU, BERT, and AGRAWAL disclose the method of claim 18.
WU further discloses configuring a fourth erase block of the memory array as the second zone of the memory array, wherein the fourth erase block comprises a fourth group of memory cells coupled to a fourth group of access lines and at least to a second string of the plurality of strings of the memory array (¶[0134] – “the word lines {‘a fourth group of access lines’} of a given memory string may be grouped into zones that can be selectively erased … for example, a second set of word lines coupled to the memory channel may be grouped into a second zone”; ¶[0135] – “the memory cells of the memory device 100 may be grouped into units of memory cells {‘fourth group of memory cells’} that can be selectively erased … as discussed above using different word lines”).
BERT further discloses wherein the second zone corresponds to the ZNS (¶[0098] – “each block can be divided into sub-blocks, and each sub-block includes multiple NAND strings”; the word lines and memory cells of a string may be grouped into multiple zones per ¶[0134-0135] as noted above).
AGRAWAL discloses accessing the second zone by accessing the second and fourth erase blocks substantially simultaneously (¶[0037] – “the present disclosure provides for the provisioning of a first partition in flash memory having multiple dies as channels that is allocated to very low-sized zones to perform storage operations across all dies in parallel, where each block (or sub-block) in a die is allocated as a lowest level of erase unit for the first partition”; ¶[0101] – “the controller 123 may write data across multiple dies in parallel that are allocated to the first zone”).
Claim(s) 12 and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over WU in further view of BERT, YANG, AGRAWAL, and CARIELLO (US PGPub 2020/0333976).
With respect to Claim 12, the combination of WU, BERT, YANG, and AGRAWAL disclose the apparatus of claim 9.
WU, BERT, YANG, and AGRAWAL may not explicitly disclose wherein the memory array is organized as a plurality of logical units (LUNs), and wherein the first, second, third, and fourth erase blocks are included in a same LUN of the plurality of LUNs.
However, CARIELLO discloses wherein the memory array is organized as a plurality of logical units (LUNs) (¶[0003] – “A storage system, such as a solid-state drive (SSD), can include a memory controller and one or more memory devices, including a number of (e.g.. multiple) dies or logical units (LUNs)”; ¶[0025] – “the non-volatile memory device can include a number of non-volatile memory devices (e.g. dies or LUNs) such as one or more stacked flash memory devices, each including non-volatile memory (NVM) and a device controller or other periphery circuitry thereon (e.g. device logic, etc.) and controlled by the memory controller over an internal storage-system communication interface”), and wherein the first, second, third, and fourth erase blocks are included in a same LUN of the plurality of LUNs (¶[0003], ¶[0025]; ¶[0017] – “multiple zones (e.g. sub-groups of memory cells, or one or more groups of memory cells from a block, a window, a plane, a memory devices, etc) can be determined based on temperature uniformity, such that operations in a specific zone or range of zones can be performed with a high degree of uniformity, such that a single (or small number) of temperature compensations can apply across groups of memory cells within the zone”).
WU, BERT, YANG, AGRAWAL, and CARIELLO are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU, BERT, YANG, AGRAWAL, and CARIELLO before him or her, to modify the memory device of the combination of WU, BERT, YANG, and AGRAWAL to include flash memory device stacking as taught by CARIELLO. A motivation for doing so would have been to increase capacity of the storage device. Therefore, it would have been obvious to combine WU, BERT, YANG, AGRAWAL, and CARIELLO to obtain the invention as specified in the instant claims.
With respect to Claim 14, the combination of WU, BERT, YANG, and AGRAWAL disclose the apparatus of claim 9.
WU, BERT, YANG, and AGRAWAL may not explicitly disclose wherein the memory array is organized as a plurality of logical units (LUNs), and wherein the first and third erase blocks are included in different LUNs of the plurality of LUNs.
However, CARIELLO discloses wherein the memory array is organized as a plurality of logical units (LUNs) (¶[0003] – “A storage system, such as a solid-state drive (SSD), can include a memory controller and one or more memory devices, including a number of (e.g.. multiple) dies or logical units (LUNs)”; ¶[0025] – “the non-volatile memory device can include a number of non-volatile memory devices (e.g. dies or LUNs) such as one or more stacked flash memory devices, each including non-volatile memory (NVM) and a device controller or other periphery circuitry thereon (e.g. device logic, etc.) and controlled by the memory controller over an internal storage-system communication interface”), and wherein the first and third erase blocks are included in different LUNs of the plurality of LUNs (¶[0003], ¶[0025]; ¶[0017] – “multiple zones (e.g. sub-groups of memory cells, or one or more groups of memory cells from a block, a window, a plane, a memory devices, etc) can be determined based on temperature uniformity, such that operations in a specific zone or range of zones can be performed with a high degree of uniformity, such that a single (or small number) of temperature compensations can apply across groups of memory cells within the zone”).
WU, BERT, YANG, AGRAWAL, and CARIELLO are analogous art because they are from the same field of endeavor of computer memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of WU, BERT, YANG, AGRAWAL, and CARIELLO before him or her, to modify the memory device of the combination of WU, BERT, YANG, and AGRAWAL to include flash memory device stacking as taught by CARIELLO. A motivation for doing so would have been to increase capacity of the storage device. Therefore, it would have been obvious to combine WU, BERT, YANG, AGRAWAL, and CARIELLO to obtain the invention as specified in the instant claims.
With respect to Claim 15, the combination of WU, BERT, YANG, AGRAWAL, and CARIELLO disclose the apparatus of claim 14.
CARIELLO further discloses wherein the second and fourth erase blocks are included in different LUNs of the plurality of LUNs (¶[0003], ¶[0025]; ¶[0017] – “multiple zones (e.g. sub-groups of memory cells, or one or more groups of memory cells from a block, a window, a plane, a memory devices, etc) can be determined based on temperature uniformity, such that operations in a specific zone or range of zones can be performed with a high degree of uniformity, such that a single (or small number) of temperature compensations can apply across groups of memory cells within the zone”).
With respect to Claim 16, the combination of WU, BERT, YANG, AGRAWAL, and CARIELLO disclose the apparatus of claim 14.
CARIELLO further discloses wherein the second and fourth erase blocks are included in a same LUN of the plurality of LUNs (¶[0003], ¶[0025]; ¶[0017] – “multiple zones (e.g. sub-groups of memory cells, or one or more groups of memory cells from a block, a window, a plane, a memory devices, etc) can be determined based on temperature uniformity, such that operations in a specific zone or range of zones can be performed with a high degree of uniformity, such that a single (or small number) of temperature compensations can apply across groups of memory cells within the zone”).
Conclusion
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/ERIC T LOONAN/Examiner, Art Unit 2137
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