DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The Examiner acknowledges Applicant’s amendments and remarks filed on 23 September 2025. They have been fully considered and are persuasive in part. The amendments are sufficient to overcome the rejection based on 35 U.S.C. 112(b). However, the new claim language has necessitated new grounds for rejection under 35 U.S.C. 112(a). Additionally, the amendments are not sufficient to differentiate the invention from the prior art, and Applicant’s arguments are not persuasive to overcome the associated prior art rejections.
On pp. 9 of the filed remarks, Applicant presented the following argument:
Heo describes using different "clock division ratios" to generate the respective signals. However, Heo does not describe "an operating set of clock divide factors" and "a plurality of stored sets of clock divide factors." For at least failing to describe storing a plurality of stored sets of divide factors, Heo fails to describe an operating set of clock divide factors of the plurality of stored sets of divide factors. As Heo fails to disclose these limitations of independent claim 1, it also fails to disclose other limitations that recite these phrases.
The Examiner respectfully disagrees. Heo teaches that clock divider 132 includes one or more registers storing clock division ratio information [para. 0045: “…the clock divider 132 may include one or more register(s) storing clock division ratio information that defines one or more clock division ratio(s).”], and that specific clock division ratios may be selected based on an SVD alarm signal [“…a first clock division ratio value may be set as a default to generate the operating clock CLK having the first frequency (f1) that is provided to the CPU 134 during normal battery conditions, as indicated by the negative SVD alarm signal… a second clock division ratio may be set to generate the operating clock having the second frequency (f2) that is provided to the CPU 134 during low battery conditions, as indicated by the positive SVD alarm signal.”]. Heo additionally teaches that separate clocks may be provided to a CPU and GPU, each having its own clock division ratio [para. 0091: “…the clock divider 332 may divide a source clock using one clock division ratio to generate a first operating clock provided to the CPU 334, and also divide the source clock using a second clock division ratio to generate a second operating clock provided to the GPU 336.”], and that the previously disclosed alarm signal may be used to trigger different ratios [“…in response to a received alarm signal(s) the respective operating clocks may be adjusted differently and/or according to different adjustment timing.”]. Because Heo teaches that the CPU and GPU employ different clock divide ratios, Heo discloses “an operating set of clock divide factors”. And because Heo also teaches that the clock divider includes registers storing clock divide ratios, also teaches that different ratios may be selected based on an alarm signal, Heo also discloses “a plurality of stored sets of clock divide factors”.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 has been amended to recite a clock controller producing respective clock signals using a respective clock divide factor of a plurality of clock divide factors in an operating set of clock divide factors, the operating set being one of a plurality of stored sets of clock divide factors. The broadest reasonable interpretation (BRI) of the amended claim language identifies at least three groups of clock divide factors: a plurality (that is part of an operating set), the operating set (that is part of a plurality of stored sets), and the plurality of stored sets. More specifically, the BRI allows for the plurality to be construed as a specific subset of the operating set because the claim language recites “a plurality of clock divide factors in an operating set of clock divide factors”. The specification fails to identify a specific plurality of clock divide factors that are subset of the operating set.
The specification teaches that smart clock controller SCC 266 [Fig. 5 and 6] provides the set of clock divide factors N1 to Nk used to produce respective clock signals using a respective clock divide factors from the set of N1 to Nk [para. 0084-0086, 0101]. The specification additionally teaches that SCC 266 includes sets of registers which hold sets of clock divide factors N1 to Nk that may be selectively provided (using MUX 277) based on different operating conditions [para. 0103-0109]. The claimed “plurality of stored sets” corresponds to the disclosed sets of clock divide factors N1 to Nk stored in registers 272. The disclosed clock divide factors N1 to Nk that are selected from the registers 272 and output from MUX 277 may reasonably be interpreted as either the claimed “plurality of clock divide factors” or the claimed “operating set of clock divide factors”. However, the specification does not identify another set of clock divide factors that would support the claim’s recitation of both “the plurality” and the “operating set” as distinct groups.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 9-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Heo et al., U.S. Patent Application Publication No. 2023/0276367.
Regarding claim 1, Heo discloses a circuit [Fig. 1, 14] comprising a plurality of peripherals [Fig. 1: CPUs 134; Fig. 14: CPUs 334 and GPU 336] configured to be clocked with a respective clock signal [Fig. 1 and 14: CPUs and GPU receive respective clock signals from CLK divider 132/332] of a plurality of clock signals [i.e., CPU and GPU clock together comprise the set of “a plurality of clock signals”], wherein the circuit comprises:
a clock controller configured to produce each respective clock signal of the plurality of clock signals via a respective clock divide factor of a plurality of clock divide factors in an operating set of clock divide factors [para. 0045, 0091: for a given instance of time, the clock divide ratios currently in effect for the CPU and GPU constitute “an operating set”], wherein the operating set of clock divide factors is one of a plurality of stored sets of clock divide factors, the clock controller having stored therein the plurality of stored sets of clock divide factors [para. 0045: “… the clock divider 132 may include one or more register(s) storing clock division ratio information that defines one or more clock division ratio(s)”],
wherein the clock controller comprises a clock divide factor selection circuitry1 configured to select the operating set of clock divide factors out of the plurality of stored sets of clock divide factors [para. 0045: “…a first clock division ratio value may be set as a default to generate the operating clock CLK having the first frequency (f1)… a second clock division ratio may be set to generate the operating clock having the second frequency (f2)…”]; and
wherein the clock controller is configured to apply to the plurality of peripherals each respective clock signal of the plurality of clock signals produced by a clock divide factor in the operating set of clock divide factors selected out of the plurality of stored sets of clock divide factors [para. 0091: “Here, the operating clock CLK) provided to the CPU 334 may be the same as (or different from) the operating clock provided to the GPU 336… the clock divider 332 may divide a source clock using one clock division ratio to generate a first operating clock provided to the CPU 334, and also divide the source clock using a second clock division ratio to generate a second operating clock provided to the GPU 336.”].
Regarding claim 2, Heo discloses the clock controller comprises a plurality of storage locations comprising a first storage location and a second storage location having stored therein a first set of clock divide factors and a second set of clock divide factors [para. 0045: registers storing clock division ratios], respectively, wherein, in response to being clocked by respective clock signals produced via the second set of clock divide factors, the plurality of peripherals have a lower power absorption than when clocked by respective clock signals produced via the first set of clock divide factors [para. 0051: “…the SoC 130 in the mobile device 100 will automatically adjust (i.e., reduce) the frequency of an operating clock controlling the operation of a CPU 134 (E), thereby reducing power consumption by the CPU 134.”].
Regarding claim 3, Heo discloses the clock divide factor selection circuitry in the clock controller is configured to receive a power status signal and to select the operating set of clock divide factors out of the first set and the second set of clock divide factors based on the power status signal [para. 0045: SVD alarm signal].
Regarding claim 4, Heo discloses a consumption detector configured to monitor an amount of current absorbed by the circuit, a power control logic unit configured to receive a current evaluation signal from the consumption detector and produce the power status signal based the current evaluation signal [para. 0052: “…when a drop of the power supply voltage Vin due to sudden voltage/current consumption detected, the frequency of the operating clock CLK is reduced in response to a positive SVD alarm signal…”].
Regarding claims 9-12, Heo discloses the circuit is configured to operate in a sequence of power cycles, and at least one set of clock divide factors in the sets of clock divide factors:
is stored in a non-volatile memory and loaded during a power cycle in the sequence of power cycles [para. 0046: “…certain clock division ratio information may be loaded to the registers of the clock divider 132 during a power-up operation for the mobile device 100 or during a power reset operation for the SoC. The clock division ratio information may be externally provided and/or stored in a nonvolatile memory disposed in the PMIC 120 or SoC 130…”], or
is re-calculated during a power cycle in the sequence of power cycles [para. 0056: “Following the end of each SMPL (i.e., once the level of the power supply voltage returns above the reference voltage), the clock divider 132 re-adjusts the frequency of the operating clock CLK from the second frequency F_CLK2 to the first frequency F_CLK1 in response to respective deactivations of the positive SVD alarm signal (or transitions back to the negative alarm signal).”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 6, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Heo in view of Maggi et al., U.S. Patent Application Publication No. 2023/0081639.
Regarding claim 5, Heo discloses the circuit of claim 5, and also teaches that the power control circuit is configured to produce the power status signal based on a result of comparing the voltage with a threshold [para. 0007: “…comparing the power supply voltage to the reference voltage, and if the power supply voltage is lower than the reference voltage, generating an alarm signal, and changing a frequency of the operating clock in response to the alarm signal…”] but does not teach upper and lower threshold values for current.
Maggi discloses an upper and lower threshold for current comparison [para. 0029: “For example, a first threshold is associated with the current load changing from a low current to a high current and a second threshold is used when changing from a high current to a low current. Such an approach can provide hysteresis and prevent switching too frequently.”].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Heo and Maggi by modifying Heo to store upper and lower threshold values for current comparison as taught by Maggi. Heo teaches that the sudden voltage drop (SVD) signal may be triggered by high current consumption functions [para. 0004, 0086, 0093], suggesting that current comparisons may also be used to trigger the SVD signal. Maggi teaches that current comparisons may be performed with a first and a second current threshold for low-to-high current transitions and high-to-low current transitions, respectively. The combination is motivated by Maggi’s teaching that a first and second threshold comparison provides hysteresis and prevents switching states too frequently.
Regarding claim 6, Maggie teaches that the upper and lower threshold values are selectively adjustable [para. 0093: “Such thresholds can be programmable.”].
Regarding claims 13 and 14, Heo discloses the circuit is configured to operate in a sequence of power cycles, and at least one set of clock divide factors in the sets of clock divide factors:
is stored in a non-volatile memory and loaded during a power cycle in the sequence of power cycles [para. 0046: “…certain clock division ratio information may be loaded to the registers of the clock divider 132 during a power-up operation for the mobile device 100 or during a power reset operation for the SoC. The clock division ratio information may be externally provided and/or stored in a nonvolatile memory disposed in the PMIC 120 or SoC 130…”], or
is re-calculated during a power cycle in the sequence of power cycles [para. 0056: “Following the end of each SMPL (i.e., once the level of the power supply voltage returns above the reference voltage), the clock divider 132 re-adjusts the frequency of the operating clock CLK from the second frequency F_CLK2 to the first frequency F_CLK1 in response to respective deactivations of the positive SVD alarm signal (or transitions back to the negative alarm signal).”].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kume, U.S. Patent Application Publication No. 2012/0001664 discloses an invention comprising a clock controller [Fig. 1] configured to produce each respective clock signal of a plurality of clock signals [ICLK0 to ICLKn] via a respective clock divide factor in an operating set of clock divide factors [DR#-1 to DR#-n], wherein the operating set of clock divide factors is one of a plurality of stored sets of clock divide factors [REG0, REG1], and clock divide factor selection circuitry [Fig. 1: selector SEL] is configured to select the operating set of clock divide factors out of the plurality of stored sets of clock divide factors.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office
Phone: 571-272-7181
Fax: 571-273-7181
ji.bae@uspto.gov
1 The BRI of “clock divide factor selection circuitry” includes any and every circuit capable of performing the claimed function. Since Heo discloses the recited function, Heo also discloses the claimed circuitry.
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