DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the clock divide factors in the operating set of clock divide factors selected out of the respective sets of clock divide factors”. There is insufficient antecedent basis for this limitation. This language appears to reference a third set of clock divide factors that is a subset of the operating set of clock divide factors, which itself is a subset of the respective sets of clock divide factors. The claim has not provided an original recitation for clock divide factors in the operating set of clock divide factors. Additionally, this language is indefinite because it is unclear whether the clock divide factors in the operating set of clock divide factors (i.e., an unspecified subset of the operating set) are selected out of the respective sets, or the entirety of the operating set of clock divide factors is selected out of the respective sets. The claim has previously established the latter, but the claim language may be interpreted to indicate the former. Appropriate correction and clarification is required.
Claim 7 recites counter circuitry “configured to have count first and second counter values”. The claim language is unclear and requires correction. Claim 8 also includes this language and is rejected on the same basis.
Claim 9 recites “the sets of clock divide factors” in lines 3-4. Parent claim 1 provides an original recitation of respective clock divide factors (lines 4-5), respective sets of clock divide factors (line 6), and an operating set of clock divide factors (line 8). The recitation of “the sets of clock divide factors” is indefinite because it is unclear which of the clock divide factors established in claim 1 is being referenced. Claims 10-16 also include this language and are rejected on the same basis.
Claim 17 is directed to a method of configuring the circuit of claim 1. The subsequent steps of the method are indefinite because it is unclear how this functional language further limits the circuit. The limitations are entirely functional in nature, suggesting that they may be directed to steps for using the circuit. Under this interpretation, the steps may be viewed as an intended use and therefore non-limiting. Alternatively, the steps may be viewed as functions executed by the circuit. Under this interpretation, the claim fails to include any language to indicate that the circuit is configured to execute the functions, merely reciting that the steps themselves constitute a method of configuring the circuit. But it not clear how the functions themselves can configure the circuit to execute the functions. Applicant is advised to amend the claim as further limiting the circuit by reciting that the circuit is configured to execute the claimed steps (e.g., “wherein the circuit of claim 1 is further configured to…”).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 9-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Heo et al., U.S. Patent Application Publication No. 2023/0276367.
Regarding claim 1, Heo discloses a circuit [Fig. 1, 14] comprising a plurality of peripherals [Fig. 1: CPUs 134; Fig. 14: CPUs 334 and GPU 336] configured to be clocked with respective clock signals [Fig. 1 and 14: CPUs and GPU receive respective clock signals from CLK divider 132/332], wherein the circuit comprises a clock controller configured to produce the respective clock signals via respective clock divide factors [para. 0045: clock division ratios], the clock controller having stored therein respective sets of clock divide factors [para. 0045: “… the clock divider 132 may include one or more register(s) storing clock division ratio information that defines one or more clock division ratio(s).”], wherein the clock controller comprises clock divide factor selection circuitry configured to select an operating set of clock divide factors out of the respective sets of clock divide factors [para. 0045: “…a first clock division ratio value may be set as a default to generate the operating clock CLK having the first frequency (f1)… a second clock division ratio may be set to generate the operating clock having the second frequency (f2)…”] and wherein the clock controller is configured to apply to the plurality of peripherals respective clock signals produced via the clock divide factors in the operating set of clock divide factors selected out of the respective sets of clock divide factors [para. 0091: “Here, the operating clock CLK) provided to the CPU 334 may be the same as (or different from) the operating clock provided to the GPU 336… the clock divider 332 may divide a source clock using one clock division ratio to generate a first operating clock provided to the CPU 334, and also divide the source clock using a second clock division ratio to generate a second operating clock provided to the GPU 336.”].
Regarding claim 2, Heo discloses the clock controller comprises a plurality of storage locations comprising a first storage location and a second storage location having stored therein a first set of clock divide factors and a second set of clock divide factors [para. 0045: registers storing clock division ratios], respectively, wherein, in response to being clocked by respective clock signals produced via the second set of clock divide factors, the plurality of peripherals have a lower power absorption than when clocked by respective clock signals produced via the first set of clock divide factors [para. 0051: “…the SoC 130 in the mobile device 100 will automatically adjust (i.e., reduce) the frequency of an operating clock controlling the operation of a CPU 134 (E), thereby reducing power consumption by the CPU 134.”].
Regarding claim 3, Heo discloses the clock divide factor selection circuitry in the clock controller is configured to receive a power status signal and to select the operating set of clock divide factors out of the first set and the second set of clock divide factors based on the power status signal [para. 0045: SVD alarm signal].
Regarding claim 4, Heo discloses a consumption detector configured to monitor an amount of current absorbed by the circuit, a power control logic unit configured to receive a current evaluation signal from the consumption detector and produce the power status signal based the current evaluation signal [para. 0052: “…when a drop of the power supply voltage Vin due to sudden voltage/current consumption detected, the frequency of the operating clock CLK is reduced in response to a positive SVD alarm signal…”].
Regarding claims 9-12, Heo discloses the circuit is configured to operate in a sequence of power cycles, and at least one set of clock divide factors in the sets of clock divide factors:
is stored in a non-volatile memory and loaded during a power cycle in the sequence of power cycles [para. 0046: “…certain clock division ratio information may be loaded to the registers of the clock divider 132 during a power-up operation for the mobile device 100 or during a power reset operation for the SoC. The clock division ratio information may be externally provided and/or stored in a nonvolatile memory disposed in the PMIC 120 or SoC 130…”], or
is re-calculated during a power cycle in the sequence of power cycles [para. 0056: “Following the end of each SMPL (i.e., once the level of the power supply voltage returns above the reference voltage), the clock divider 132 re-adjusts the frequency of the operating clock CLK from the second frequency F_CLK2 to the first frequency F_CLK1 in response to respective deactivations of the positive SVD alarm signal (or transitions back to the negative alarm signal).”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 6, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Heo in view of Maggi et al., U.S. Patent Application Publication No. 2023/0081639.
Regarding claim 5, Heo discloses the circuit of claim 5, and also teaches that the power control circuit is configured to produce the power status signal based on a result of comparing the voltage with a threshold [para. 0007: “…comparing the power supply voltage to the reference voltage, and if the power supply voltage is lower than the reference voltage, generating an alarm signal, and changing a frequency of the operating clock in response to the alarm signal…”] but does not teach upper and lower threshold values for current.
Maggi discloses an upper and lower threshold for current comparison [para. 0029: “For example, a first threshold is associated with the current load changing from a low current to a high current and a second threshold is used when changing from a high current to a low current. Such an approach can provide hysteresis and prevent switching too frequently.”].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Heo and Maggi by modifying Heo to store upper and lower threshold values for current comparison as taught by Maggi. Heo teaches that the sudden voltage drop (SVD) signal may be triggered by high current consumption functions [para. 0004, 0086, 0093], suggesting that current comparisons may also be used to trigger the SVD signal. Maggi teaches that current comparisons may be performed with a first and a second current threshold for low-to-high current transitions and high-to-low current transitions, respectively. The combination is motivated by Maggi’s teaching that a first and second threshold comparison provides hysteresis and prevents switching states too frequently.
Regarding claim 6, Maggie teaches that the upper and lower threshold values are selectively adjustable [para. 0093: “Such thresholds can be programmable.”].
Regarding claims 13 and 14, Heo discloses the circuit is configured to operate in a sequence of power cycles, and at least one set of clock divide factors in the sets of clock divide factors:
is stored in a non-volatile memory and loaded during a power cycle in the sequence of power cycles [para. 0046: “…certain clock division ratio information may be loaded to the registers of the clock divider 132 during a power-up operation for the mobile device 100 or during a power reset operation for the SoC. The clock division ratio information may be externally provided and/or stored in a nonvolatile memory disposed in the PMIC 120 or SoC 130…”], or
is re-calculated during a power cycle in the sequence of power cycles [para. 0056: “Following the end of each SMPL (i.e., once the level of the power supply voltage returns above the reference voltage), the clock divider 132 re-adjusts the frequency of the operating clock CLK from the second frequency F_CLK2 to the first frequency F_CLK1 in response to respective deactivations of the positive SVD alarm signal (or transitions back to the negative alarm signal).”].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The following references are directed to inventions that employ clock dividers to supply clock signals to a plurality of peripheral components:
Lele et al., U.S. Patent Application Publication No. 2021/0034095,
Jacobowitz et al., U.S. Patent No. 8,161,314,
Seki et al., U.S. Patent Application Publication No. 2010/0308874,
Pedersen, U.S. Patent No. 6,975,154,
Sager et al., U.S. Patent No. 6,256,745.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JI H BAE whose telephone number is (571)272-7181. The examiner can normally be reached Tuesday to Friday and every other Monday, 9 am to 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office
Phone: 571-272-7181
Fax: 571-273-7181
ji.bae@uspto.gov