DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 7, 9-11, 16, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by 3GPP TSG RAN WG1 Meeting 91, R1-1721387, Reno, USA, 11/27-12/1, 2017, Agenda Item 7.3.2.3, Qualcomm Incorporated, Multiplexing of PUCCH and PUSCH, Discussion and Decision, hereinafter “D1”, IDS disclosed by applicant).
Regarding claims 1 and 19, D1 discloses a user equipment (UE), comprising:
one or more memories storing processor-executable code; and
one or more processors coupled with the one or more memories and
individually or collectively operable to execute the code to cause the UE to:
receive, from a network entity, a downlink control message (see the DCI indicated in step 1 at the bottom of page 5) indicating the UE to multiplex an uplink control message (see UCI, step 1, bottom of page 5) associated with a first modulation and coding scheme (MCS) (see UCI MCS mentioned in step 2, top of page 6) on an uplink data channel (see PUSCH in algorithm 1 and step 1, bottom of page 5) associated with a second MCS (see PUSCH-MCS , bottom of page 5), wherein the first MCS has a first modulation order and the second MCS has a second modulation order that is different than the first modulation order (see the “QAM order” in step 1, bottom of page 5, for PUSCH-MCS and “QAM order” for UCI in step 2, top of page 6, see also Figure 2, page 6, given the modulation order of UCI and PUSCH can be different” and the two different modulation mappers, one for UCI and one for UL-SCH, in Figure 2);
multiplexing, base at least in part on the downlink control
message, the uplink control message associated with the first MCS on the uplink
data channel associated with the second MCS to generate a multiplexed uplink
message comprising the uplink control message multiplexed with uplink data of
the uplink data channel (see Algorithm 1: MCS/Modulation determination for UCI when piggybacked on PUSCH, bottom of page 5, and Figure2); and transmit, via a wireless communications link between the network entity and the UE, the multiplexed uplink message (see section 1, piggyback UL transmission).
Regarding claims 2, 11 and 20, D1 discloses wherein the one or more processors are individually or collectively further operable to execute the code to cause the UE to: receive, as part of the downlink control message, an indication of a data
MCS indicator associated with the second MCS and an MCS backoff value, wherein the
first MCS is based at least in part on the data MCS indicator and the MCS backoff
value (see page 5, step 1, DCI containing the second MCS, MCS for data , a MCS backoff value, the first MCS being computed from the second MCS and the backoff value, DCI indicates PUSCH-MCS and beta offset for UCI).
Regarding claims 7, and 16, D1 discloses wherein the downlink control message is a downlink control information (DCI) message that indicates the first MCS associated
with the uplink control message and the second MCS associated with the uplink data
channel (see page 5, step1 and page 6, step 2, UCI MCS table).
Regarding claims 9, and 18, D1 discloses wherein the one or more processors are individually or collectively further operable to execute the code to cause the UE to: receive, as part of the DCI message, an uplink control MCS indicator indicating that the first MCS is associated with the first modulation order (see page 5, DCI with beta offset indicator for UCI) and a first code rate and a data MCS indicator indicating that the second MCS is associated with the second modulation order and a second code rate (see page 5, PUSCH _MCS).
Regarding claim 10, D1 discloses a network entity (see page 3, section 2, eNB), comprising: one or more memories storing processor-executable code; and one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the network entity to: output, to a user equipment (UE), a downlink control message (see the DCI indicated in step 1 at the bottom of page 5) indicating the UE to multiplex an uplink control message (see UCI, step 1, bottom of page 5) associated with a first modulation and coding scheme (MCS) (see UCI MCS mentioned in step 2, top of page 6) on an uplink data channel (see PUSCH in algorithm 1 and step 1, bottom of page 5) associated with a second MCS (see PUSCH-MCS , bottom of page 5), wherein the first MCS has a first modulation order and the second MCS has a second modulation order that is different than the first modulation order (see the “QAM order” in step 1, bottom of page 5, for PUSCH-MCS and “QAM order” for UCI in step 2, top of page 6, see also Figure 2, page 6, given the modulation order of UCI and PUSCH can be different” and the two different modulation mappers, one for UCI and one for UL-SCH, in Figure 2); and obtain, via a wireless communications link between the network entity and the UE, a multiplexed uplink message comprising the uplink control message multiplexed with uplink data of the uplink data channel, wherein the uplink control message is associated with the first MCS on the uplink data channel associated with the second MCS. (see Algorithm 1: MCS/Modulation determination for UCI when piggybacked on PUSCH, bottom of page 5, and Figure2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-6, 8, 12-15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of Soriaga et al. (US 2019/0150179 A1, hereinafter “Soriaga”, IDS disclosed by applicant).
Regarding claims 3, and 12, D1 discloses all the subject matter but fails to mention explicitly wherein: the UE is configured with an MCS table comprising a set of indexes each associated with a respective MCS; the data MCS indicator indicates a second index from the set of indexes that is associated with the second MCS; and a difference between the second index and the MCS backoff value is equal to a first index of the set of indexes that is associated with the first MCS. However, Soriaga from a similar field of endeavor discloses wherein: the UE is configured with an MCS table comprising a set of indexes each associated with a respective MCS; the data MCS indicator indicates a second index from the set of indexes that is associated with the second MCS (see para. 0063, MCS table with indexes); and a difference between the second index and the MCS backoff value is equal to a first index of the set of indexes that is associated with the first MCS (see para. 0063, MCS index with backoff value to derive first index). Thus, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention was made to include MCS index scheme of Soriaga into MCS table of D1. The method can be implemented in a table. The motivation of doing this is to spectral efficiency of uplink transmission.
Regarding claims 4, and 13, D1 discloses all the subject matter but fails to mention wherein the one or more processors are individually or collectively further operable to execute the code to cause the UE to: receive a second downlink control message that configures the MCS table at the UE. However, Soriaga from a similar field of endeavor discloses wherein the one or more processors are individually or collectively further operable to execute the code to cause the UE to: receive a second downlink control message that configures the MCS table at the UE (see para. 0061-0063, receive DCI). Thus, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention was made to include MCS index scheme of Soriaga into MCS table of D1. The method can be implemented in a table. The motivation of doing this is to spectral efficiency of uplink transmission.
Regarding claims 5, and 14, D1 discloses all the subject matter but fails to mention explicitly wherein: the UE is configured with an MCS-spectral efficiency (SE) table for transmission uplink control messages that comprises a set of SE values each associated with a respective MCS value; the data MCS indicator indicates that the uplink data channel is associated with the second MCS which is associated with a second SE value; a division between the second SE value and the MCS backoff value is equal to a first SE value; and the second MCS is associated with an SE value of the set of SE values that is closet in value to the first SE value. However, Soriaga from a similar field of endeavor discloses wherein: the UE is configured with an MCS-spectral efficiency (SE) table for transmission uplink control messages that comprises a set of SE values each associated with a respective MCS value (see para. 0063, determine MCS for data channel in a table); the data MCS indicator indicates that the uplink data channel is associated with the second MCS which is associated with a second SE value (see para. 0061, SE PUSCH as a product of code rate and QAM order); a division between the second SE value and the MCS backoff value is equal to a first SE value (see para. 0062, determine SE UCI= SE PUSCH/beta offset); and the second MCS is associated with an SE value of the set of SE values that is closet in value to the first SE value (see para. 0063, code rate of QAM order in the MCS table less than the spectral efficiency for the uplink control information transmission). Thus, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention was made to include MCS index scheme of Soriaga into MCS table of D1. The method can be implemented in a table. The motivation of doing this is to spectral efficiency of uplink transmission.
Regarding claims 6, and 15, D1 discloses wherein the one or more processors are individually or collectively further operable to execute the code to cause the UE to: receive a second downlink control message that indicates for the UE to use MCS-SE table from a plurality of MCS-SE tables configured at the UE for transmission of uplink control messages (see page 5, step1 and page 6, step 2, UCI MCS table).
Regarding claims 8, and 17, D1 discloses all the subject matter but fails to mention explicitly wherein: receiving, as part of the DCI message, an MCS backoff value associated with the second MCS, wherein; a first set of bits of the MCS backoff value indicates a scaling factor for a first spectral efficiency (SE) value of the uplink control message relative a second SE value for the uplink data channel; a second set of bits of the MCS backoff value indicates the second modulation order; and the second MCS is based at least in part on the first SE value and the second modulation order. However, Soriaga from a similar field of endeavor discloses wherein: receiving, as part of the DCI message, an MCS backoff value associated with the second MCS, wherein; a first set of bits of the MCS backoff value indicates a scaling factor for a first spectral efficiency (SE) value of the uplink control message relative a second SE value for the uplink data channel (see para. 0064, code rate is based on scaling factor; para. 0061, DCI message with PUSCH coding scheme and offset for UCI); a second set of bits of the MCS backoff value indicates the second modulation order; and the second MCS is based at least in part on the first SE value and the second modulation order (see para. 0061-0062, modulation order and SE values to compute MCS for data and UCI). Thus, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention was made to include MCS index scheme of Soriaga into MCS table of D1. The method can be implemented in a table. The motivation of doing this is to spectral efficiency of uplink transmission.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD S ANWAR whose telephone number is (571)270-5641. The examiner can normally be reached M-F 6-5 EST.
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MOHAMMAD S. ANWAR
Primary Examiner
Art Unit 2463
/MOHAMMAD S ANWAR/ Primary Examiner, Art Unit 2463