Office Action Predictor
Last updated: April 16, 2026
Application No. 18/607,099

Switch Device and Hard Disk Device

Non-Final OA §102§103
Filed
Mar 15, 2024
Examiner
NGUYEN, DANNY
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., LTD.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
95%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
1207 granted / 1340 resolved
+22.1% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
31 currently pending
Career history
1371
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
38.1%
-1.9% vs TC avg
§102
52.2%
+12.2% vs TC avg
§112
6.3%
-33.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1340 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 1. Claims 1, 4 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Namai et al (USPN 2020/0083878). Regarding claim 1, Namai discloses a switch device (a switch device 1 shown in figure 1), comprising: a switch element (e.g. a switch element 22), including a gate, a drain, a source, a back gate, a first body diode disposed between the drain and the back gate and a second body diode disposed between the source and the back gate; a first switch circuit, including a first switch (26) connected between the back gate and an application end at ground potential (GND); and a second switch circuit (24, 25), including a second switch (25) connected between the back gate and the source. Regarding claim 4, Namai discloses wherein the second switch (24, 25) includes a first NMOS transistor (24) and a first PMOS transistor (25) connected in parallel between the back gate and the source of the switch element (22). 2. Claims 1, 14 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kosuge (USPN 2009/0284287). Regarding claim 1, Kosuge discloses a switch device (a switch device 10E shown in figure 8), comprising: a switch element (e.g. a switch element MP1), including a gate, a drain, a source, a back gate, a first body diode disposed between the drain and the back gate and a second body diode disposed between the source and the back gate (the switching element MP1 inherently includes a PN junction parasitic diodes formed between a drain terminal and a substrate terminal and a source terminal and a substrate terminal, only a PN diode D1 shows in the drawing 7); a first switch circuit, including a first switch (MP 10) connected between the back gate and an application end at ground potential (a MP 10 is coupled to a ground via a MN3, see par. 0145); and a second switch circuit (MN3, MP7, MP8), including a second switch (such as MP8 electrically tied to a source electrode of MP1 via a power terminal VDDIO) connected between the back gate and the source. Regarding claim 14, Kosuge discloses wherein the first switch (MN3, MP7, MP8) and the second switch (MP10) are arranged along a chip edge of a chip (a chip 20E) of the switch device (MP1) (MP10, MN3, MP7, MP8 of a substrate voltage controlled circuit 22E are arranged along a chip edge of a chip (a chip 20E, see figure 8). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 3. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Namai et al (USPN 2020/0083878) in view of Voldman (USPN 2001/0043112). Regarding claim 3, Namai discloses all limitations of claim 1 as discussed above, but does not explicitly teach a high pass filter as claimed. Voldman discloses a back gate control circuit (see figure 11) includes a first high-pass filter (41, 71) connected between a drain of a switch element (43) and a control end of a first switch (110). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified a switching device of Namai to incorporate a high pass filter as disclosed by Voldman in order to increase a current drive and reduce a less voltage stress. Thus improving a protection performance. 4. Claims 1, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al (USPN 2015/0137260) in view of Namai et al (USP 2020/0083878). Regarding claims 1, 15, Matsui discloses a hard disk device (see figure 1, par. 0052), comprising: a switch device (QH); and an HDD (LD), configured to be supplied with an output voltage output from a source (S1) of the switch element (QH). Matsui does not explicitly disclose the switching device as claimed. Namai discloses a switch device (a switch device 1shown in figure 1), comprising: a switch element (e.g. a switch element 22), including a gate, a drain, a source, a back gate, a first body diode disposed between the drain and the back gate and a second body diode disposed between the source and the back gate; a first switch circuit, including a first switch (26) connected between the back gate and an application end at ground potential (GND); and a second switch circuit (24, 25), including a second switch (25) connected between the back gate and the source. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified a switching device of Matsui to incorporate a switching device as disclosed by Namai in order to control a back gate voltage of the switching device so that protecting the switching device from a reverse current event. Allowable Subject Matter 5. Claims 2, 5-13, 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY NGUYEN whose telephone number is (571)272-2054. The examiner can normally be reached M-F 8:00AM-4:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-271-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANNY NGUYEN/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Mar 15, 2024
Application Filed
Nov 21, 2025
Non-Final Rejection — §102, §103
Mar 26, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12598729
ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD THEREOF
2y 5m to grant Granted Apr 07, 2026
Patent 12592559
FIELD DEVICE CURRENT LIMITING
2y 5m to grant Granted Mar 31, 2026
Patent 12587004
LEAKAGE CURRENT PROTECTION DEVICE AND ELECTRICAL APPLIANCES EMPLOYING THE SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12567548
ACCELERATED MOTION RELAY
2y 5m to grant Granted Mar 03, 2026
Patent 12562559
ARC FLASH MITIGATION DEVICE
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
95%
With Interview (+5.1%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 1340 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in for Full Analysis

Enter your email to receive a magic link. No password needed.

Free tier: 3 strategy analyses per month