DETAILED ACTION
Claims 1-20 are currently pending in the application and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 11/26/2025 have been fully considered but they are not persuasive.
Applicant’s amendments did not overcome the rejections under 35 USC § 112(b) as shown below. In fact, none of the rejections under 35 USC § 112(b) were addressed by amendment or argument. In addition, Applicant removed the limitation that was stated as allowable, once the rejections under 35 USC § 112(b) were corrected, from claim 1 and move it to claim 2, making claim 1 broader. As a result, claim 1 is no longer allowable as previously stated and will be rejected in view of the prior art. As a result, claims 1-11 and 13 remain rejected under 35 USC § 112(b) and a prior art rejection of claim 1 has been added.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are:
Claim 1:
This claim recites the limitation “receive, … data from a source memory cell of the plurality of memory cells and at least one error correction parity bit associated with the data for transfer to a target memory cell of the plurality of memory cells”. (Emphasis added). The claim never performs the transferring step; therefore, this claim is rejected for being incomplete for omitting essential steps, such omission amounting to a gap between the steps. (Clarification and correction are required).
This claim also recites the limitations “perform error correction on the data based on the data from the source memory cell having a data error”. The claim never detects the data error as shown in Fig. 14, step 1406, so how can the data error be corrected when it was never detected? Therefore, this claim is rejected for being incomplete for omitting essential steps, such omission amounting to a gap between the steps. (Clarification and correction are required).
Claim 2:
This claim recites “the circuit is configured to transfer…”, but is missing where the items are being transferred from and where they’re transferred to. Therefore, this claim is rejected for being incomplete for omitting essential steps, such omission amounting to a gap between the steps. (Clarification and correction are required).
This claim also recites the limitations “perform error correction on the at least one error correction parity bit based on the at least one error correction parity bit having a parity bit error”. The claim never detects the parity bit error as shown in Fig. 14, step 1414, respectively, so how can parity bit error be corrected when it was never detected? Therefore, this claim is rejected for being incomplete for omitting essential steps, such omission amounting to a gap between the steps. (Clarification and correction are required).
Claim 3:
This claim is missing where the items are being transferred from. Therefore, this claim is rejected for being incomplete for omitting essential steps, such omission amounting to a gap between the steps. (Clarification and correction are required).
Claim 4:
This claim recites “maintain a mapping of the data stored in a holding register”. However, nowhere in this claim or the claim it depends on ever stores the data in a holding register. Therefore, this claim is rejected for being incomplete for omitting essential steps, such omission amounting to a gap between the steps. (Clarification and correction are required).
Claims 1-7, 9 and 11:
These claims exhibit similar deficiencies as claim 4 and are rejected in like.
Claims 8 and 10:
These claims are also rejected because they depend on a base rejected claim and have the same problems of being incomplete for omitting essential steps.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13:
This claim recites the limitation "the command" in line 4. There is insufficient antecedent basis for this limitation in the claim. This occurred because the antecedent basis for this was amended out of claim 12.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Porter (US-10636459), hereinafter Porter.
Claim 1:
Porter teaches a memory device (Fig. 1, non-volatile memory 101), comprising:
at least one memory array (Fig. 1, memory device 102) comprising a plurality of memory cells configured to store data; and
a circuit (Fig. 1, Controller 104) configured to: receive, for a memory management read operation of a memory management function, data from a source memory cell of the plurality of memory cells and at least one error correction parity bit associated with the data for transfer to a target memory cell of the plurality of memory cells (The transfer of data D2 to data DM from resister 209 to row 235-2,1 respectively concurrently with the transfer of data A1 to data AM-1 from row 235-1,2 to register 209 can continue until data DM is transferred. Data AM is then transferred to segment 249-M so that segments 249-1 to 249-M respectively contain data A1 to data AM respectively from the portions of row 235-1,2 respectively corresponding to columns 236-1,1 to 236-1,M. In some examples, each of data A1 to data AM-1 may be sensed by a respective sense component 239-1 in response to a respective activation pulse 485, sent to register 246, and sent from register 246 to a respective segment 249 while rows 235-2,1 and 235-1,2 are currently activated and while data is sent from a segment 249 to row 235-2,1, Fig. 4B and discussion therein.); and
perform error correction on the data based on the data from the source memory cell having a data error (The controller 104 can also be configured to perform an error correction operation, using an error correction code (ECC), on data A1 to data AM while it is being transferred from row 235-1,2 to register 209, such as while data A1 to data AM is being transferred from register 246 to register 209, for example, Fig. 4B and discussion therein.).
Allowable Subject Matter
Claim 2 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include the limitations of this claim into claim 1. None of the prior art teaches performing error correction on the at least one error correction parity bit based on the at least one error correction parity bit having a parity bit error as written in claim 2.
Claim 13 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 12 and 14-20 are allowed.
The following is an Examiner’s Statement of Reasons for Allowance:
The present invention relates to memory devices in general, and more particularly, but not limited to, memory management holding latch placement and control signal generation.
The claimed invention as set forth in claim 12 recites features such as:
A method comprising:
storing, in a holding register of a circuit of a memory device, data and at least one error correction parity bit associated with the data that is received from a source memory cell of the memory device;
receiving, from a controller, a request to read the data; determining whether an address associated with the request to read the data matches with a source row address of the source memory cell mapped to the holding register storing the data; and
providing, if the address associated with the request matches with the source row address mapped to the holding register storing the data, the data from the holding register to the controller.
The prior arts of record, namely Porter (US-10636459), teach memory management component 128 includes an address converter, such as a logical-to-physical (L2P) address mapping table 132. For example, table 132 can map logical addresses received from host 103 to physical addresses of locations of groups of memory cells, such as rows, within memory array 106. In some examples, a logical address of a row in subarray 107-1 may be mapped to a row in subarray 107-2 when data from a row in subarray 107-1 is transferred to a row in subarray 107-2 during wear leveling. A logical address of a row in subarray 107-1 may be mapped to a register (e.g., a holding register), which may be part of read/latch circuitry 120, in response to transferring data from that row to the register during a wear leveling operation, for example. As used herein, the term “row” can refer to an access line (e.g., a select line or word line) to which a group of memory cells are commonly coupled and/or to the group of cells themselves (e.g., “a row of cells”). (Col. 4, ll. 23-40). Even though Porter discloses a holding register it does not serve the same functions the current application, which is storing the data and the at least one error correction parity bit until the data and the at least one error correction parity bit are transferred to the target memory cell.
Therefore, Porter fails to teach, singly or in combination, storing, in a holding register of a circuit of a memory device, data and at least one error correction parity bit associated with the data that is received from a source memory cell of the memory device and providing, if the address associated with the request matches with the source row address mapped to the holding register storing the data, the data from the holding register to the controller. As such, modification of the prior art of record to include the claimed storing, in a holding register of a circuit of a memory device, data and at least one error correction parity bit associated with the data that is received from a source memory cell of the memory device and providing, if the address associated with the request matches with the source row address mapped to the holding register storing the data, the data from the holding register to the controller can only be motivated by hindsight reasoning, or by changing the intended use and function of the prior art themselves. Therefore, it is not clear that one of ordinary skill in the art at the time of the invention would have made the necessary modifications to the prior art of record to encompass the storing, in a holding register of a circuit of a memory device, data and at least one error correction parity bit associated with the data that is received from a source memory cell of the memory device and providing, if the address associated with the request matches with the source row address mapped to the holding register storing the data, the data from the holding register to the controller set forth in the present application. Moreover, none of the prior arts of record, taken either alone or in combination, anticipate nor render obvious the storing, in a holding register of a circuit of a memory device, data and at least one error correction parity bit associated with the data that is received from a source memory cell of the memory device and providing, if the address associated with the request matches with the source row address mapped to the holding register storing the data, the data from the holding register to the controller as set forth in claim 12. Independent claim(s) 17 recite(s) similar patentable features, although worded differently, and are/is allowable for the same reasons as claim 12. Hence, claims 12 and 14-20 are allowable over the prior arts of record.
The Examiner favors the allowance of claims 12 and 14-20. Any comments considered necessary by applicant must be submitted no later than the payment of the Issue Fee and, to avoid processing delays, should preferably accompany the Issue Fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN J TABONE JR whose telephone number is (571)272-3827. The examiner can normally be reached M-F 9 AM to 7 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN J TABONE JR/Primary Examiner, Art Unit 2111 02/06/2026