DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Response to Amendment
Applicant’s amendments filed July 06, 2026 have been fully considered and entered.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-14, 17 and 20 rejected under 35 U.S.C. 102(a)(2) as being anticipated by Darmawikarta et al. (US-20230185033-A1), hereafter Darmawikarta.
Regarding claim 11, Darmawikarta disclose a package (FIG.2. Photonic package 100) comprising:
a metallization portion (redistribution layer (RDL) 148. Par. [0057]: comprising at least one layer of an insulating material and metallization) comprising:
one or more dielectric layers (Par. [0057]: 148 comprising at least one layer of an insulating material and metallization (e.g., conductive pathways through a dielectric material)) ; and
a plurality of metallization interconnects (Par. [0057]. See annotated figure 2 below);
a first integrated device (XPU 118) coupled to the metallization portion through a first plurality of solder interconnects (solder 134. See annotated figure 2 below) , wherein a front side (The front side is interpreted as the active side facing substrate 124) of the first integrated device (118) is directed in a direction towards the metallization portion (RDL 148);
an encapsulation layer at least partially encapsulating the first integrated device (Insulating material 133. Par. [0044]: Insulating material 133-2 of the second layer 104-2 surrounding XPU 118. The encapsulation layer in interpreted as material used to embed one or more dies in a layer that may include a mold, a resin and/or epoxy);
a plurality of post interconnects (Interconnects 130) located in the encapsulation layer (insulating material 133-2) , wherein the plurality of post interconnects are coupled to the plurality of metallization interconnects (see annotated figure 2 below) ;
a second integrated device (EIC 114) coupled to the metallization portion (RDL 148) through a second plurality of solder interconnects (solder 134. See annotated figure 2 below);
an optical integrated device (PIC 102) coupled to the plurality of metallization interconnects (see annotated figure 2 below) of the metallization portion (RDL 148) through a third plurality of solder interconnects (see annotated figure 2 below),
wherein the third plurality of solder interconnects touch (i) the plurality of metallization interconnects and (ii) the optical integrated device (PIC 102. See annotated figure 2 below), and wherein the optical integrated device (PIC 102) is located outside of the metallization portion (RDL 148. FIG. 2) ;
an optical fiber coupled to the optical integrated device (Par. [0027]); and
a package substrate (package substrate 124) coupled to the plurality of post interconnects through a fourth plurality of solder interconnects.
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Regarding claim 12, Darmawikarta discloses the device of claim 11. Darmawikarta further discloses the second integrated device (EIC 114) is coupled to the optical integrated device (PIC 102) through an electrical path that includes a solder interconnect from the second plurality of solder interconnects, metallization interconnects from the metallization portion and a solder interconnect from the third plurality of solder interconnects (Par.[0027]: EIC 114 and TGVs 192 in a first layer 104-1 electrically coupled via interconnects 130 to an XPU 118 and a PIC 102).
Regarding claim 13, Darmawikarta discloses the device of claim 11. Darmawikarta further discloses the first integrated device (XPU 118) is coupled to the optical integrated device (PIC 102) through an electrical path that includes a solder interconnect from the first plurality of solder interconnects, metallization interconnects from the metallization portion and a solder interconnect from the third plurality of solder interconnects (Par. [0066]: PIC 102 and XPU 118 may be electrically coupled with TGVs 192 through associated conductive traces, planes, and pads in RDL 148-2).
Regarding claim 14, Darmawikarta discloses the device of claim 11. Darmawikarta further discloses the second integrated device (EIC 114) is coupled to the first integrated device (XPU 118) through an electrical path that includes a solder interconnect from the second plurality of solder interconnects, metallization interconnects from the metallization portion and a solder interconnect from the first plurality of solder interconnects (Par.[0027]: EIC 114 and TGVs 192 in a first layer 104-1 electrically coupled via interconnects 130 to an XPU 118 and a PIC 102).
).
Regarding claim 17, Darmawikarta discloses the device of claim 11 . Darmawikarta further discloses a plurality of power rail interconnects located in the encapsulation layer (Par. [0036]: Interconnects 130 may comprise die-to-die (DTD) interconnects along with associated conductive traces, planes, vias, and pads enabling electrical coupling between PIC 102 and EIC 114. Conductive planes serve the same function as a power rail).
Regarding claim 20, Darmawikarta discloses the device of claim 11 . Darmawikarta further discloses a connector socket coupled to the metallization portion, wherein the connector socket is configured to provide an electrical path for power (Par. [0017]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Darmawikarta et al. (US20230185033A1), hereafter Darmawikarta, and in view of Karhade et al. (US20240027710A1), hereafter Karhade.
Regarding claim 15, Darmawikarta discloses the device of claim 11. Darmawikarta further discloses a passive device (Par. [0042]: package substrate 124 may comprise a single or multi-layered insulating material with metallization including planes, traces, vias, and passive components (e.g., inductors, capacitors) within the insulating material and/or on the surfaces.) . Darmawikarta fails to disclose the passive device coupled to the metallization portion.
Karhade teaches a passive device (Bride die 202) coupled to the metallization portion (Column 16 lines 55-62. The metallization portion is the area in between 170-1 and 170-2).
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to modify the device of Darmawikarta by coupling the passive device to the metallization portion as taught by Karhade.
One of ordinary skill in the art would have been motivated to make this modification to optimize space utilization, reduce interconnect lengths, and improve signal integrity within the semiconductor package, as demonstrated by Karhade's placement of the bridge die. Furthermore, integrating a passive device directly onto a designated metallization portion relies on predictable, well-known assembly techniques within the packaging art. A person of ordinary skill would have expected success in combining these teachings to achieve a more compact and electrically efficient device layout without altering the core functionality of Darmawikarta's optical components
Regarding claim 16, Darmawikarta discloses the device of claim 15 . Darmawikarta further discloses the passive device (Par. [0042]) , but fails to disclose the passive device is at least partially encapsulated by the encapsulation layer.
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to modify the device of Darmawikarta to have the passive device partially located in the encapsulation layer. A person of ordinary skill in art would have been motivated to implement this modification to protect the passive device from environmental or mechanical damage, thereby improving overall device reliability. The combination of these known elements would yield no more than the predictable result of an encapsulated passive device with enhanced durability.
Claim 18-19 is rejected under 35 U.S.C. 103 as being unpatentable over Darmawikarta et al. (US20230185033A1), hereafter Darmawikarta.
Regarding claim 18, Darmawikarta discloses the device of claim 17. Darmawikarta further discloses the plurality of power rail interconnects (conductive planes) are located between the first integrated device (XPU 118) and the package substrate (package substrate 124. Par. [0042]).
While Darmawikarta does not explicitly disclose the power rails interconnects are located at the back side of 102, the placement of interconnects on the back of a chip is a known technique for
power delivery. Before the effective filing date of the present invention, it would have been obvious
to a person of ordinary skill in the art to position the power rails at the back of the integrated device
as a matter of routine optimization. Specifically, this placement would be considered a routine design
choice to optimize signal routing on the front side or to manage thermal constraints of the PIC 102. Consequently, placing the power rails on the back side constitutes the application of a known technique to a known device to yield predictable results.
Regarding claim 19, Darmawikarta discloses the device of claim 11. Darmawikarta further discloses second integrated device (EIC 114) but fails to disclose the second integrated device includes memory.
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to include memory within the second integrated device. One of ordinary skill in the art would have been motivated to include memory in the electronic integrated circuit (EIC) to provide local, high-speed data storage and buffering capability directly on the component. This modification represents a routine application of known data-storage principles to an integrated device, yielding predictable results such as improved processing efficiency, reduced latency, and minimized data-bus bottlenecks between the EIC and external components.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Karhade et al. (US12392970B2) , hereafter Karhade, and in view of Li et al. (US20240027710A1), hereafter Li.
Regarding claim 1, Karhade discloses a package (FIG. 1A. Photonic Package 100) comprising:
a package substrate (124);
a first integrated device (XPU 118) coupled to the package substrate through a first plurality of solder interconnects (Interconnects 130. Column 12 lines 46-48. Solder reflow refers to the formation of solder joints);
an encapsulation layer (Insulation material 133. Column 7 lines 13-19 and Column 12 line 59-Column 13 line 3. The encapsulation layer in interpreted as material used to embed one or more dies in a layer that may include a mold, a resin and/or epoxy) at least partially encapsulating the first integrated device (FIG 1A);
a plurality of post interconnects (Conductive pillars 152) located in the encapsulation layer (FIG 1A);
a metallization portion coupled to the plurality of post interconnects (FIG. 1A. Column 7 lines 19-38. Column 16 lines 55-62. The metallization portion is the area in between 170-1 and 170-2);
a second integrated device (EIC 114) coupled to the metallization portion through a second plurality of solder interconnects (Interconnects 130. Column 12 lines 46-48. Solder reflow refers to the formation of solder joints);
an optical integrated device (PIC 102) coupled to the package substrate (Column 4 lines 18-20); and
an optical fiber coupled to the optical integrated device (Column 41 lines 53-55).
Karhade fails to disclose the optical integrated device located at least partially in the package substrate.
Li teaches an optical integrated device (FIC. 1C. PIC 126) located at least partially in the package substrate (FIG. 1C. package substrate 122).
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to modify the package of Karhade by integrating the optical integrated device at least partially within the package substrate, as taught by Li, in order to reduce the overall profile height of the photonic package and improve mechanical stability. A person of ordinary skill in the art would have been motivated to incorporate Li’s embedded configuration into the package of Karhade because placing the optical integrated device at least partially inside the substrate minimizes the vertical stack-up height, enables shorter interconnect paths to improve signal integrity, and provides better physical protection for sensitive optical components. A person of ordinary skill in the art would have had a reasonable expectation of success in combining these teachings because both Karhade and Li operate in the closely related field of semiconductor and optoelectronic packaging, and the modification involves the predictable application of known substrate-embedding techniques to achieve a more compact and reliable electronic assembly.
Regarding claim 2, Karhade discloses the package of claim 1. Karhade further discloses a front side of the first integrated device is directed in a direction towards the package substrate (Column 23 lines 1-7: double sided XPU 118. The front side is interpreted as the active side facing substrate 124.)
Regarding claim 3, Karhade discloses the package of claim 1. Karhade further discloses the second integrated device (EIC 114) is configured to be electrically coupled to the optical integrated device (PIC 102) through an electrical path that includes a solder interconnect (Column 7 lines 21-28 and Column 10 lines 45-46) from the second plurality of solder interconnects (Interconnects 130), metallization interconnects (Metallization lines. Column 16 lines 33-37) from the metallization portion (Column 16 lines 55-62), a post interconnect (Interconnect 130) from the first plurality of solder interconnects (Column 16 lines 33-37: Metallization lines providing conductive pathways to and from various elements in the photonic package. Column 7 lines 6-11: conductive pathways connecting one or more dies including non-adjacent layers).
Regarding claim 4, Karhade discloses the package of claim 1. Karhade further discloses the first integrated device (XPU 118) is configured to be electrically coupled to the optical integrated device (PIC 102) through an electrical path that includes a solder interconnect (Column 7 lines 21-28) from the first plurality of solder interconnects (FIG 1A. Column 7 lines 19-28. Column 16 lines 33-37: Metallization lines providing conductive pathways to and from various elements in the photonic package. Column 7 lines 6-11: conductive pathways connecting one or more dies including non-adjacent layers).
Regarding claim 5, Karhade discloses the package of claim 1. Karhade further discloses the second integrated device (EIC 114) is configured to be electrically coupled to the first integrated device (XPU 118) through an electrical path that includes a solder interconnect (Column 19 lines 44-52) from the second plurality of solder interconnects (Interconnects 130), metallization interconnects (Metallization lines. Column 16 lines 33-37) from the metallization portion (Column 16 lines 55-62), a post interconnect from the plurality of post interconnects (Conductive Pillars 152) and a solder interconnect from the first plurality of solder interconnects (Interconnects 130), interconnects from the package substrate (Interconnects 150), and another solder interconnect (Interconnect 130) from the first plurality of solder interconnects (FIG. 1A and FIG. 4. Column 7 lines 19-28. Column 16 lines 33-37: Metallization lines providing conductive pathways to and from various elements in the photonic package. Column 7 lines 6-11: conductive pathways connecting one or more dies including non-adjacent layers).
Regarding claim 6, Karhade discloses the package of claim 1. Karhade further discloses the second integrated device (EIC 114) is configured to be electrically coupled to the first integrated device (XPU 118) through an electrical path that includes a solder interconnect (Column 19 lines 44-52) from the second plurality of solder interconnects (Interconnects 130), metallization interconnects (Metallization lines. Column 16 lines 33-37) from the metallization portion (Column 16 lines 55-62), a post interconnect from the plurality of post interconnects (Conductive Pillars 152) and a solder interconnect from the first plurality of solder interconnects (Interconnects 130), interconnects from the package substrate (Interconnects 150), the optical integrated device (PIC 102), and another solder interconnect (Interconnect 130) from the first plurality of solder interconnects (FIG 1A and FIG 4. Column 7 lines 19-28. Column 11 lines 41-41. Column 16 lines 33-37: Metallization lines providing conductive pathways to and from various elements in the photonic package. Column 7 lines 6-11: conductive pathways connecting one or more dies including non-adjacent layers).
Regarding claim 7, Karhade discloses the package of claim 1. Karhade further discloses comprising a connector socket coupled to the metallization portion, wherein the connector socket is configured to provide an electrical path for power (Column 4 lines 33-45 and Column 7 lines 21-28).
Regarding claim 8, Karhade discloses the package of claim 1. Karhade further discloses the optical integrated device includes a waveguide and a circuit for processing optical signals and/or electrical signals (Colum 3 lines 37-44 and Column 8 lines 12-16).
Regarding claim 9, Karhade discloses the package of claim 1. Karhade further discloses the optical fiber extends through the package substrate (Column 25 lines 47-50).
Regarding claim 10, Karhade discloses the package of claim 1. Karhade further discloses integrated device (XPU 118) includes memory. An XPU implicitly has local memory (e.g. registers or cache).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAJANAE N GREEN whose telephone number is (571)272-2188. The examiner can normally be reached Tues-Fri. 5:30a-3:30p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at (571) 272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAJANAE NICOLE GREEN/ Examiner, Art Unit 2874
/MICHELLE R CONNELLY/ Primary Examiner, Art Unit 2874
