DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statements filed on July 22, 2024 and December 02, 2024 have all been considered and made of record (note the attached copies of form PTO-1449).
Drawings
Fourteen (14) sheets of drawings were filed on March 15, 2024.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-17 and 19-20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karhade et el. (US12392970B2), hereafter Karhade.
Regarding claim 1, Karhade discloses a package (FIG. 1A. Photonic Package 100) comprising: a package substrate (124); a first integrated device (XPU 118) coupled to the package substrate through a first plurality of solder interconnects (Interconnects 130. Column 12 lines 46-48. Solder reflow refers to the formation of solder joints); an encapsulation layer (Insulation material 133. Column 7 lines 13-19 and Column 12 line 59-Column 13 line 3. The encapsulation layer in interpreted as material used to embed one or more dies in a layer that may include a mold, a resin and/or epoxy) at least partially encapsulating the first integrated device (FIG 1A); a plurality of post interconnects (Conductive pillars 152) located in the encapsulation layer (FIG 1A); a metallization portion coupled to the plurality of post interconnects (FIG. 1A. Column 7 lines 19-38. Column 16 lines 55-62. The metallization portion is the area in between 170-1 and 170-2); a second integrated device (EIC 114) coupled to the metallization portion through a second plurality of solder interconnects (Interconnects 130. Column 12 lines 46-48. Solder reflow refers to the formation of solder joints); an optical integrated device (PIC 102) coupled to the package substrate (Column 4 lines 18-20); and an optical fiber coupled to the optical integrated device (Column 41 lines 53-55).
Regarding claim 2, Karhade discloses the package of claim 1. Karhade further discloses a front side of the first integrated device is directed in a direction towards the package substrate (Column 23 lines 1-7: double sided XPU 118. The front side is interpreted as the active side facing substrate 124.)
Regarding claim 3, Karhade discloses the package of claim 1. Karhade further discloses the second integrated device (EIC 114) is configured to be electrically coupled to the optical integrated device (PIC 102) through an electrical path that includes a solder interconnect (Column 7 lines 21-28 and Column 10 lines 45-46) from the second plurality of solder interconnects (Interconnects 130), metallization interconnects (Metallization lines. Column 16 lines 33-37) from the metallization portion (Column 16 lines 55-62), a post interconnect (Interconnect 130) from the first plurality of solder interconnects (Column 16 lines 33-37: Metallization lines providing conductive pathways to and from various elements in the photonic package. Column 7 lines 6-11: conductive pathways connecting one or more dies including non-adjacent layers).
Regarding claim 4, Karhade discloses the package of claim 1. Karhade further discloses the first integrated device (XPU 118) is configured to be electrically coupled to the optical integrated device (PIC 102) through an electrical path that includes a solder interconnect (Column 7 lines 21-28) from the first plurality of solder interconnects (FIG 1A. Column 7 lines 19-28. Column 16 lines 33-37: Metallization lines providing conductive pathways to and from various elements in the photonic package. Column 7 lines 6-11: conductive pathways connecting one or more dies including non-adjacent layers).
Regarding claim 5, Karhade discloses the package of claim 1. Karhade further discloses the second integrated device (EIC 114) is configured to be electrically coupled to the first integrated device (XPU 118) through an electrical path that includes a solder interconnect (Column 19 lines 44-52) from the second plurality of solder interconnects (Interconnects 130), metallization interconnects (Metallization lines. Column 16 lines 33-37) from the metallization portion (Column 16 lines 55-62), a post interconnect from the plurality of post interconnects (Conductive Pillars 152) and a solder interconnect from the first plurality of solder interconnects (Interconnects 130), interconnects from the package substrate (Interconnects 150), and another solder interconnect (Interconnect 130) from the first plurality of solder interconnects (FIG. 1A and FIG. 4. Column 7 lines 19-28. Column 16 lines 33-37: Metallization lines providing conductive pathways to and from various elements in the photonic package. Column 7 lines 6-11: conductive pathways connecting one or more dies including non-adjacent layers).
Regarding claim 6, Karhade discloses the package of claim 1. Karhade further discloses the second integrated device (EIC 114) is configured to be electrically coupled to the first integrated device (XPU 118) through an electrical path that includes a solder interconnect (Column 19 lines 44-52) from the second plurality of solder interconnects (Interconnects 130), metallization interconnects (Metallization lines. Column 16 lines 33-37) from the metallization portion (Column 16 lines 55-62), a post interconnect from the plurality of post interconnects (Conductive Pillars 152) and a solder interconnect from the first plurality of solder interconnects (Interconnects 130), interconnects from the package substrate (Interconnects 150), the optical integrated device (PIC 102), and another solder interconnect (Interconnect 130) from the first plurality of solder interconnects (FIG 1A and FIG 4. Column 7 lines 19-28. Column 11 lines 41-41. Column 16 lines 33-37: Metallization lines providing conductive pathways to and from various elements in the photonic package. Column 7 lines 6-11: conductive pathways connecting one or more dies including non-adjacent layers).
Regarding claim 7, Karhade discloses the package of claim 1. Karhade further discloses comprising a connector socket coupled to the metallization portion, wherein the connector socket is configured to provide an electrical path for power (Column 4 lines 33-45 and Column 7 lines 21-28).
Regarding claim 8, Karhade discloses the package of claim 1. Karhade further discloses the optical integrated device includes a waveguide and a circuit for processing optical signals and/or electrical signals (Colum 3 lines 37-44 and Column 8 lines 12-16).
Regarding claim 9, Karhade discloses the package of claim 1. Karhade further discloses the optical fiber extends through the package substrate (Column 25 lines 47-50).
Regarding claim 10, Karhade discloses the package of claim 1. Karhade further discloses integrated device (XPU 118) includes memory. An XPU implicitly has local memory (e.g. registers or cache).
Regarding claim 11, Karhade discloses a package (FIG. 1A. Photonic Package 100) comprising: a metallization portion (Column 16 lines 55-62. The metallization portion is the area in between 170-1 and 170-2); a first integrated device (XPU 118) coupled to the metallization portion (FIG. 1A. Column 7 lines 19-38. Column 16 lines 55-62) through a first plurality of solder interconnects (Interconnects 130. Column 12 lines 46-48. Solder reflow refers to the formation of solder joints), wherein a front side of the first integrated device is directed in a direction towards the metallization portion (The metallization portion is the area in between 170-1 and 170-2. Column 23 lines 1-7: double sided XPU 118. (Column 23 lines 1-7: double sided XPU 118. The front side is interpreted as the active side facing substrate 124.); an encapsulation layer at least partially encapsulating the first integrated device (FIG 1A. Insulation material 133. Column 7 lines 13-19, Column 12 line 59-Column 13 line 3. The encapsulation layer in interpreted as material used to embed one or more dies in a layer that may include a mold, a resin and/or epoxy); a plurality of post interconnects (Conductive pillars 152) located in the encapsulation layer (FIG 1A); a second integrated device (EIC 114) coupled to the metallization portion through a second plurality of solder interconnects (Interconnects 130. Column 12 lines 46-48. Solder reflow refers to the formation of solder joints); an optical integrated device (PIC 102) coupled to the metallization portion (FIG. 1A. Column 7 lines 19-38. Column 16 lines 55-62) through a third plurality of solder interconnects (Interconnects 130); an optical fiber coupled to the optical integrated device (Column 41 lines 53-55.; and a package substrate (Substrate 124) coupled to the plurality of post interconnects through a fourth plurality of solder interconnects (FIG 1A).
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Regarding claim 12, Karhade discloses the package of claim 11. Karhade further discloses the second integrated device (EIC 114) is coupled to the optical integrated device (PIC 102) through an electrical path that includes a solder interconnect (Column 7 lines 21-28 and Column 10 lines 45-46) from the second plurality of solder interconnects (interconnects 130), metallization interconnects (Metallization lines. Column 16 lines 33-37) from the metallization portion and a solder interconnect from the third plurality of solder interconnects (FIG 1A. Column 7 lines 19-28. Column 11 lines 41-41. Column 16 lines 33-37: Metallization lines providing conductive pathways to and from various elements in the photonic package. Column 7 lines 6-11: conductive pathways connecting one or more dies including non-adjacent layers).
Regarding claim 13, Karhade discloses the package of claim 11. Karhade further discloses the first integrated device (XPU 118) is coupled to the optical integrated device (PIC 102) through an electrical path that includes a solder interconnect (Column 7 lines 21-28 and Column 10 lines 45-46) from the second plurality of solder interconnects (interconnects 130), metallization interconnects (Metallization lines. Column 16 lines 33-37) from the metallization portion and a solder interconnect from the third plurality of solder interconnects (FIG 1A. Column 7 lines 19-28. Column 11 lines 41-41. Column 16 lines 33-37: Metallization lines providing conductive pathways to and from various elements in the photonic package. Column 7 lines 6-11: conductive pathways connecting one or more dies including non-adjacent layers).
Regarding claim 14, Karhade discloses the package of claim 11. Karhade further discloses second integrated device (EIC 114) is coupled to the first integrated device (XPU 118) through an electrical path that includes a solder interconnect (Column 19 lines 44-52) from the second plurality of solder interconnects (Interconnects 130), metallization interconnects (Metallization lines. Column 16 lines 33-37) from the metallization portion (Column 16 lines 55-62), and a solder interconnect from the first plurality of solder interconnects (FIG 1A. and FIG 4. Column 7 lines 19-28. Column 11 lines 41-41. Column 16 lines 33-37: Metallization lines providing conductive pathways to and from various elements in the photonic package. Column 7 lines 6-11: conductive pathways connecting one or more dies including non-adjacent layers).
Regarding claim 15, Karhade discloses the package of claim 11. Karhade further discloses a passive device (Bridge die 202) coupled to the metallization portion (FIG 1A).
Regarding claim 16, Karhade discloses the package of claim 11. Karhade further discloses the passive device (Bridge die 202) is at least partially encapsulated by the encapsulation layer (Insulating material 133. FIG. 1A. Column 7 lines 13-18).
Regarding claim 17, Karhade discloses the package of claim 11. Karhade further discloses a plurality of power rail interconnects (Interconnects 128 and associated conductive traces, planes, vias and pads (Column 12 lines 32-35). Conductive planes serve the same function of a power rail.) located in the encapsulation layer (Insulating material 133. Column 7 lines 13-19).
Regarding claim 19, Karhade discloses the package of claim 11. Karhade further discloses integrated device (XPU 118) includes memory. An XPU implicitly has local memory (e.g. registers or cache).
Regarding claim 20, Karhade discloses the package of claim 11. Karhade further discloses a connector socket coupled to the metallization portion, wherein the connector socket is configured to provide an electrical path for power (Column 4 lines 33-45).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 rejected under 35 U.S.C. 103 as being unpatentable over Karhade et el. (US12392970B2), hereafter Karhade.
Regarding claim 18, Karhade discloses the package of claim 11. Karhade further discloses the plurality of power rails interconnects coupling the first integrated device (XPU 118) and the package substrate (124). Column 12 lines 32-35.
While Karhade does not explicitly disclose the power rails interconnects are located at the back side of 118, the placement of interconnects on the back of a chip is a known technique for power delivery. Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to position the power rails at the back of the integrated device as a matter of routine optimization. Specifically, this placement would be considered a routine design choice to optimize signal routing on the front side or to manage thermal constraints of the XPU 118. Consequently, placing the power rails on the back side constitutes the application of a known technique to a known device to yield predictable results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Karhade et al. (US20220342150A1) sees the entire disclosure.
Ganesan et al. (US20230082706A1) see the entire disclosure.
Karhade et al. (US20220342150A1) see the entire disclosure.
Yu et al. (US20210091056A1) see the entire disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAJANAE N GREEN whose telephone number is (571)272-2188. The examiner can normally be reached Tues-Fri. 5:30a-3:30p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at (571) 272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAJANAE NICOLE GREEN/Examiner, Art Unit 2874
/UYEN CHAU N LE/Supervisory Patent Examiner, Art Unit 2874