CTNF 18/607,181 CTNF 79422 DETAILED ACTION Claims 1-20 are presented for examination. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because claim 20 is directed to “a computer-readable medium”, which, disclosed by the specification, a computer-readable medium can be a transitory machine-readable storage media (See specification, paragraph [0030]). Thus, the recited “a computer-readable medium” is not a process, a machine, a manufacture or a composition matter, as defined in 35 U.S.C. 101. Accordingly, claim 20 fails to recite statutory subject matter under 35 U.S.C. 101. Examiner suggests amending the above claims to add “non-transitory” to obviate the rejection. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 17, 19 and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Roberts et al. (CN 107015845 A - English translation is provided by USPTO) . As to claim 1, Roberts teaches an apparatus for display processing (a computer; page 15, last paragraph), comprising: at least one memory (the software is stored on the tangible storage medium in machine-readable form; page 15, last paragraph); and at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor, individually or in any combination, is configured to (in the form of a computer program comprising computer readable program code for configuring computers for performing part of the method of or to include is adapted to run on a computer when program execution described herein all steps of any method of computer program code tool computer program form, and wherein the computer program can be embodied on a computer readable storage medium. tangible (or temporary) storage medium for example includes magnetic disk, thumb drive, memory card and so on, and does not include propagating signals. Software can be suitable for execution on a parallel processor or a serial processor such that the method steps may be executed in any suitable order or simultaneously; page 15, last paragraph – page 16, 1 st paragraph): configure a virtualization component (the virtualization of the GPU is mediated in the (such as firmware running in the GPU); page 15, 2 nd paragraph and abstract) for a set of workloads associated with a set of virtual machines (VMs) (the GPU is shared between a plurality of VMs (for example on the CPU operation of up to 8 of the VM or can have more than 8 VM running on the CPU) is performed via management programs of all communication between operating system and GPU on the VM; page 6, 1 st paragraph and GPU workloads; abstract and page 4, 1 st paragraph); execute the set of workloads associated with the set of VMs (GPU 54 includes a GPU core 56 comprises hardware (such as data flow quantity bismerthlazol, a shadow cluster, texture pipeline and data post-processing module) to execute GPU task; page 6, last paragraph) for a set of virtual queues (VM queue; page 12, 4 th paragraph and the work on the GPU queue; page 14, 3 rd paragraph); and perform at least one of : (1) a mapping of the set of VMs to the set of virtual queues, (2) a security check for an ability of each of the set of VMs to access a set of software registers (In other implementations, calling management program and the management program as a security agent, and the OS of the additional calling VM ID, and then the method shown in FIG. 3 and the above-mentioned continuously. Because the performance of the microprocessor by an external memory access (because of delay associated with each of the external memory accesses), and kick register comparison for each VM using a single kick register introduces a performance penalty, because many access to HD/FI is needed. In another example, using a mixture of two kinds of method (each VM special kick register and a single kick register). Examples in the presence ratio of the VMOS, kick register can be composed of more than one of the OS-all VM using, for example, the not only the OS-all those VM ID) ID limit. In an implementation, the VM management program, or the microprocessor 58 running firmware code to know is the special OS ID scanning N VM queue; page 12, 2 nd – 4 th paragraphs), or (3) a mapping of each of the set of virtual queues to each of a set of control data paths. As to claim 2, Roberts teaches the apparatus of claim 1, wherein the at least one processor, individually or in any combination, is further configured to: perform a security identifier (ID) check for each ID corresponding to each of the set of VMs, wherein the performance of the security ID check is based on the execution of the set of workloads (Management program also at R-MMU 120 and 122(block 208) in establishing a translation table (also referred to as "page table"), wherein transitioning between the client physical address and the real physical address depends on the OS, and so the conversion table according to the OS R-MMU120, 122 indexed or selected. after the allocating memory and OS-ID (In block 206) and build R-MMU (in block 208), the VM can be loaded (block 25) and may begin executing (block 212). In operation (or execution) stage 204 during VM execution and the OS of the VM for each transaction on system bus 116 by its related-ID identification (block214). The lower the management program may also be assigned its own OS-ID so that it can be used to determine which portion of the management program accessible memory. Since each transaction is for OS-ID tagging, OS-ID effectively provide address space m of more bits. transaction of the is not originated from trigger transaction inherits their OS-ID so that output from the GPU inherited submitted OS of CPU to generate the output-ID; page 9, 1 st – 2 nd paragraphs). As to claim 3, Roberts teaches the apparatus of claim 2, wherein to perform the security ID check, the at least one processor, individually or in any combination, is configured to: perform the security ID check at a memory management unit (MMU) (Management program also at R-MMU 120 and 122(block 208) in establishing a translation table (also referred to as "page table"), wherein transitioning between the client physical address and the real physical address depends on the OS, and so the conversion table according to the OS R-MMU120, 122 indexed or selected. after the allocating memory and OS-ID (In block 206) and build R-MMU (in block 208), the VM can be loaded (block 25) and may begin executing (block 212).; page 9, 1 st paragraph). As to claim 17, Roberts teaches the apparatus of claim 1, wherein the at least one processor, individually or in any combination, is further configured to: obtain an indication of the set of workloads associated with the set of VMs (works/tasks of GPU; page 14, 1 st paragraph, page 6, last paragraph); store the set of workloads associated with the set of VMs in the set of virtual queues (GPU queue; page 14, 3 rd paragraph); and obtain an indication to start an execution of the set of workloads associated with the set of VMs for the set of virtual queues (when the VM (such as a graphics application that is in the VM) wishes to trigger the GPU task, VM control flow is established in a memory (block 302), and which can be finished by conventional manner, such as if the is the VM is a native CPU has an associated GPU. VM then command a command written in the common circular buffer (block 304), i.e., each VM running on the CPU can use the same virtual address and a client physical address to the write command, and the client computer physical address mapped to the HD/FI by the CPU R-MMU 120 VM specific physical address (block 30 6) so that the command may be stored (block30, 8). controlling the flow of the building (in block 302) and storage command (in block 304-308) in the intends the GPU is executed before submitted to the GPU; page 10, 3 rd paragraph). As to claim 19, Roberts teaches a method of display processing (method of GPU virtualization; page 3, last paragraph), comprising: configuring a virtualization component (the virtualization of the GPU is mediated in the (such as firmware running in the GPU); page 15, 2 nd paragraph and abstract) for a set of workloads associated with a set of virtual machines (VMs) (the GPU is shared between a plurality of VMs (for example on the CPU operation of up to 8 of the VM or can have more than 8 VM running on the CPU) is performed via management programs of all communication between operating system and GPU on the VM; page 6, 1 st paragraph and GPU workloads; abstract and page 4, 1 st paragraph); executing the set of workloads associated with the set of VMs (GPU 54 includes a GPU core 56 comprises hardware (such as data flow quantity bismerthlazol, a shadow cluster, texture pipeline and data post-processing module) to execute GPU task; page 6, last paragraph) for a set of virtual queues (VM queue; page 12, 4 th paragraph and the work on the GPU queue; page 14, 3 rd paragraph); and performing at least one of : (1) a mapping of the set of VMs to the set of virtual queues, (2) a security check for an ability of each of the set of VMs to access a set of software registers (In other implementations, calling management program and the management program as a security agent, and the OS of the additional calling VM ID, and then the method shown in FIG. 3 and the above-mentioned continuously. Because the performance of the microprocessor by an external memory access (because of delay associated with each of the external memory accesses), and kick register comparison for each VM using a single kick register introduces a performance penalty, because many access to HD/FI is needed. In another example, using a mixture of two kinds of method (each VM special kick register and a single kick register). Examples in the presence ratio of the VMOS, kick register can be composed of more than one of the OS-all VM using, for example, the not only the OS-all those VM ID) ID limit. In an implementation, the VM management program, or the microprocessor 58 running firmware code to know is the special OS ID scanning N VM queue; page 12, 2 nd – 4 th paragraphs), or (3) a mapping of each of the set of virtual queues to each of a set of control data paths. As to claim 20, Roberts teaches a computer-readable medium storing computer executable code for display processing, the code when executed by at least one processor causes the at least one processor to (the software is stored on the tangible storage medium in machine-readable form; page 15, last paragraph … in the form of a computer program comprising computer readable program code for configuring computers for performing part of the method of or to include is adapted to run on a computer when program execution described herein all steps of any method of computer program code tool computer program form, and wherein the computer program can be embodied on a computer readable storage medium. tangible (or temporary) storage medium for example includes magnetic disk, thumb drive, memory card and so on, and does not include propagating signals. software can be suitable for execution on a parallel processor or a serial processor such that the method steps may be executed in any suitable order or simultaneously; page 15, last paragraph – page 16, 1 st paragraph): configure a virtualization component (the virtualization of the GPU is mediated in the (such as firmware running in the GPU); page 15, 2 nd paragraph and abstract) for a set of workloads associated with a set of virtual machines (VMs) (the GPU is shared between a plurality of VMs (for example on the CPU operation of up to 8 of the VM or can have more than 8 VM running on the CPU) is performed via management programs of all communication between operating system and GPU on the VM; page 6, 1 st paragraph and GPU workloads; abstract and page 4, 1 st paragraph); execute the set of workloads associated with the set of VMs (GPU 54 includes a GPU core 56 comprises hardware (such as data flow quantity bismerthlazol, a shadow cluster, texture pipeline and data post-processing module) to execute GPU task; page 6, last paragraph) for a set of virtual queues (VM queue; page 12, 4 th paragraph and the work on the GPU queue; page 14, 3 rd paragraph); and perform at least one of : (1) a mapping of the set of VMs to the set of virtual queues, (2) a security check for an ability of each of the set of VMs to access a set of software registers (In other implementations, calling management program and the management program as a security agent, and the OS of the additional calling VM ID, and then the method shown in FIG. 3 and the above-mentioned continuously. Because the performance of the microprocessor by an external memory access (because of delay associated with each of the external memory accesses), and kick register comparison for each VM using a single kick register introduces a performance penalty, because many access to HD/FI is needed. In another example, using a mixture of two kinds of method (each VM special kick register and a single kick register). Examples in the presence ratio of the VMOS, kick register can be composed of more than one of the OS-all VM using, for example, the not only the OS-all those VM ID) ID limit. In an implementation, the VM management program, or the microprocessor 58 running firmware code to know is the special OS ID scanning N VM queue; page 12, 2 nd – 4 th paragraphs), or (3) a mapping of each of the set of virtual queues to each of a set of control data paths . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (CN 107015845 A - English translation is provided by USPTO) in view of Thakkar et al. (US 2016/0105456 A1) . As to claim 4, Roberts does not teach wherein the security ID check includes at least one failure, wherein the at least one processor, individually or in any combination, is further configured to: communicate the at least one failure of the security ID check to software. However, Thakkar teaches communicate the at least one failure of the security ID check to software (Compliance checker(s) 204A notify VM transfer manager 202A of data block(s) that fail a compliance check. VM transfer manager 202A, VM transfer manager 202B, or both can take one or more actions, discussed below, in response to failure of a compliance check performed by compliance checker(s) 204A. The action(s) to be taken can be defined by VM transfer policy 212, VM transfer policy 214, or both. In another example, compliance check(s) can be performed by compliance checker(s) 204B in hybridity director 174. VM transfer manager 202A can transfer each data block associated with the selected VM, and VM transfer manager 202B can invoke compliance checker(s) 204B to perform compliance check(s) on data block(s). Compliance checker(s) 204B can notify VM transfer manager 202B of any data block(s) that fail a compliance check; paragraphs [0030]-[0031]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the concepts taught by Thakkar to the system of Roberts because Thakkar teaches a method that allows only VMs that passed the security check can execute in the system, thus improve the security of the system . 07-21-aia AIA Claim s 5-8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (CN 107015845 A - English translation is provided by USPTO) in view of Cheng et al. (CN 116501665 A - English translation is provided by USPTO) . As to claim 5, Roberts does not teach determine whether access is granted for a retrieval of register data for each of the set of workloads; and retrieve the register data for each of the set of workloads associated with the set of VMs based on the access being granted. However, Cheng teaches determine whether access is granted for a retrieval of register data for each of the set of workloads; and retrieve the register data for each of the set of workloads associated with the set of VMs based on the access being granted (determining the first identifier and the first address of the to be accessed from the access generated by the target , wherein the first address represents the position of the to be accessed in the target group; based on the first identification, determining the target group and the target protection corresponding to the target from the preset at least two groups and the preset protection group; determining the access authority of the target to the target group based on the target protection ; In response to the right being , the to be is from the target group based on the first address, and the to be accessed is accessed by the target; page 3, 5 th paragraph and page 11, 1 st – 2 nd paragraphs). It would have been obvious to one of ordinary skill in the art before the effective filed date of the claimed invention to apply the teaching of Cheng to the system of Roberts because Cheng teaches a method that does not need to set complex software program to control the authority of the virtual machine to access the register, and improves the efficiency of the virtual machine to access the register (abstract). As to claim 6, Roberts as modified by Cheng does not teach wherein the register data includes information for configuring software registers at a display processing unit (DPU). However, Roberts teaches the register data includes information for configuring software registers at a graphics processing unit (GPU) (a software configuration that describes or defines hardware, which achieve the above module, function, component, unit or logic (e.g., graphics processing system 202 component), such as HDL (hardware description language) software, as programmable chip used for integrated circuit design or the configuration to achieve the desired function. That is, it can provide a computer readable storage medium having computer readable program code of the form data set is defined with an integrated circuit, which when processed in the integrated circuit manufacturing system configuration system on its code in the manufacturing configuration forming performed herein, the graphics processing system or any method of manufacture comprises any device of the graphics processing system. IC data set may be, for example, suitable HDL for writing computer code such as register transfer level (RTL) code. will now be described processing integrated circuit defining data set at the integrated circuit manufacturing system to configure system to produce graphics processing system example with respect to FIG. 5.; page 16, 3 rd paragraph). It would have been obvious to one of ordinary skill in the art that the concept taught by Roberts that applies to a GPU could have been applied to a DPU. As to claim 7, Roberts as modified by Cheng teaches the apparatus of claim 5, wherein the register data includes a virtual identifier (ID) associated with each of the set of virtual queues (see Cheng: the target protection register may store a virtual machine identifier, and if the virtual machine identifier is the same as the first virtual machine identifier, the target virtual machine is determined to have access rights to the target data register set; page 10, 4 th paragraph). As to claim 8, Roberts as modified by Cheng does not teach the apparatus of claim 5, wherein to retrieve the register data, the at least one processor, individually or in any combination, is configured to: retrieve the register data from a double data rate (DDR) memory after a security identifier (ID) check. However, Roberts teaches retrieve the register data from a memory after a security identifier (ID) check. (providing dedicated GPU register for each VM, and each VM may only see their own GPU register (i.e., access); page 6, 2 nd paragraph and abstract). Thus, Roberts teaches memory in general, and does not teach DDR memory. It would have been obvious to one of ordinary skill in the art that the memory taught by Roberts could be replaced by the DDR memory because DDR memory has a large capacity and allows data to be transferred at a faster rate. As to claim 15, Roberts as modified by Cheng teaches the apparatus of claim 1, wherein to perform the security check, the at least one processor, individually or in any combination, is further configured to: perform the security check regarding whether each of the set of VMs is able to access the set of software registers (see Cheng: determining the first identifier and the first address of the to be accessed from the access generated by the target , wherein the first address represents the position of the to be accessed in the target group; based on the first identification, determining the target group and the target protection corresponding to the target from the preset at least two groups and the preset protection group; determining the access authority of the target to the target group based on the target protection ; In response to the right being , the to be is from the target group based on the first address, and the to be accessed is accessed by the target; page 3, 5 th paragraph and page 11, 1 st – 2 nd paragraphs) . 07-21-aia AIA Claim s 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (CN 107015845 A - English translation is provided by USPTO) in view of Croxford et al. (US 2016/0371808 A1) . As to claim 9, Roberts does not teach the apparatus of claim 1, wherein the at least one processor, individually or in any combination, is further configured to: determine whether access is granted for a configuration of software registers; and configure data for the software registers based on the access being granted, wherein the data includes control information for data processing of a display processing unit (DPU). However, Croxford teaches determine whether access is granted for a configuration of software registers; and configure data for the software registers based on the access being granted (The driver for the graphics processor (for example) could then be configured to allow software applications to access and set these tile signature enable/disable registers, thereby giving the software application the opportunity to control directly whether or not and where (for which frame regions) the signature generation and comparisons take place; paragraph [0297]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of Croxford to the system of Roberts because Croxford teaches a method to provide hardware registers that enable/disable the tile signature comparisons for particular frame regions, such that the signature generation and comparison is only performed for a tile if the register for the frame region in which the tile resides is set (paragraph [0296]). Furthermore, it would have been obvious that the teaching could also be applied to a DPU instead of GPU as taught by Roberts. As to claim 13, Roberts as modified by Croxford teaches the apparatus of claim 1, wherein each of the set of control data paths includes hardware that is used to perform a set of display processing operations, wherein the set of display processing operations includes at least one of: fetching image data from a double data rate (DDR) memory; performing pixel processing; or communicating the pixel processing to a display panel (As is shown in FIG. 10, the process begins for a new output frame to be provided in step 1002. Then, in step 1004, the process comprises initialising to the first region of the output frame (e.g. the top line of the output frame) to be provided. Then, in step 1006, the process comprises initialising the signature for that first region and initialising to the first pixel of that first region (e.g. the first pixel of the top line of the output frame to be provided). Next, in step 1008, the pixel data for the required layers for the first region are fetched from the latency buffers 904, 906, 908. Then, in step 1010, the fetched pixel data is composited. Then, in step 1012, the signature for the region is updated based on composited pixel data. Then, in step 1014, the composited pixel data is buffered in the pixel buffer 912. Next, in step 1016, it is determined whether all of the pixels of the first region have been processed. If there are still some pixels left to be processed, then the next pixel is selected in step 1018 and the process returns to step 1008 to process that next pixel. Conversely, if there are no more pixels left to be processed, then in step 1020, the signature of the corresponding region in the previous frame is fetched using the signature fetch/store circuitry 916; paragraphs [0323]-[0325]) . 07-21-aia AIA Claim s 10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (CN 107015845 A - English translation is provided by USPTO) . As to claim 10, Roberts does not teach determine whether the execution has reached a last workload in the set of workloads; and generate an interrupt for software based on the execution reaching the last workload, wherein the interrupt includes information regarding which VM in the set of VMs triggered the generation of the interrupt. However, Roberts teaches finishing the GPU task can trigger the microprocessor interrupt (block 320), such as that used in the task of the resource can be released for use by another GPU task. And on completion of the interrupt can trigger the start of a GPU workload, such as the GPU task kick but triggered by the previous GPU tasks (the previous GPU task for example using GPU task triggered with the same resource) (page 11, last paragraph – page 12, 1 st paragraph). Given the teaching of Roberts above regarding resource(s) is released for another workload, i.e., the workload is the last workload, and information about the VM must also be provided so the resources for the VM to execute the workload can be released. As to claim 18, Roberts does not clearly teach output an indication of the performance at least one of: (1) the mapping of the set of VMs to the set of virtual queues, (2) the security check for the ability of each of the set of VMs to access the set of software registers, or (3) the mapping of each of the set of virtual queues to each of the set of control data paths, wherein to output the indication of the performance, the at least one processor, individually or in any combination, is configured to: transmit the indication of the performance; or store the indication of the performance. However, Roberts teaches the security check for the ability of each of the set of VMs to access the set of software registers (as set forth in claim 1 above). Roberts further teaches executes the GPU tasks (page 6, last paragraph). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the performance of the security check for the ability of each of the set of VMs to access the set of software registers must be returned/transmitted to the manager/requestor in order for the GPU tasks can be executed . 07-21-aia AIA Claim s 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (CN 107015845 A - English translation is provided by USPTO) in view of Mehta et al. (US 2018/0352474 A1) . As to claim 14, Roberts does not teach perform the mapping of the set of VMs to the set of virtual queues based on a mapping table for the mapping of the set of VMs to the set of virtual queues. However, Mehta teaches perform the mapping of the set of VMs to the set of virtual queues based on a mapping table for the mapping of the set of VMs to the set of virtual queues (Hypervisor 114 may also dynamically adjust the number of NIC queues allocated to pool 405 based on the number of virtual machines that have LRO capability, the amount of traffic destined for such virtual machines, etc. Although one-to-one mapping between NIC queue 121/122/123 between virtual machine 131/132/133 is shown, it should be understood that multiple virtual machines may share a particular NIC queue; paragraph [0034] and [0013]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of Mehta to the system of Roberts because Mehta teaches a method that allows workloads/requests from multiple sources/VMs sent to appropriate queues for processing which is an advantage in the display sharing environment taught by Roberts. As to claim 16, Roberts as modified by Mehta teaches configure a mapping table for the mapping of the set of VMs to the set of virtual queues (see Mehta: Hypervisor 114 may also dynamically adjust the number of NIC queues allocated to pool 405 based on the number of virtual machines that have LRO capability, the amount of traffic destined for such virtual machines, etc. Although one-to-one mapping between NIC queue 121/122/123 between virtual machine 131/132/133 is shown, it should be understood that multiple virtual machines may share a particular NIC queue; paragraph [0034] and [0013]) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: As to claims 11-12, the prior art of record does not teach or render obvious the limitations recited in claims 11-12, when taken in the context of the claims as a whole, specific to generate a busy signal for each of the set of virtual queues and each of the set of control data paths; map the busy signal for each of the set of virtual queues to the busy signal for each of the set of control data paths; and initiate each of a set of display processing operations based on the generation of the busy signal for each of the set of virtual queues and each of the set of control data paths. Moreover, evidence for modifying the prior art teachings by one of ordinary skill level in the art was not uncovered so as to result in the invention as recited in claims 11-12 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Meisner et al. (US 8,972,984 B2) teaches methods and systems for virtualizing audio hardware for one or more virtual machines. A control virtual machine (VM) may translate a first stream of audio functions calls from a first VM hosted by a hypervisor. The translated first stream of audio function calls may be destined for a sound card of the computing device executing the hypervisor. The control VM may detect a second stream of audio functions calls from a second VM hosted by the hypervisor. The control VM may translate the second stream of audio functions calls from the second VM. The control VM may further merge the translated first stream of audio function calls and the translated second stream of the audio function calls in response to the detected second stream. The control VM may transmit the merged stream of audio function calls to the sound card. HE et al. (US 2023/0108461 A1) teaches a circuitry configured to generate at least one virtual device interface to utilize the processor circuitry and provide the at least one virtual device interface to a server to assign to a process to provide the process with capability to utilize the processor circuitry. In some examples, the processor circuitry is to perform one or more of local area network access, cryptographic processing, and/or storage access. In some examples, the storage access comprises access to one or more Non-volatile Memory Express (NVMe) devices. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIEM K CAO whose telephone number is (571)272-3760. The examiner can normally be reached Monday-Friday 8:00am-4:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at 571-270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DIEM K CAO/Primary Examiner, Art Unit 2196 DC June 12, 2026 Application/Control Number: 18/607,181 Page 2 Art Unit: 2196 Application/Control Number: 18/607,181 Page 3 Art Unit: 2196 Application/Control Number: 18/607,181 Page 4 Art Unit: 2196 Application/Control Number: 18/607,181 Page 5 Art Unit: 2196 Application/Control Number: 18/607,181 Page 6 Art Unit: 2196 Application/Control Number: 18/607,181 Page 7 Art Unit: 2196 Application/Control Number: 18/607,181 Page 8 Art Unit: 2196 Application/Control Number: 18/607,181 Page 9 Art Unit: 2196 Application/Control Number: 18/607,181 Page 10 Art Unit: 2196 Application/Control Number: 18/607,181 Page 11 Art Unit: 2196 Application/Control Number: 18/607,181 Page 12 Art Unit: 2196 Application/Control Number: 18/607,181 Page 13 Art Unit: 2196 Application/Control Number: 18/607,181 Page 14 Art Unit: 2196 Application/Control Number: 18/607,181 Page 15 Art Unit: 2196 Application/Control Number: 18/607,181 Page 16 Art Unit: 2196 Application/Control Number: 18/607,181 Page 17 Art Unit: 2196 Application/Control Number: 18/607,181 Page 18 Art Unit: 2196 Application/Control Number: 18/607,181 Page 19 Art Unit: 2196 Application/Control Number: 18/607,181 Page 20 Art Unit: 2196 Application/Control Number: 18/607,181 Page 21 Art Unit: 2196
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