DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-9 are pending in this application.
Response to Amendment
Claim 1 is amended.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama U.S. Patent Application 2005/0116692 (hereinafter “Sugiyama”) and further in view of Nakatani et al. U.S. Patent Application 2008/0203986 (hereinafter “Nakatani”).
Regarding claim 1, Sugiyama teaches a switch device (i.e. switching regulator 200)(fig.3), comprising: a switch element (i.e. switching transistor M1)(fig.3), including: a first end (implicit) to which an input voltage is applicable (refer to Vin)(fig.3); a second end (implicit) to which an output voltage is applicable (refer to Vout)(fig.3); and a control terminal (implicit); a DA converter; and an output voltage control unit (refer to DAC control circuit 202, DAC1, CMP1, PWM control circuit 201 and switching transistor M1)(fig.3), including the switch element (implicit) and configured to control the output voltage (refer to [0030]), wherein the output voltage control unit is configured to generate a control voltage applicable to the control terminal such that the output voltage is gradually increased according to a ramp-like change in an output of the DA converter (refer to abstract and figure 4B); however, Sugiyama does not teach the output voltage control unit is configured to generate the control voltage to have a value higher than the input voltage based on the output voltage reaching the input voltage. However, Nakatani teaches the output voltage control unit is configured to generate the control voltage to have a value higher than the input voltage based on the output voltage reaching the input voltage (refer to comparator circuit 4)(fig.1)(refer also to [0023]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Sugiyama to include the control voltage magnitude of Nakatani to provide the advantage of ensuring proper switch operation (i.e. full turn on/off of the switch) when the output voltage is boosted above the input voltage (refer to Nakatani abstract).
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama and Nakatani as applied to claim 1 above, and further in view of Shida et al. U.S. Patent Application 2014/0118583 (hereinafter “Shida”).
Regarding claim 2, Sugiyama and Nakatani teach the switch device of Claim 1; however, they do not teach the device further comprising: a counter, configured to count clocks and output a count value to the DA converter. However, Shida teaches the device further comprising: a counter (i.e. counter 321)(fig.4), configured to count clocks and output a count value to the DA converter (implicit)(refer to fig.4). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the switch device of Sugiyama and Nakatani to replace DAC control circuit 202 and DAC1 with the ramp generator 320 of Shida to provide the advantage of creating a smoother ramp signal, thereby minimizing overshoot.
Regarding claim 3, Sugiyama, Nakatani, and Shida teach the switch device of Claim 2, wherein a frequency of the clocks is variable (refer to Shida [0066]).
Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama and Nakatani as applied to claim 1 above, and further in view of Jordanger et al. U.S. Patent Application 2019/0393697 (hereinafter “Jordanger”).
Regarding claim 4, Sugiyama and Nakatani teach the switch device of Claim 1, wherein the output voltage control unit includes a component (i.e. Sugiyama CMP1 and PWM control circuit 201)(fig.3) configured to receive a feedback voltage (refer to Sugiyama divided voltage Vd)(fig.3) obtained by dividing the output voltage (implicit) and an input signal based on the output of the DA converter (implicit)(refer to Sugiyama Vref)(fig.3), and output the control voltage (implicit); however, they do not teach wherein the component is an error amplifier. However, Jordanger teaches the component being an error amplifier (refer to driver circuit 704)(fig.7)(refer also to [0034]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Sugiyama and Nakatani to include the error amplifier of Jordanger to provide the advantage of outputting a smoothly ramping control signal to the gate of the switching element in order to prevent overshoot.
Regarding claim 5, Sugiyama, Nakatani and Jordanger teach the switch device of Claim 4, wherein the output voltage at a time the input signal reaches a maximum voltage is less than the input voltage (implicit)(refer to Jordanger fig 7).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama, Nakatani, and Jordanger as applied to claim 4 above, and further in view of Shida.
Regarding claim 9, Sugiyama, Nakatani, and Jordanger teach the switch device of Claim 4; however, they do not teach the device further comprising: a low-pass filter, disposed at an output side of the DA converter and configured to generate the input signal. However, Shida teaches the device further comprising: a low-pass filter (i.e. low-pass filter 323)(fig.4), disposed at an output side of the DA converter (implicit)(refer to DAC 322)(fig.4) and configured to generate the input signal (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the switch device of Sugiyama, Nakatani, and Jordanger to replace DAC control circuit 202 and DAC1 with the ramp generator 320 of Shida to provide the advantage of creating a smoother ramp signal, thereby minimizing overshoot.
Allowable Subject Matter
Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claims 6-8 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 6, especially a booster circuit, configured to boost the output voltage to generate a boosted power supply voltage, wherein the boosted power supply voltage is suppliable to an output stage of the error amplifier, and when the output voltage reaches the input voltage before the input signal reaches a maximum voltage, the error amplifier is configured to be switched from an amplifying operation to a comparing operation, thereby turning the switch element to a full-on state. Sugiyama, Nakatani, Shida, and/or Jordanger do not teach a booster circuit, configured to boost the output voltage to generate a boosted power supply voltage, wherein the boosted power supply voltage is suppliable to an output stage of the error amplifier, and when the output voltage reaches the input voltage before the input signal reaches a maximum voltage, the error amplifier is configured to be switched from an amplifying operation to a comparing operation, thereby turning the switch element to a full-on state. Lin U.S. Patent Application 2013/0002224 (hereinafter “Lin”) teaches a similar device (refer to Lin figure 5); however, Lin does not teach a booster circuit, configured to boost the output voltage to generate a boosted power supply voltage, wherein the boosted power supply voltage is suppliable to an output stage of the error amplifier, and when the output voltage reaches the input voltage before the input signal reaches a maximum voltage, the error amplifier is configured to be switched from an amplifying operation to a comparing operation, thereby turning the switch element to a full-on state.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838