DETAILED ACTION
This office action is in response to a Response After Final Action filed 8/6/2026.
No claims have been amended. No claims have been added. No claims have been cancelled. Thus claims 1-20 have been examined.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 11-12, and 15-20 are rejected under 35 U.S.C. 102 (a)(1) and 35 U.S.C. 102 (a)(2) as being anticipated by Louzoun (Louzoun et al., US 2003/0163654 A1).
Regarding claim 1, Louzoun teaches A method, (Louzoun [Abstract] discloses the invention concepts are directed to a method, system, and apparatus.) comprising: receiving, from a controller and at a bank controller different from the controller (Louzoun Fig. 1 and [0011]-[0018] and most notable [0011] that discloses logic block 102 may be a memory controller that controls memory devices 104 that may be memory banks and thus logic 102 may be a bank controller different from controller 106, where controller 106 forwards commands to the memory device(s). Louzoun [0013] discloses the scheduler within controller 102 receives commands and data from the request source and transfers the data to controller 106 for transmittal to the memory devices.) a command to access a volatile memory device that is coupled with the controller, (Louzoun Fig. 1 and [0011]-[0013] discloses memory devices 104 may be DRAM devices that are examples of volatile memory devices connected to controller 106.) the volatile memory device comprising a channel coupled with a set of banks comprising a first bank and a second bank, (Consistent with para [0014] of the instant application, a channel may be an element configured to communicate data, C/A, and clock information with the memory die. Louzoun [0003] discloses the DRAM devices receive read and write commands via a memory bus coupled to a processor and schedules them to a plurality of banks per Louzoun [0013]. Thus the memory bus may be a channel/bus ash shown in Fig. 1 connected to a first and second bank based on a queueing scheme.)
wherein the channel comprises a set of control channels; (Per para [0068] of the instant application a control channel may be a means for transmitting a sequence of commands to a bank and furthermore “a set of control channels” para [0068] further states the set of control channels may be shared by the first bank and the second bank. Thus there may be a single element (a channel) that contains a set of control channels where each control channel is a means for transmitting a sequence of commands to a first bank or a second bank, and the set of control channels (i.e. the means for transmitting commands to a first bank and a second bank) may be shared. Louzoun [0012]-[0013] discloses the scheduler 108 schedules a plurality of banks using the memory bus thus there are a plurality of sequence of commands scheduled for the plurality of banks over the memory bus of Fig. 1 and thus there may be a set of control channels shared by the first bank and the second bank to control the first and second banks. The means of transmitting a command to the first bank is a first control set and the means of transmitting a command to the second bank is a second control set, where the first and second control set may be shared.)
determining which bank of the set of banks is available to perform the command (Louzoun [0017] discloses the scheduler within logic 102 determines which bank of a plurality of banks is to perform the command. Louzoun [0022] discloses this may be based on if the bank is currently available.)
based at least in part on a type of the command and respective operation types associated with the set of banks; (Louzoun [0018]-[0019] discloses the scheduling may be based on the type of command to schedule such as a read or write command as well as which banks have a request for a read command, the type of the previous command transmitted via the memory bus, thus based on the types associated with the set of banks. Louzoun Fig. 2 and [0022] and [0023] discloses the system first determines which banks could receive an optimal read or write command based at least in part on if the bank is currently available (thus based on respective operation types associated with each bank, thus based on the respective operation types associate with the set of banks).)
selecting, via the bank controller, the first bank of the volatile memory device to perform the command based at least in part on determining which bank of the set of banks is available; (Louzoun Fig. 1 and [0011]-[00017] and [0022]-[0023] discloses logic 102 (the bank controller) may schedule the bank based on if the bank is currently available. Examiner notes the bank scheduled may be the first bank.)
assigning, via the bank controller, the command to the first bank of the volatile memory device based at least in part on selecting the first bank; (Louzoun [0013] discloses the scheduler with the logic 102 (i.e. bank controller) generates commands to the memory device which would include the command to the first bank based on its scheduling algorithm that selects the first bank to be scheduled next.)
determining, via the bank controller, a sequence of commands communicated over the set of control channels based on the command assigned to the first bank and one or more other commands assigned to the second bank associated with the channel (Louzoun [0003] discloses the DRAM devices receive read and write commands via a memory bus coupled to a processor or a memory control and schedules them to a plurality of banks per Louzoun [0013]. Thus there may be a first and second bank that commands are assigned to. Louzoun Fig. 2 and [0022] and [0023] discloses the scheduling to a first bank is based on the received inputs (i.e. based on the command assigned to the first bank) and based on reviewing all received inputs and their bank status (are the associated bank available to receive an optimal read or write command based at least in part on if the associated bank currently has a read or write command. Louzoun [0012]-[0013] discloses the commands are communicated over the set of control commands that manage the transmittal of data over the memory bus).
wherein determining the sequence of commands is based on respective types of the one or more other commands; (Louzoun [0015] discloses the schedule receives status information including which banks have a request for a write command and which banks have requests for read commands and if the bank is currently idle and could receive an optimal read command or write command, thus determines the sequence based on the respective types of the one or more commands.)
and accessing, via the bank controller, the first(Louzoun [0013] discloses the scheduler with the memory controller 102 generates commands to the memory device which would include the command to the first bank based on its scheduling algorithm that selects the first bank to be scheduled next.)
Regarding claim 2, Louzoun teaches the limitations of claim 1 above. Louzoun further teaches further comprising: receiving, from the controller, an indication to prioritize the command over other commands, wherein assigning the command is based on receiving the indication. (Louzoun [0021] teaches the status information received from the controller by the scheduler may include priority information to allow for faster execution that could be for a write command to reset the memory device. The write command to reset the memory device is a command sent based on an indication to prioritize the command over other commands received from the controller as status information.)
Regarding claim 4, Louzoun teaches the limitations of claim 2 above. Louzoun further teaches wherein selecting the first (Louzoun Fig. 1 and [0014] discloses the scheduler receives status information that may indicate a priority write command to per Louzoun [0021] may include priority information for certain types of commands to allow for faster execution that could be a write command to reset the memory device based on a request by the processor. Thus the priority write to reset the memory device will be scheduled at the first bank by the scheduler based on the priority indication.)
Regarding claim 5, Louzoun teaches the limitations of claim 1 above. Louzoun further teaches further comprising: initiating a media management operation for the volatile memory device based on accessing the first bank. (Louzoun Fig. 1 and [0014] discloses the scheduler receives status information that may indicate a priority write command to per [0021] reset the memory device to allow for faster execution. The priority write to reset the memory device is an example of a media management operation for the volatile memory device.)
Regarding claim 11, Louzoun teaches the limitations of claim 1 above. Louzoun further teaches further comprising: identifying a first performance parameter of the first bank and a second performance parameter of the second bank, wherein assigning the command to the first bank is based on the first performance parameter and the second performance parameter. (Louzoun Fig. 2 steps 204 and 206 and [0022]-[0023] discloses the system determines what mode the memory banks are in (read or write mode) to avoid a bank turn-around when scheduling memory requests. Thus the current mode of each bank (including a first and second bank) is an example of a performance parameter for each bank that is used to schedule/assign a command to the first bank based on the performance parameters.)
Regarding claim 12, Louzoun teaches the limitations of claim 1 above. Louzoun further teaches wherein determining the sequence of commands further comprises: determining a priority of the command and a duration of pendency of the command, wherein determining the sequence of commands is based on the priority and the duration of pendency. (Consistent with paragraph [0079] of the instant application a means for determining a duration of pendency of the command is determining any element that affects the duration of the command or the time frame that the command may wait to execute (the duration of its pendency. Louzoun [0022] discloses that the commands can be sent to a memory device/bank based on the command type currently executing at the memory bank. The type of command currently executing at the memory bank is an example of a duration of pendency of the command since the type of command currently executing affects how long the command must wait to execute if it is to execute a bus turnaround. Louzoun [0021] teaches sending commands is based on a priority commands. Thus, determining the sequence of commands to send to the memory devices is based on the command priorities as well as the duration of pendency.)
Regarding claim 15, Louzoun teaches An apparatus, (Louzoun [Abstract] discloses the invention concepts are directed to a method, system, and apparatus.) comprising: a first die; (consistent with para [0021] of the instant application a die may be a chip. Louzoun [0011] discloses logic block 102 may be a chipset, thus a plurality of chips that control the memory devices and there may be a first chip.)
one or more controllers associated with the first die; (Louzoun Fig. 1 and [0011]-[0017] that discloses with logic block 102 that makes up the chipset and may be a memory controller.) an interface block coupled with the first die, (Louzoun [0011]-[0017] discloses Logic block 102 that is an example of an interface block coupled with the first die) the interface block comprising one or more bank controllers; (Louzoun Fig. 1 and [0011]-[0017] that discloses controller 106 that is a component of the chipset) a second die; (Louzoun Fig. 1 and [0011]-[0017] that discloses logic 102 that may be a chipset, thus there may be a plurality of chips, therefore there may be a second die/chip.)
and a volatile memory device coupled with the second die, (Louzoun Fig. 1 and [0011]-[]0017] that discloses memory devices 104 that are coupled with the logic 102 that make up a chipset, including a second die.) the volatile memory device comprising: a first bank of memory cells; a second bank of memory cells; (Louzoun Fig. 1 and [0011] that discloses there are a plurality of banks and [0001] discloses the memory devices may be composed of memory cell arrays, thus there may be a first bank of memory cells and a second bank of memory cells.) and a first channel coupled with the first bank and the second bank, (Louzoun [0003] discloses the DRAM devices receive read and write commands via a memory bus coupled to a processor or a memory control and schedules them to a plurality of banks per Louzoun [0013]. Thus there may be a first and second bank connected via the memory bus/channel of Fig. 1.)
wherein the first channel comprises a set of control channels, ((Per para [0068] of the instant application a control channel may be a means for transmitting a sequence of commands to a bank. Louzoun [0013] discloses the scheduler 108 schedules a plurality of banks thus there are a plurality of sequence of commands scheduled for the plurality of banks over the memory bus of Fig. 1.)
the interface block being configured to schedule access operations for the first bank and the second bank of the volatile memory device (Louzoun [0017] discloses the scheduler within logic 102 determines which bank of a plurality of banks is to perform the command, including for a first and second bank.) based on commands received from the one or more controllers, (Louzoun Fig. 1 and [0011]-[0017] discloses the scheduler within logic 102 schedules the memory based on information from controller 106.)
wherein the interface block is further configured to: determine which bank of a set of banks is available to perform the commands (Louzoun [0017] discloses the scheduler within logic 102 determines which bank of a plurality of banks is to perform the command. Louzoun [0022] discloses this may be based on if the bank is currently available.) based at least in part on a type of command and respective operation types associated with the set of banks; (Louzoun [0018]-[0019] discloses the scheduling may be based on the type of command to schedule such as a read or write command as well as which banks have a request for a read command, the type of the previous command transmitted via the memory bus, thus based on the types associated with the set of banks.)
select the first bank of the volatile memory device to perform the commands; (Louzoun may schedule the bank based on if the bank is currently available, where the bank scheduled may be the first bank.)
and access the first bank and the second bank of the volatile memory device via the one or more bank controllers. (Louzoun [0003] discloses the SDRAMS memory devices receive read and write commands via a memory bus coupled to a processor or a memory control and schedules them to a plurality of banks per Louzoun [0013]. Thus there may be a first and second bank accessed by the logic 102.)
Regarding claim 16, Louzoun teaches the limitations of claim 15 above. Louzoun further teaches wherein the interface block is further configured to: assign a command of the commands received from the one or more controllers to the first bank of the volatile memory device; (Louzoun [0013] discloses the scheduler with the memory controller 102 (the interface block) generates commands to the memory device which would include the command to the first bank based on its scheduling algorithm that selects the first bank to be scheduled next based on information from controller 106.)
and receive, from the one or more controllers, an indication to prioritize the command over other commands. (Louzoun [0021] teaches the status information received from the controller by the scheduler may include priority information to allow for faster execution that could be for a write command to reset the memory device. The write command to reset the memory device is a command sent based on an indication to prioritize the command over other commands received from the controller as status information.)
Regarding claim 17, Louzoun teaches the limitations of claim 15 above. Louzoun further teaches wherein the interface block is further configured to: initiate a media management operation for the volatile memory device. (Louzoun Fig. 1 and [0014] discloses the scheduler within the logic 102 receives status information that may indicate a priority write command to per [0021] reset the memory device to allow for faster execution. The priority write to reset the memory device is an example of a media management operation for the volatile memory device.)
Regarding claim 18, Louzoun teaches the limitations of claim 15 above. Louzoun further teaches wherein the interface block is further configured to: identify a first performance parameter of the first bank and a second performance parameter of the second bank. (Louzoun Fig. 2 steps 204 and 206 and [0022]-[0023] discloses the system determines what mode the memory banks are in (read or write mode) to avoid a bank turn-around when scheduling memory requests. Thus the current mode of each bank (including a first and second bank) is an example of a performance parameter for each bank that is used to schedule/assign a command to the first bank based on the performance parameters.)
Regarding claim 19, Louzoun teaches the limitations of claim 15 above. Louzoun further teaches wherein the interface block is further configured to: determine a priority of a command received from the one or more controllers and a duration of pendency of the command. (Consistent with paragraph [0079] of the instant application a means for determining a duration of pendency of the command is determining any element that affects the duration of the command or the time frame that the command may wait to execute (the duration of its pendency). Louzoun [0022] discloses that the commands can be sent to a memory device/bank based on the command type currently executing at the memory bank. The type of command currently executing at the memory bank is an example of a duration of pendency of the command since the type of command currently executing affects how long the command must wait to execute if it is to execute a bus turnaround. Louzoun [0021] teaches sending commands is based on a priority commands. Thus, determining the sequence of commands to send to the memory devices is based on the command priorities as well as the duration of pendency.)
Regarding claim 20, Louzoun teaches A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: (Louzoun Claim 28 discloses the inventive concepts may be implemented using a storage medium having stored thereon instructions that, when executed by a computing platform.)
The remainder of claim 20 recite limitations described in claim 1 above and thus is rejected based on the teaching and rationale of claim 1 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Louzoun (Louzoun et al., US 2003/0163654 A1) as detailed in claim 2 and further in view of Williams (Williams et al., US 7,035,908 B1)
Regarding claim 3, Louzoun teaches the limitations of claim 2 above. However Louzoun does not explicitly teach further comprising: inserting the command at a front of a queue associated with the first bank based on receiving the indication, wherein determining the sequence of commands is based on inserting the command at the front of the queue.
Williams, of a similar field of endeavor, further teaches further comprising: inserting the command at a front of a queue associated with the first bank based on receiving the indication, wherein determining the sequence of commands is based on inserting the command at the front of the queue. (Louzoun [0017] discloses the logic 102 may use a bank based queueing schedule to determine the specific bank to receive a command. Louzoun [0021] discloses the system may schedule a priority write command to reset the memory device. Williams teaches a message circuit that pass messages within a memory architecture. Williams [Summary of the invention] and column 3, lines 49-55 taches that a system may maintain a queue for command processing where the commands at the front of the queue are for urgent messages and the rest of the queue is for normal processing. Urgent (i.e. priority) commands are placed at the front of the FIFO queue if there is no other urgent messages pending.)
Louzoun and Williams are in a similar field of endeavor as both relate to computer implemented solutions. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the concept of a single queue containing both normal and priority requests in a single queue as taught by Williams into the solution of Louzoun. Thus combining prior art elements according to known methods (using a single queue with priority commands placed at the front of the queue as taught by Williams into the solution of Louzoun that maintains a queue and with priority commands) to yield predictable results; (Simplify the hardware/circuitry for implementing a memory FIFO to provide orderly command passing between multiple system components while maintaining high priority and normal priority commands. See Williams column 4 lines 31-48.)
Claims 6-10 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Louzoun (Louzoun et al., US 2003/0163654 A1) as detailed in claim 1 and 5 above and further in view of Oh (OH, US 2023/0326511 A1).
Regarding claim 6, Louzoun teaches the limitations of claim 5 above. However, Louzoun does not explicitly teach wherein initiating the media management operation further comprises: detecting a possibility of one or more errors caused by a row hammer event based on accessing the first bank; and initiating a row hammer mitigation operation based on detecting the possibility.
Oh, of a similar field of endeavor, further teaches wherein initiating the media management operation further comprises: detecting a possibility of one or more errors caused by a row hammer event based on accessing the first bank; and initiating a row hammer mitigation operation based on detecting the possibility. (Examiner notes that, consistent with para [0049] of the instant application, a media management operation may be a row hammer mitigation, refresh, error control, or repair operation. Oh [Abstract] discloses a memory device that includes a row hammer management circuity and a refresh control circuit. The row hammer management circuit tracks what cell rows have been intensively accessed, and issues refresh operations on the adjoining rows to reduce the effects of the row hammer operations and would do so for the volatile memory devices of the solution of Hall in view of Akamatsu. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices of Hall may be volatile memory devices.)
Louzoun and Oh are all in a similar field of endeavor as all relate to computer implemented solutions. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed data of the claimed invention to incorporate the row hammer / refresh control circuitry of Oh into the solution of Louzoun, thus combining prior art elements according to known methods (the row hammer mitigation of Oh using row/column decoders into the solution of Louzoun that schedules memory commands including memory management commands to a memory) to yield predictable results; (a memory controller that schedules memory access commands and results in fewer errors in the memory access requests caused by row hammer threats that are known to create memory access errors when responding to access requests.)
The motivation to incorporate Oh into the solution of Louzoun for claims 7-10 are the same as set forth in claim 6 above.
Regarding claim 7, Louzoun teaches the limitations of claim 5 above. However, Louzoun does not explicitly teach wherein initiating the media management operation further comprises: initiating a refresh operation for the first bank based on accessing the first bank.
Oh, of a similar field of endeavor, further discloses wherein initiating the media management operation further comprises: initiating a refresh operation for the first bank based on accessing the first bank. Oh [Abstract] and [0006] discloses a memory device that includes a row hammer management circuity and a refresh control circuit. The row hammer management circuit tracks what cell rows have been intensively accessed, and issues refresh operations on the adjoining rows to reduce the effects of the row hammer operations. The refresh operation is an example of a media management operation initiated for adjoining rows of the memory device which are rows within the same memory bank in the solution of Louzoun that would be a volatile memory bank per Louzoun [0011] that disclose the first and second memory devices may be DRAM memory devices which are examples of volatile memory devices.)
The motivation to combine Oh into Louzoun is the same as set forth in claim 6 above.
Regarding claim 8, Louzoun teaches the limitations of claim 5 above. However, Louzoun does not explicitly teach wherein initiating the media management operation further comprises: initiating a repair operation to repair a row, a column, or a through-silicon via of the first bank based on accessing the first bank.
Oh, of a similar field of endeavor, further discloses wherein initiating the media management operation further comprises: initiating a repair operation to repair a row, a column, or a through-silicon via of the first bank based on accessing the first bank. (Oh [Abstract], [0006], and [0239] discloses a memory device that includes a row hammer management circuity and a refresh control circuit. The row hammer management circuit tracks what cell rows have been intensively accessed, and issues refresh operations on the adjoining rows to reduce the effects of the row hammer operations. The refresh operation is an example of a media management operation initiated to repair voltage degradation/fluctuations in adjoining rows of the memory device that degrade quickly and are repaired via a refresh where the adjoining rows are rows within the same memory bank that in the solution of Louzoun that are volatile banks per Louzoun [0011] that disclose the first and second memory devices may be DRAM memory devices which are examples of volatile memory devices.)
The motivation to combine Oh into Louzoun is the same as set forth in claim 6 above.
Regarding claim 9, Louzoun teaches the limitations of claim 5 above. However, Louzoun does not explicitly teach wherein initiating the media management operation further comprises: initiating an error control operation for the first bank based on accessing the first bank.
Oh, of a similar field of endeavor, further discloses wherein initiating the media management operation further comprises: initiating an error control operation for the first bank based on accessing the first bank. (Examiner notes that repairing degraded voltages is an example of providing an error control operation as it reduces errors in adjoining rows to a row experience an unusually high level of activity that degrades the adjoining cell voltages. Oh [Abstract], [0006], and [0239] discloses a memory device that includes a row hammer management circuity and a refresh control circuit. The row hammer management circuit tracks what cell rows have been intensively accessed, and issues refresh operations on the adjoining rows to reduce the effects of the row hammer operations. The refresh operation is an example of a media management operation initiated to repair voltage degradation/fluctuations in adjoining rows of the memory device that degrade quickly and are repaired via a refresh where the adjoining rows are rows within the same memory bank that in the solution of Louzoun that are volatile banks per Louzoun [0011] that disclose the first and second memory devices may be DRAM memory devices which are examples of volatile memory devices.)
The motivation to combine Oh into Louzoun is the same as set forth in claim 6 above.
Regarding claim 10, Louzoun teaches the limitations of claim 5 above. However, Louzoun does not explicitly teach
wherein the media management operation is initiated without receiving instructions from the controller.
Oh, of a similar field of endeavor, further discloses wherein the media management operation is initiated without receiving instructions from the controller. (Oh [Abstract], [0006], and [0239] discloses the media management operation of a refresh operation is triggered by the row hammer management circuit and the refresh control circuit. Oh Fig. 1 and supporting para [0054] and [0057] discloses that the row hammer management circuit 500 is contained within the Semiconductor Memory Device 200 containing DRAM memory that is an example of the DRAM memory of Louzoun.)
The motivation to combine Oh into Louzoun is the same as set forth in claim 6 above.
Regarding claim 13, Louzoun teaches the limitations of claim 1 above.
Louzoun [0001] teaches the memory cell array is arranged as a matrix of rows and columns. But does not explicitly teach wherein determining the sequence of commands further comprises: determining a first sequence of commands for the first bank including row commands and columns commands associated with the first sequence of commands; and determining a second sequence of commands for the second bank including row commands and column commands associated with the second sequence of commands, wherein the sequence of commands communicated over the set of control channels of the channel are based on the row commands and the column commands associated with the first sequence of commands and the row commands and the column commands associated with the second sequence of commands.
Oh, of a similar field of endeavor, further teaches wherein determining the sequence of commands further comprises: determining a first sequence of commands for the first bank including row commands and columns commands associated with the first sequence of commands; (Louzoun [0013] discloses the schedule schedules commands to a plurality of banks, thus to a first bank that may be to a memory array arranged as a matrix of rows and columns. Oh Fig. 3 and [0074]-[0079] discloses this is performed by issuing commands to row decoders and column address requests from the controller. Thus the scheduling of Louzoun first bank would be performed by a sequent of row commands and column commands associated with the first bank of Louzoun).
and determining a second sequence of commands for the second bank including row commands and column commands associated with the second sequence of commands, (Louzoun [0013] discloses the schedule schedules commands to a plurality of banks, thus to a second bank that may be to a memory array arranged as a matrix of rows and columns. Oh Fig. 3 and [0074]-[0079] discloses this is performed by issuing commands to row decoders and column address requests from the controller. Thus the scheduling of Louzoun first bank would be performed by a sequent of row commands and column commands associated with the second bank of Louzoun).
wherein the sequence of commands communicated over the set of control channels of the channel are based on the row commands and the column commands associated with the first sequence of commands and the row commands and the column commands associated with the second sequence of commands. (Louzoun [0013] discloses the schedule schedules commands to a plurality of banks, thus to first and second banks that may be to a memory array arranged as a matrix of rows and columns. Oh Fig. 3 and [0074]-[0079] discloses this is performed by issuing commands to row decoders and column address requests from the controller to the respective bank.)
The motivation to combine Oh into Louzoun is the same as set forth in claim 6 above.
Regarding claim 14, Louzoun teaches the limitations of claim 1 above.
Louzoun [0001] teaches the memory cell array is arranged as a matrix of rows and columns. But does not explicitly teach further comprising: determining whether a column command or a row command or both are to be communicated over the set of control channels of the channel as part of performing the command, wherein determining the sequence of commands is based on determining whether the column command or the row command or both are to be communicated.
Louzoun in view of Oz further teaches further comprising: determining whether a column command or a row command or both are to be communicated over the set of control channels of the channel as part of performing the command, wherein determining the sequence of commands is based on determining whether the column command or the row command or both are to be communicated. Louzoun [0013] discloses the schedule schedules commands to a plurality of banks, thus to first and second banks that may be to a memory array arranged as a matrix of rows and columns. Oh Fig. 3 and [0074]-[0079] and [0094] discloses this is performed by issuing commands to row decoders and column address requests from the controller to the respective bank by a command decoder 211 that processes commands.)
The motivation to combine Oh into Louzoun is the same as set forth in claim 6 above.
Response to Remarks
Examiner thanks applicant for their claim amendments and remarks of 8/6/2026. They have been fully considered.
Applicant argues on page 8 of their remarks ‘Louzoun Does Not Disclose a "Bank Controller Different from the Controller"
Independent claim 1 recites "receiving, from a controller and at a bank controller different from the controller, a command to access a volatile memory device that is coupled with the controller." This limitation expressly requires two distinct entities: (1) a controller, and (2) a bank controller that is "different from" the controller. The bank controller receives commands from the controller.
The Office Action maps both the "controller" and the "bank controller" to the same element-logic block 102 of Louzoun. Specifically, the Office Action states that Louzoun's "logic block 102 may be a memory controller and thus may be a bank controller different from controller 102." (Office Action at 3.) This mapping is internally contradictory: it identifies the same structural element (logic block 102) as both the "controller" that sends commands and the "bank controller" that receives them. A single element cannot simultaneously be "different from" itself.’
Examiner agrees. Thus a second Final Office Action is enclosed.
Applicant argues on page 8 of their remarks ‘Louzoun's logic block 102 is a unitary structure comprising a command request source 110, a scheduler 108, and a controller 106, all integrated within the same logic block. (Louzoun, Fig. 1, " [0011]-[0012].) Nowhere does Louzoun disclose that any component within logic block 102 operates as a separate "bank controller" that receives commands from a separate "controller." To the contrary, the command flow in Louzoun proceeds from the processor to the command request source 110, then to the scheduler 108, and finally through controller 106 to the memory devices. (Louzoun, 11 [0012]-[0013].) Controller 106 is positioned downstream of the scheduler and functions merely to forward scheduled commands to the memory bus-it does not send commands to a separate bank controller for further scheduling decisions.”
Examiner respectfully notes applicant is arguing a limitation not recited in the claims. The claim recites the limitation “a bank controller different from the controller”. The claim does not recite the limitation “separate”. Logic 102 that is an example of a bank controller is different from Controller 106.
Applicant argues on pages 8-9 of their remarks ‘The claimed architecture requires a distinct hierarchical relationship: a controller sends a command to a bank controller, and the bank controller (which is different from the controller) then performs the subsequent operations of determining which bank is available, selecting a bank, assigning the command, and determining a sequence of commands. Louzoun simply does not disclose this two-tier architecture. Because Louzoun fails to disclose a "bank controller different from the controller" that receives commands from the controller, Louzoun cannot anticipate claim 1.’
Examiner respectfully disagrees. As noted above, Louzoun discloses a hierarchical structure where logic 102 (that may be a memory controller that controls memory banks thus is an example of a bank controller) contains controller 102 and logic 102 is different from controller 106. Louzoun teaches the claimed “bank controller different from the controller”.
Applicant argues on page 9 of their remarks ‘Louzoun Also Does Not Disclose a Channel Comprising a "Set of Control Channels".
Claim 1 further recites that "the volatile memory device comprising a channel coupled with a set of banks comprising a first bank and a second bank, wherein the channel comprises a set of control channels." This limitation defines a structured channel hierarchy: a channel couples with the banks, and within that channel are multiple control channels.
The Office Action maps this limitation to the single memory bus of Louzoun's Figure 1 and paragraph [0003]. However, Louzoun discloses only a single memory bus connecting the logic block 102 to the memory devices 104. (Louzoun 1 [0003].) Louzoun does not disclose that this memory bus comprises a "set of control channels" within it. A single undifferentiated bus is not a "channel" that "comprises a set of control channels." The claim requires multiple control channels within the channel structure-a concept entirely absent from Louzoun.’
Examiner respectfully disagrees. First, applicant is arguing a limitation not claimed. The claim does not recite a “structured channel hierarchy”. The claim recites “a channel, … wherein the channel comprises a set of control channels”. Thus the channel contains set of control channels. One interpretation of the “hierarchy” applicant is referring to may simply be that the “channel” may be a single element that contains a “set of control channels” along with other elements. The upper level “channel” may be the name of a component that contains multiple sub-components (lower level elements in the “hierarchy”) including “a set of control channels”. As noted in the office action, “the channel” may simply be a bus. And the bus may further contain “a set of control channels”. Per para [0068] of the instant application a control channel may be a means for transmitting a sequence of commands to a bank and furthermore “a set of control channels” para [0068] notes the set of control channels may be shared by the first bank and the second bank. Examiner notes that the “a set of control channels” may be logical or physical. Thus there may be a single element (a channel) that contains a set of control channels where each control channel is a means for transmitting a sequence of commands to a first bank or a second bank, and the set of control channels (i.e. the means for transmitting commands to a first bank and a second bank) may be shared. Louzoun [0013] discloses the scheduler 108 schedules a plurality of banks thus there are a plurality of sequence of commands scheduled for the plurality of banks over the memory bus of Fig. 1 and thus there may be a set of control channels shared by the first bank and the second bank to control the first and second banks. The means of transmitting a command to the first bank is a first control set and the means of transmitting a command to the second bank is a second control set, where the first and second control set may be shared.)
Applicant argues on pages 8-9 of their remarks ‘Louzoun further Does Not Disclose Determining a Sequence of Commands Communicated Over the Set of Control Channels
Claim 1 recites "determining, via the bank controller, a sequence of commands communicated over the set of control channels based on the command assigned to the first bank and one or more other commands assigned to the second bank associated with the channel, wherein determining the sequence of commands is based on respective types of the one or more other commands."
This limitation requires the bank controller to affirmatively determine a sequence of commands to be communicated over the control channels, where that determination is based on both: (a) the command assigned to the first bank, and (b) one or more other commands assigned to the second bank-specifically based on the respective types of those other commands. This describes a control-channel-level sequencing decision that considers the interplay between commands destined for different banks.
The Office Action maps this to Louzoun's description that the scheduler receives status information including which banks have requests for write commands and which have requests for read commands. (Office Action at 5, citing Louzoun 1 [0015].) But Louzoun's scheduler determines which bank to schedule next and what type of command to issue-it does not determine a "sequence of commands communicated over the set of control channels" based on commands already assigned to both a first bank and a second bank. Louzoun's scheduler operates at the bank-selection level (choosing which bank gets the next command), not at the control-channel sequencing level (determining how commands already assigned to multiple banks are ordered for transmission over control channels).
There is a fundamental distinction between Louzoun's bank-level scheduling (selecting which bank receives a command next based on status information) and the claimed control- channel-level sequencing (determining how a sequence of commands for multiple banks is communicated over control channels). Louzoun does not contemplate the claimed sequencing operation, which requires awareness of commands already assigned to both the first and second banks and determining a transmission sequence over the control channels based on those assignments and their respective types.
Examiner respectfully disagrees. As noted in the office action above, Louzoun [0022]-[0023] discloses making scheduling decisions based on (1) the received inputs (i.e. read and/or write requests) and (2) which banks could receive an optimal read or write command based at least in part on if the bank is currently available.
First, applicant is arguing a limitation not claimed. The claim recites “determining.. a sequence of commands communicated.. based on the command assigned to the first bank and one or more other commands assigned to the second bank associated with the channel, wherein determining the sequence of commands is based on respective types of the one or more other commands”. The claims do not require a ‘sequencing operation, which requires awareness of commands already assigned to both the first and second banks and determining a transmission sequence over the control channels based on those assignments and their respective types’.
Louzoun further discloses scheduling which bank receives a command next is based on the status information of the bank and its ability to issue an optimum read or write command based on if the target bank is idle (thus is or is not executing a previous command) and thus takes into account (is based on) one or more previously issued commands that may running, thus preventing the bank from being idle. Louzoun takes into consideration the command type (read or write). Thus Louzoun teaches the claimed “determining.. a sequence of commands communicated.. based on the command assigned to the first bank and one or more other commands assigned to the second bank associated with the channel, wherein determining the sequence of commands is based on respective types of the one or more other commands”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M. GIROUARD whose telephone number is (469)295-9131. The examiner can normally be reached M-F 9:30 - 7:30.
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138
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