DETAILED ACTION
This office action is in response to a Request for Continued Examination (RCE) filed 11/7/2025 for application 18/607,283 that claims priority to provisional application 63/457,703 filed 4/6/2023.
Claims 1, 3-9, 11, 13, 15-16, 18, and 20 have been amended. No claims are new. No claims have been cancelled. Thus, claims 1-20 have been examined.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/7/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 11-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hall (Hall, JR. et al., US 2018/0364919 A1) in view of Akamatsu (Akamatsu US 11,011,212 B1).
Regarding claim 1, Hall teaches A method, comprising: receiving, from a controller, (Hall [0001] discloses the application is directed to a method of using host memory controllers 108-1 to 108-N to send data to a Memory Systems 104-1 to 104-N, thus discloses N controllers that send data to the memory systems 104-N. Thus the memory system receive commands from the host controllers.) a command to access a volatile memory device that is coupled with the controller, (Hall Figs 1 & 2 and supporting paras [0008] and [0015]-[0025] discloses a host memory controller (i.e. the controller) sends commands to a first memory device and to a second memory device (such as Memory Device 110-1 and 110-2. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile memory devices. ) the volatile memory device comprising a channel coupled with a set of volatile banks comprising a first volatile bank and a second volatile bank, (Examiner notes that the instant application does not contain an explicit definition for the term “set of” and Examiner has interpreted the phrase “set of” to be a “collection of one or more”. Examiner further notes that consistent with paragraph [0026] of the instant application, a channel may be a bus (i.e. signal paths with terminals). Thus the claim recites the limitation of a bus/channel coupled with one or more banks comprising a first volatile memory bank and a second volatile memory bank. Hall Fig. 1 and supporting para [0016]-[0017] that discloses channel 112-1 coupled with memory system 104-1 contains memory circuitry such as DRAM 110-1 to 110-X that are memory devices within the claimed ‘memory device’ (i.e. the combination of 112-1 and 104-1.) See also Hall Fig. 1 and supporting para [0015] that disclose the first (110-1) and second memory (one of 110-2 to 110-X) may be volatile memory.) wherein the channel comprises a first set of data channels dedicated to the first volatile bank, (Hall Figs. 1 and 2 and supporting paras [0017] and [0025] discloses that signals between host 102 and memory devices memory devices 110-1 to 110-X are communicated using a data bus over channel 112-1. Thus the data bus in channel 112-1 communicating with memory devices 110-1 is an example of a first set of data channels. Examiner notes that per Fig. 2 and supporting para [0025] that discloses that select line 222 may be used to dedicate the data bus to memory device 110-1 for a period of time. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile memory devices.) a second set of data channels dedicated to the second volatile bank, (Hall Fig. 1 and supporting para [0017] discloses that signals between host 102 and memory devices memory devices 110-1 to 110-X are communicated using a data bus over channel 112-1. Fig. 2 and supporting para [0025] discloses that select line 224 may be used to dedicate the data bus to memory device 110-X for a period of time, thus the data bus in channel 112-1 is an example of a second set of data channels dedicated to a second memory. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile memory devices. ) and a set of control channels shared by the first volatile bank and the second volatile bank; (Hall Figs. 1 to 3 and supporting paras [0025]-[0027] discloses that there may be a single command/address (C/A) bus 328 that outputs commands from the Host Memory Controller 308 of Fig. 3 (and 108-1 of Fig. 1 ) to the memory devices 110-1 to 110-X which share access to the command/access bus 228 using select signals 222 and 224 where the command/address bus is an example of a set of control channels shared by the memory devices 110-1 to 110-X. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile memory devices.) selecting the first volatile bank of the volatile memory device to perform the command based at least in part on receiving the command; (Hall Figs 1 & 2 and supporting paras [0009] and [0017]-[0025] (most notably [0020] that discloses a third address set may identify separate devices within the 110- series ) discloses a host memory controller uses the address range to select a memory device as the target of the access request and select signal 222 causes the commands in command/address bus 228 to be routed to (i.e. assigned to) a specific memory device such as the first memory device 110-1. ) assigning the command to the first volatile bank of the volatile memory device; (Hall Figs 1 & 2 and supporting paras [0017]-[0025] discloses select signal 222 causes the commands in command/address bus 228 to be routed to (i.e. assigned to) first memory device 110-1. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile memory devices.) based at least in part on selecting the first volatile bank; (Hall Figs 1 & 2 and supporting paras [0017]-[0025] discloses a host memory controller uses the address range to select a memory device as the target of the access request and select signal 222 causes the commands in command/address bus 228 to be routed to (i.e. assigned to) first memory device 110-1.) determining a sequence of commands communicated over the set of control channels based on the command assigned to the first volatile bank and one or more other commands assigned to the second volatile bank associated with the channel; (Examiner notes that consistent with para [0070] a sequence of commands may be a single command. Hall [0020] and [0027]-[0028] discloses there may be a first and second command and each may contain an address and the target of each command may be sent to the memory devices such as 110-1 and 110-X based on an address range assigned to the memory device. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile memory devices. Thus the solution of Hall may identify a sequence of commands communicated over the control channels (the control channels in 112-1 .. 112-M) based on the address that targets (assigns to) the first volatile memory device 110-1 or the second volatile memory device 110-X based on the commands address.)
and accessing, via a bank controller different from the controller, the first bank of the volatile memory device based on determining the sequence of commands. (Hall [0020] and [0027]-[0028] discloses the system may route the commands containing an address associated with the first set of memory to the first memory device and the target device will access the memory based on receiving the command. Hall Fig. 1 discloses X Controllers 114 within the X memory devices 110-(1 to X) within each memory system 104-(1-X), where each controller 114 within each memory device 110(1 to X) control access the memory device based on the commands from the Host memory Controller, where the controllers 114 are different from the host memory controller 108-(1 to N) (i.e. ‘the controller)).
Hall discloses sending memory commands to memory devices such as memory devices 110-1 to 110-X, and 110-1 to 110-Y, etc.. but does not explicitly disclose those memory devices consist of a memory bank. Thus Hall does not explicitly disclose the volatile memory device comprising a set of volatile banks comprising a first volatile bank and a second volatile bank, wherein the channel comprises a first set of data channels dedicated to the first volatile bank, a second set of data channels dedicated to the second volatile bank, and a set of control channels shared by the first volatile bank and the second volatile bank; selecting the first volatile bank of the volatile memory device to perform the command based at least in part on receiving the command; assigning the command to the first volatile bank of the volatile memory device based at least in part on selecting the first volatile bank; determining a sequence of commands communicated over the set of control channels based on the command assigned to the first volatile bank and one or more other commands assigned to the second volatile bank associated with the channel; and accessing, via a volatile bank controller different from the controller, the first volatile bank of the volatile memory device based on determining the sequence of commands.
Akamatsu, of a similar field of endeavor, further discloses the volatile memory device comprising a channel coupled with a set of banks comprising a first bank and a second bank, wherein the channel comprises a first set of data channels dedicated to the first bank, a second set of data channels dedicated to the second bank, and a set of control channels shared by the first bank and the second bank; selecting the first volatile bank of the volatile memory device to perform the command based at least in part on receiving the command; assigning the command to the first bank of the volatile memory device based at least in part on selecting the first volatile bank; determining a sequence of commands communicated over the set of control channels based on the command assigned to the first bank and one or more other commands assigned to the second bank associated with the channel; and accessing, via a bank controller different from the controller, the first bank of the volatile memory device based on determining the sequence of commands. (Akamatsu discloses a memory device may include one or more memory dies. Each memory die may include a local memory controller 165 and a memory array where the memory array may be one or more memory banks. Thus the solution of Hall that discloses a memory device with a memory die that contains a memory array in view of Akamatsu teaches a memory device with a memory die that contains a memory array that may be one or more memory banks controlled by the local memory controller 165 that is an example of a bank controller as it controls memory in a memory bank. Additionally, examiner notes in the solution of Hall in view of Akamatsu the memory array may contain just one memory bank per array. There may be one array within each Memory Die, and there may be one memory die within each memory device 110. See Akamatsu col. 4, lines 45-60. Thus 101-1 may contain a single Memory Array 170-a, and a second 101-2 through X may contain a single Memory Array 170-a and commands received may be directed based on an address within the request to either the first volatile bank in the first 101-1 DRAM or the second volatile bank in second DRAM (101-2 through X) based on the address associated with each volatile bank.)
Hall and Akamatsu are in a similar field of endeavor as both are related to computer implemented solutions directed to DRAM memory. Thus, it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the concept of a memory array including a plurality of memory banks for DRAM memory arrays as disclosed by Akamatsu that discloses that a memory array may support one or more memory banks. Thus using a known technique to improve similar devices (methods, or products) in the same way (such as supporting a plurality of banks within a memory array of a DRAM memory as taught by Akamatsu into the DRAM memory of Hall, and as further described on pages 70-76 of course notes titled 18-447 Computer Architecture Lecture 21: Main Memory by Prof Onur Mutlu disclosed in the relevant art section) ). One would be motivated to do so in order to support a plurality of memory banks of DRAM memory that enable concurrent DRAM access.
The motivation for combining Akamatsu into Hall for claims 2-14 is the same as disclosed in claim 1 above.
Regarding claim 2, the combination of Hall and Akamatsu teaches all of the limitations of claim 1 above. Hall further teaches further comprising: receiving, from the controller, an indication to prioritize the command over other commands, wherein assigning the command is based on receiving the indication. (Hall [0021] discloses that the address associated with a command may be used to prioritize the command, thus the address is an example of “an indication to prioritize the command over other commands” and the command is assigned to a given bank based on receiving the command with an address (i.e. the indication).)
Regarding claim 4, the combination of Hall and Akamatsu teaches all of the limitations of claim 1 above.
Hall in view of Akamatsu further teaches wherein selecting the first volatile bank to perform the command is based on receiving the indication. (Halls Fig. 2 and supporting para [0025] that discloses that select line 222 may be used to dedicate the data bus 226 and the command/address bus 228 to memory device 110-1 (i.e. selecting the first memory bank in the solution of Hall in view of Akamatsu) to perform the command for the address that assigned the command as a priority command per Hall [0021]. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile memory devices.))
The motivation to combine the bank of Akamatsu into the solution of Hall is the same as set forth in claim 1 above.
Regarding claim 11, the combination of Hall and Akamatsu teaches all of the limitations of claim 1 above.
Hall in view of Akamatsu further teaches further comprising: identifying a first performance parameter of the first volatile bank and a second performance parameter of the second volatile bank, wherein assigning the command to the first volatile bank is based on the first performance parameter and the second performance parameter. (Hall [0021] discloses that the commands can be sent to a memory device/ (i.e. bank in the solution of Hall in view of Akamatsu) based on the a priority assigned to the command based on the number of commands in a command queue for the device and the types of commands in the command queue. The number and type of commands in the command queue for a device are both an example of a performance parameter of each device (including the first bank) since the number of commands and the type of commands the device must execute affects how quickly the device may responds which is an example of a performance parameter of the device. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile memory devices in the solution of Hall in view of Akamatsu.)
The motivation to combine the bank of Akamatsu into the solution of Hall is the same as set forth in claim 1 above.
Regarding claim 12, the combination of Hall and Akamatsu teaches all of the limitations of claim 1 above. Hall further teaches wherein determining the sequence of commands further comprises: determining a priority of the command and a duration of pendency of the command, wherein determining the sequence of commands is based on the priority and the duration of pendency. (Consistent with paragraph [0079] of the instant application a means for determining a duration of pendency of the command is determining any element that affects the duration of the command or the time frame that the command may wait to execute (the duration of its pendency). Hall [0021] discloses that the commands can be sent to a memory device/bank based on the a priority assigned to the command based on two factors (1) the address that is the target of the command and (2) the number of commands in a command queue for the device and the types of commands in the command queue. The number and type of commands in the command queue for a device are an example of a duration of pendency of the command since the number of commands and the type of commands the device must execute affects how long the command must wait to execute. Thus, determining the sequence of commands to send to the memory devices is based on the command priorities.)
Regarding claim 13, the combination of Hall and Akamatsu teaches all of the limitations of claim 1 above.
Hall in view of Akamatsu further teaches wherein determining the sequence of commands further comprises: determining a first sequence of commands for the first volatile bank including row commands and columns commands associated with the first sequence of commands; (Hall [0020] and [0027]-[0028] discloses there may be a first command to the first memory identified by the address of the first command and the solution of Hall may identify a first sequence of commands (which may be the data, and address/control commands associated with the first command) that communicated over the data and address/control buses of channel 112-1 and are associated with the first command sent to the first memory device (i.e. first memory bank in the solution of Hall in view of Akamatsu that may be a volatile memory bank per that in the solution of Hall in view of Akamatsu that are volatile banks per Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile.).)
and determining a second sequence of commands for the second volatile bank including row commands and column commands associated with the second sequence of commands, (Hall [0020] and [0027]-[0028] discloses there may be a second command to the second memory identified by a the address of the second command and the solution of Hall may identify a second sequence of commands (which may be the data, and address/control commands associated with the second command) communicated over the control channel 112-1 and are associated with the second command sent to the second memory device (i.e. second memory bank in the solution of Hall in view of Akamatsu that are volatile banks per Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile.).)
wherein the sequence of commands communicated over the set of control channels of the channel are based on the row commands and the column commands associated with the first sequence of commands and the row commands and the column commands associated with the second sequence of commands. (Hall [0020] and [0027]-[0028] discloses there may be a first command to the first memory and a second command to the second memory and each may contain an address which defines the target of each command based on an address range assigned to the memory device. Thus the solution of Hall may identify both a first and second sequence of commands (consisting of data and address/control commands) communicated over the control channel 112-1 where the values associated with the data and address/control bus for each command are examples of row commands and column commands associated with the sequence of commands. The sequence of commands may be the first and second sequence of commands sent to the first and second memories, thus the sequence of commands communicated over the set of control channels are based on row commands and column commands associated with the first and second sequence of commands.)
The motivation to combine the bank of Akamatsu into the solution of Hall is the same as set forth in claim 1 above.
Regarding claim 14, the solution of Hall and Akamatsu teaches all of the limitations of claim 1 above. Hall further teaches further comprising: determining whether a column command or a row command or both are to be communicated over the set of control channels of the channel as part of performing the command, wherein determining the sequence of commands is based on determining whether the column command or the row command or both are to be communicated. (Hall [0024] discloses that the memory system 104-1 to 104-N contain address circuitry to latch address signals including a row decoder and column decoder provided through the command/address bus. Hall Fig. 3 and supporting para [0026] discloses the system uses a select memory device to identify the target memory device of the command/address bus using the address of the command. Thus it is determining whether the column/row decoder at the respective memory device should receive the command (are to be communicated over the control channel as a part of processing the address while performing the command. The step of determining the sequence of commands from claim 1 that is the step of identifying the address is based on whether the command should be sent to (communicated with) the first memory device or second memory device.)
Regarding claim 15, Hall teaches An apparatus, (Hall Fig. 1 and supporting [0004] discloses Fig. 1 discloses an apparatus.) comprising: a first die; (Hall Figs 1 &2 and supporting paras [0006] and [0015] discloses the memory devices 101-1 to 101-X may be apparatus and an apparatus per the application may be a circuit or a die.) one or more controllers associated with the first die; (Hall Fig. 1 and supporting para [0015] that discloses controller 114 associated with memory device/die 110-1.) an interface block coupled with the first die, the interface block comprising one or more bank controllers; (Examiner notes that consistent with para [0081] of the instant application an interface block may be a component of the system that schedules die commands for execution by a memory device/block. Hall para [0015] discloses controller 114 receive commands from the host using channel 112-1 and controls execution of the commands on the memory device, thus a combination of Channel 112 and the Controller 114 is an example of an interface block coupled to a die (such as die 110-1))
a second die; and a volatile memory device coupled with the second die, (Hall Fig. 1 and supporting para [0015] discloses a plurality of memory devices 110-1 to 110-X, 110-1 to 110-Y, etc. that may be memory die and is an example of a second die containing volatile memory and is an example of a second die that is a volatile memory device coupled with the second die.)
the volatile memory device (Hall Figs. 1 and 2 and supporting paras [0009] and [0025] that consists of Memory System 104-1 with Controller 112-1 that is an example of a volatile memory device. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile.) comprising: a first volatile bank of memory cells; (Hall Fig. 1 and supporting paras [0023] that discloses memory device 110-1 that is an example of a first device containing memory cells. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile.) a second volatile bank of memory cells; (Hall Fig. 1 and supporting paras [0023] that discloses memory device 110-X that is an example of a second device containing memory cells. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile.) and a first channel coupled with the first volatile bank and the second volatile bank, (Hall Figs. 1 & 2 and supporting paras [0015] that discloses channel 112-1 that contains a command/address channel that sends control data to Memory Device 110-1 and 110-X. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile.) the first channel comprises a first set of data channels dedicated to the first volatile bank, (Examiner notes that consistent with paragraph [0026] of the instant application, a channel may be a bus (i.e. signal paths with terminals). Examiner notes that the instant application does not contain an explicit definition for the term “set of” and Examiner has interpreted the phrase “set of” to be a “collection of one or more”. Hall Fig. 1 and supporting para [0017] discloses that signals between host 102 and memory devices memory devices 110-1 to 110-X are communicated using data buses over channel 112-1. Thus the data bus in channel 112-1 communicating with memory devices 110-1 to 110-x is an example of a first set of data channels (one or more data buses) communicating over channel 112-1. Examiner notes that per Fig. 2 and supporting para [0025] that discloses that select line 222 may be used to dedicate the data bus to memory device 110-1, an example of a first memory. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile.) a second set of data channels dedicated to the second volatile bank, Hall Fig. 1 and supporting para [0017] discloses that signals between host 102 and memory devices memory devices 110-1 to 110-X are communicated using a data bus over channel 112-1. Thus the data buses in channel 112-1 communicating with memory devices 110-X is an example of a second set of data channels communicating over channel 112-1. Examiner notes that per Fig. 2 and supporting para [0025] that discloses that select line 224 may be used to dedicate the data bus to memory device 110-X for a period of time, an example of a second memory. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile.) and a set of control channels shared by the first volatile bank and the second volatile bank; (Hall Fig. 1 element 328 and supporting paras [0025]-[0027] disclose that there may be a single command/address (C/A) bus 328 that outputs commands from the Host Memory Controller 308 of Fig. 3 (and 108-1 of Fig. 1 ) to the memory devise 110-1 to 110-X which share access to the command/access bus 228 using select signals. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile.)
and the interface block being configured to schedule access operations for the first volatile bank and the second volatile bank of the volatile memory device (Hall [0020] and [0027]-[0028] discloses there may be a first and second command and each may contain an address and the target of each command may be sent to the memory devices based on an address range assigned to the memory device. Thus the solution of Hall may identify a sequence of commands communicated over the control channels (the control channels in 112-1 .. 11M that are a component of the interface block) and select and send (i.e. schedule) the commands based on the commands received whose target address is to the first memory device and whose target address is to the second memory device. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile.) based on commands received from the one or more controllers, (Hall [0016]-[0017] discloses Host Controllers 108-1 to 108-N sends commands to the Memory Systems 104-1 to 104-N containing memory devices using the control channels 112-1 to 112-N.) wherein the interface block is further configured to select the first volatile bank of the volatile memory device to perform the commands and (Hall [0020] and [0027]-[0028] discloses there may be a first and second command and each may contain an address and the target of each command may be sent to the memory devices based on an address range assigned to the memory device. Thus the solution of Hall may identify a sequence of commands communicated over the control channels (the control channels in 112-1 .. 11M) based on the commands received whose target address is to the first memory device. Hall [0028] discloses that the command targets are selected by the channel such as 112-1 using selection signals as detailed in Fig. 2 and para [0025]. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile.)
However Hall does not explicitly discloses banks, thus doesn’t explicitly disclose ‘the interface block comprising one or more bank controllers, a first bank of memory cells; a second bank of memory cells; and a first channel coupled with the first bank and the second bank, the first channel comprises a first set of data channels dedicated to the first bank, a second set of data channels dedicated to the second bank, and a set of control channels shared by the first bank and the second bank; and the interface block being configured to schedule access operations for the first bank and the second bank of the volatile memory device…, wherein the interface block is further configured to access the first bank and the second bank of the volatile memory device via the one or more bank controllers.’
Akamatsu, of a similar field of endeavor, further discloses ‘the interface block comprising one or more bank controllers, a first bank of memory cells; a second bank of memory cells; and a first channel coupled with the first bank and the second bank, the first channel comprises a first set of data channels dedicated to the first bank, a second set of data channels dedicated to the second bank, and a set of control channels shared by the first bank and the second bank; and the interface block being configured to schedule access operations for the first bank and the second bank of the volatile memory device’. (Akamatsu discloses a memory device that may include one or more memory dies. Each memory die may include a local memory controller 165 and a memory array where the memory array may be one or more memory banks. Thus the solution of Hall that discloses a memory device with a memory die that contains a memory array in view of Akamatsu teaches a memory device with a memory die that contains a memory array that may be one or more memory banks controlled by the local memory controller 165 that is an example of a bank controller as it controls memory in a memory bank. Additionally, examiner notes in the solution of Hall in view of Akamatsu the memory array may contain just one memory bank per array. There may be one array within each Memory Die, and there may be one memory die within each memory device 110. See Akamatsu col. 4, lines 45-60. Thus 101-1 may contain a single Memory Array 170-a, and a second 101-2 through X may contain a single Memory Array 170-a and commands received may be directed based on an address within the request to either the first volatile bank in the first 101-1 DRAM or the second volatile bank in second DRAM (101-2 through X) based on the address associated with each volatile bank.)
wherein the interface block is further configured to access the first bank and the second bank of the volatile memory device via the one or more bank controllers.(Akamatsu column 4 lines 45-60 discloses a memory device 110 that may include a Device Memory Controller 155 and one or more memory dies (e.g. memory die 160-a to 160-N each with a local memory controller 165 and a memory array where the memory array may include one or more memory banks), thus the memory controller 165 may control a first bank and a second bank and Memory Device 110 may be a Memory Device 110-1 of Hall. The Device Memory Controller 155 may control access to a first Memory Die 160-a or a second Memory Die 160-b to 160-N within the Memory Device 110, thus the Device Memory Controller 155 is an example of a Memory Device within the interface block and discloses a memory device with a memory die that contains a memory array in view of Akamatsu teaches a bank controller and controls access to two or more DRAM (volatile ) memory banks (i.e. a first bank and a second bank).)
Hall and Akamatsu are in a similar field of endeavor as both are related to computer implemented solutions directed to DRAM memory. Thus, it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the concept of a memory array including a plurality of memory banks for DRAM memory arrays as disclosed by Akamatsu that notes that a memory array may support one or more memory banks. Thus using a known technique to improve similar devices (methods, or products) in the same way (such as supporting a plurality of banks within a memory array of a DRAM memory as taught by Akamatsu into the DRAM memory of Hall). One would be motivated to do so in order to support a plurality of memory banks typical of DRAM memory that enable concurrent DRAM access, thus reduce DRAM access latency.
The motivation for combining Akamatsu into Hall for claims 16-19 is the same as disclosed in claim 15 above.
Regarding claim 16, The combination of Hall and Akamatsu teaches all of the limitations of claim 15 above.
Hall in view of Akamatsu further teaches wherein the interface block is further configured to: assign a command of the commands received from the one or more controllers to the first volatile bank of the volatile memory device; (Hall [0020] and [0027]-[0028] discloses the system may route (i.e. assign) the commands containing an address associated with the first set of memory to the first memory device). See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile. Thus the solution of Hall that discloses a memory device with a memory die that contains a memory array in view of Akamatsu teaches a memory device with a memory die that contains a memory array that may be one or more memory banks controlled by the Device Memory Controller 155 that is an example of an interface block will assign commands received from the one or more Host memory Controllers 108-1 to the first volatile bank.)
and receive, from the one or more controllers, an indication to prioritize the command over other commands. (Hall [0021] discloses that the address associated with a command may be used to prioritize the command, thus the address is an example of “an indication to prioritize the command over other commands” and the command is assigned to a given bank based on receiving the command with an address (i.e. the indication). The one or more controllers includes the address on the command/address bus 328, where the address is an example of an indication to prioritize the command over other commands.)
The motivation for combining Akamatsu into Hall is the same as disclosed in claim 15 above.
Regarding claim 18, The combination of Hall and Akamatsu teaches all of the limitations of claim 15 above. Hall further teaches wherein the interface block is further configured to: (Hall [0020] and [0027]-[0028] discloses the system may route (i.e. assign) the commands containing an address associated with the first set of memory to the first memory device). Thus the solution of Hall that discloses a memory device with a memory die that contains a memory array in view of Akamatsu teaches a memory device with a memory die that contains a memory array that may be one or more memory banks controlled by the Device Memory Controller 155 that is a component of an interface block and will assign commands based on priority received from the one or more controllers.)
The remainder of claim 18 recites limitations described I claim 11 above and thus is rejected based on the teachings and rationale of claim 11 above.
Regarding claim 19, The combination of Hall and Akamatsu teaches all of the limitations of claim 15 above. Hall further teaches wherein the interface block is further configured to: (Hall [0020] and [0027]-[0028] discloses the system may route (i.e. assign) the commands containing an address associated with the first set of memory to the first memory device). Thus the solution of Hall that discloses a memory device with a memory die that contains a memory array in view of Akamatsu teaches a memory device with a memory die that contains a memory array that may be one or more memory banks controlled by the Device Memory Controller 155 that is a component of an interface block will assign commands based on priority received from the one or more controllers.)
determine a priority of a command received from the one or more controllers and a duration of pendency of the command. (Consistent with paragraph [0079] of the instant application a means for determining a duration of pendency of the command is determining any element that affects the duration of the command or the time that a command may wait to execute (the duration of its pendency). (Hall [0021] discloses that the commands can be sent to the memory devices based on the a priority assigned to the commands based on two factors (1) the address that is the target of the command and the number of commands in a command queue for the device and the types of commands in the command queue. The number and type of commands in the command queue for a device are an example of aa duration of pendency of the command since the number of commands and the type of commands the device must execute affects how long the command must wait to execute. Determining the sequence of commands to send to the memory devices is based on the command priorities. )
Regarding claim 20, A non-transitory computer-readable medium storing code, the code comprising instructions (Hall [0022] discloses the memory controllers may be implemented in firmware which is an example of non-transitory computer-readable medium storing code.) instructions executable by a processor to: (Hall [0009] and [0022] discloses the hosts such as host 102 contains a host processor coupled to the memory devices via a channel that may execute the firmware in host memory controller 108.)
The remainder of claim 20 recites limitations described in claim1 above and thus is rejected based on the teaching and rationale of claim 1 above.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hall (Hall, JR. et al., US 2018/0364919 A1) in view of Akamatsu (Akamatsu US 11,011,212 B1) as detailed in claim 1 above and further in view of Williams (Williams et al., US 7,035,908 B1).
Regarding claim 3, the combination of Hall and Akamatsu teaches all of the limitations of claim 1 above. Hall further teaches further comprising: inserting the command at a front of a queue associated with the first volatile bank based on receiving the indication, wherein determining the sequence of commands is based on inserting the command at the front of the queue. (Hall [0021] teaches prioritizing commands based on the address. Hall Fig. 3 and supporting para [0026] teaches the host memory controller contains a command queue 338 associated with the memories/banks (i.e. thus associated with the first bank). See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile memory devices.)
However the combination does not explicitly teach that the command is prioritized by placing it at a front of the queue. Thus does not explicitly teach at a front of a queue.. at the front of the queue.
Williams, of a similar field of endeavor, further teaches at a front of a queue.. at the front of the queue (Williams teaches a message circuit that pass messages within a memory architecture. Williams [Summary of the invention] and column 3, lines 49-55 teaches that a system may maintain a queue for command processing where the commands at the front of the queue are for urgent messages and the rest of the queue is for normal processing. Urgent (i.e. priority) commands are placed at the front of the FIFO queue if there is no other urgent messages pending.)
Hall, Akamatsu, and Williams are all in a similar field of endeavor as all relate to computer implemented solutions. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the concept of a single queue containing both normal and priority requests in a single queue as taught by Williams into the solution of Hall and Akamatsu. Thus combining prior art elements according to known methods (using a single queue with priority commands placed at the front of the queue as taught by Williams into the solution of Hall and Akamatsu that maintains a queue and with priority commands) to yield predictable results; (Simplify the hardware/circuitry for implementing a memory FIFO to provide orderly command passing between multiple system components while maintaining high priority and normal priority commands. See Williams column 4 lines 31-48.)
Claims 5-10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hall (Hall, JR. et al., US 2018/0364919 A1) in view of Akamatsu (Akamatsu US 11,011,212 B1) as detailed in claims 1 and 15 above and further in view of Oh (OH, US 2023/0326511 A1).
Regarding claim 5, the combination of Hall and Akamatsu teaches all of the limitations of claim 1 above. However, the combination does not explicitly disclose further comprising: initiating a media management operation for the volatile memory device based on accessing the first volatile bank.
Oh, of a similar field of endeavor, further teaches further comprising: initiating a media management operation for the volatile memory device based on accessing the first volatile bank. (Examiner notes that, consistent with para [0049] of the instant application, a media management operation may be a row hammer mitigation, refresh, error control, or repair operation. Oh [Abstract] discloses a memory device that includes a row hammer management circuity and a refresh control circuit. The row hammer management circuit tracks what cell rows have been intensively accessed, and issues refresh operations on the adjoining rows to reduce the effects of the row hammer operations and would do so for the volatile memory devices of the solution of Hall in view of Akamatsu. See also Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices of Hall may be volatile memory devices.)
Hall, Akamatsu, and Oh are all in a similar field of endeavor as all relate to computer implemented solutions. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed data of the claimed invention to incorporate the row hammer / refresh control circuitry of Oh into the solution of Hall and Akamatsu, thus combining prior art elements according to known methods (the row hammer mitigation of Oh into the solution of Hall and Akamatsu that sends host memory commands to a memory) to yield predictable results; (a memory device that can receive memory commands from a host that may be a laptop computer, digital camera, digital recording and playback device, mobile telephone, etc.. that receives memory access commands to support the host and results in fewer errors in the memory access requests caused by row hammer threats that are known to create memory access errors when responding to host requests.)
The motivation to incorporate Oh into the solution of Hall and Akamatsu for claims 6-10 are the same as set forth in claim 5 above.
Regarding claim 6, Hall, Akamatsu, and Oh teaches all of the limitations of claim 5 above.
Oh further teaches wherein initiating the media management operation further comprises: detecting a possibility of one or more errors caused by a row hammer event based on accessing the first volatile bank; and initiating a row hammer mitigation operation based on detecting the possibility. (Oh [Abstract] discloses a memory device that includes a row hammer management circuity and a refresh control circuit. The row hammer management circuit tracks what cell rows have been intensively accessed and thus indicate a possibility of errors, and issues refresh operations on the adjoining rows to reduce the effects of the row hammer operations. The refresh operation is an example of a media management operation initiated based on detecting the possibility of a row hammer data corruption by the row hammer management circuit of a target address directed to a memory bank in the solution of Hall in view of Akamatsu that is directed to volatile memory per Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile memory devices.)
The motivation to combine Oh into the existing combination is the same as set forth in claim 5 above.
Regarding claim 7, the combination of Hall, Akamatsu, and Oh teaches all of the limitations of claim 5 above.
Oh further teaches wherein initiating the media management operation further comprises: initiating a refresh operation for the first volatile bank based on accessing the first bank. (Oh [Abstract] and [0006] discloses a memory device that includes a row hammer management circuity and a refresh control circuit. The row hammer management circuit tracks what cell rows have been intensively accessed, and issues refresh operations on the adjoining rows to reduce the effects of the row hammer operations. The refresh operation is an example of a media management operation initiated for adjoining rows of the memory device which are rows within the same memory bank in the solution of Hall in view of Akamatsu that would be a volatile memory bank per Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile memory devices.)
The motivation to combine Oh into the existing combination is the same as set forth in claim 5 above.
Regarding claim 8, the combination of Hall, Akamatsu, and Oh teaches all of the limitations of claim 5 above.
Oh further teaches wherein initiating the media management operation further comprises: initiating a repair operation to repair a row, a column, or a through-silicon via of the first volatile bank based on accessing the first volatile bank. (Oh [Abstract], [0006], and [0239] discloses a memory device that includes a row hammer management circuity and a refresh control circuit. The row hammer management circuit tracks what cell rows have been intensively accessed, and issues refresh operations on the adjoining rows to reduce the effects of the row hammer operations. The refresh operation is an example of a media management operation initiated to repair voltage degradation/fluctuations in adjoining rows of the memory device that degrade quickly and are repaired via a refresh where the adjoining rows are rows within the same memory bank that in the solution of Hall in view of Akamatsu that are volatile banks per Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile memory devices.)
The motivation to combine Oh into the existing combination is the same as set forth in claim 5 above.
Regarding claim 9, the combination of Hall, Akamatsu, and Oh teaches all of the limitations of claim 5 above.
Oh further teaches wherein initiating the media management operation further comprises: initiating an error control operation for the first volatile bank based on accessing the first volatile bank. (Examiner notes that repairing degraded voltages is an example of providing an error control operation as it reduces errors in adjoining rows to a row experience an unusually high level of activity that degrades the adjoining cell voltages. Oh [Abstract], [0006], and [0239] discloses a memory device that includes a row hammer management circuity and a refresh control circuit. The row hammer management circuit tracks what cell rows have been intensively accessed, and issues refresh operations on the adjoining rows to reduce the effects of the row hammer operations. The refresh operation is an example of a media management operation initiated to repair voltage degradation/fluctuations in adjoining rows of the memory device that degrade quickly and are repaired via a refresh where the adjoining rows are rows within the same memory bank that in the solution of Hall in view of Akamatsu are volatile banks per Hall Fig. 1 and supporting para [0015] that disclose the first and second memory devices may be volatile memory devices.)
The motivation to combine Oh into the existing combination is the same as set forth in claim 5 above.
Regarding claim 10, the combination of Hall, Akamatsu, and Oh teaches all of the limitations of claim 5 above.
Oh further teaches wherein the media management operation is initiated without receiving instructions from the controller. (Oh [Abstract], [0006], and [0239] discloses the media management operation of a refresh operation is triggered by the row hammer management circuit and the refresh control circuit. Oh Fig. 1 and supporting para [0054] and [0057] discloses that the row hammer management circuit 500 is contained within the Semiconductor Memory Device 200 containing DRAM memory that is an example of the memory devices 110-1 to 110-X etc. that may be DRAM memory per Hall [0015].)
The motivation to combine Oh into the existing combination is the same as set forth in claim 5 above.
Regarding claim 17, the combination of Hall and Akamatsu teaches all of the limitations of claim 15 above. Hall further teaches wherein the interface block is further configured to: (Hall [0020] and [0027]-[0028] discloses the system may route (i.e. assign) the commands containing an address associated with the first set of memory to the first memory device). Thus the solution of Hall that discloses a memory device with a memory die that contains a memory array in view of Akamatsu teaches a memory device with a memory die that contains a memory array that may be one or more memory banks controlled by the local memory controller 165 that is an example of an interface block will be configured to initiate commands received from the one or more controllers.)
However, the combination does not explicitly teach wherein the interface block is further configured to: initiate a media management operation for the volatile memory device.
Oh, of a similar field of endeavor, further teaches wherein the interface block is further configured to: initiate a media management operation for the volatile memory device. (Examiner notes that, consistent with para [0049] of the instant application, a media management operation may be a row hammer mitigation, refresh, error control, or repair operation. Oh [Abstract] discloses a memory device that includes a row hammer management circuity and a refresh control circuit. The row hammer management circuit tracks what cell rows have been intensively accessed, and issues refresh operations on the adjoining rows to reduce the effects of the row hammer operations. See also Oh Fig. 36 and supporting paras [0301]-[0303] that discloses an external memory controller 1010 that external to the memory modules 1020 and/or 1030 (the memory devices) connected on a bus 1040 may initiate the commands.)
Hall, Akamatsu, and Oh are all in a similar field of endeavor as all relate to computer implemented memory solutions. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed data of the claimed invention to incorporate the row hammer / refresh control circuitry of Oh into the solution of Mall and Akamatsu, thus combining prior art elements according to known methods (the row hammer mitigation of Oh into the solution of Hall and Akamatsu that sends host memory commands to a memory) to yield predictable results; (a memory device that can receive memory commands from a host that may be a laptop computer, digital camera, digital recording and playback device, mobile telephone, etc.. that receives memory access commands to support the host and results in fewer errors in the memory access requests caused by row hammer threats that are known to create memory access errors when responding to host requests.)
The motivation to incorporate Oh into the solution of Hall and Akamatsu for claims 18-19 are the same as set forth in claim 17 above.
Response to Remarks
Examiner thanks applicant for their claim amendments and remarks of 10/24/2025. They have been fully considered. However, they are not persuasive in light of the claim rejections above and remarks below.
Applicant argues on page 8 of their remarks ‘First, the Office Action improperly equates Halls separate memory devices (110-1, 110-X) with banks within a single volatile memory device. However claim 1 specifically states that “a volatile memory device compris[es] a channel coupled with a set of volatile banks.”
Examiner respectfully notes that Examiner cites Hall in view of Akamatsu to teaches a memory device comprises a channel coupled with a set of volatile banks. Hall alone is not cited to teach the claim limitations of Applicant’s remarks. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
As noted above Hall in view of Akamatsu teaches the limitations. Hall [0015]-[0024] teaches both a Host Memory Controller 108-1, Channels 112-1 to 112-M, and Memory Devices 104-1 to 104N, where the claimed memory device may be a Channel such as 112-1 in combination with a memory system such as Memory System 104-1 and per Hall [0015] any combination, including this channel & memory system, may be an apparatus comprised of a combination of the disclosed circuitry and would be an example of a memory device. Each Memory System 104- (a component of the claimed memory device) further containing memory devices such as 110-1 that may be DRAM (as well as a RAM, ROM, SDRAM, PCRAM, RRAM, and flash memory among others) and may include a memory array (see Hall [0023]). Akamatsu discloses a memory device that may be DRAM (SDRAM, flash memory, etc.) that may include one or more memory dies. Each memory die may include a local memory controller 165 and a memory array where the memory array may be one or more memory banks. Thus the solution of Hall that discloses a memory device 110-X with a memory die that contains a memory array in view of Akamatsu teaches a memory device with a memory die that contains a memory array that may be one or more memory banks controlled by the local memory controller 165 that is an example of a bank controller as it controls access to memory in a memory bank.
More explicitly, Hall teaches a Memory system 104-1, consisting of a plurality of Memory Devices 110-1 through 110-X. Each Memory Device of Hall contains one or more Memory Controller 114. See the diagram below for additional labeling of these components:
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The newly amended distinction that the memory is volatile is taught in Hall [0023] ‘Each memory device 110-a,…, 110-X, 110-Y and memory device 111-1,…,111-Z can include one or more arrays of memory cells, e.g., non-volatile memory cells…. The memory device can include .. DRAM).’ Thus the memory within Memory devices 110- and 111- are volatile memory.
Thus Hall teach a memory device (e.g. Memory System 104-1 for example) as claimed that comprises a channel (e.g. Channel 112-1) coupled with a set of volatile memory devices 110- and 111- of Hall.
However, Hall does not explicitly teach DRAM memory devices contain banks.
Akamatsu , Fig. 1 and column 4 lines 45-60 teaches a Memory Device may contain a plurality of Memory Die, and each memory die may contain a Local Memory Controller and a Memory Array 170-a and further teaches “a memory array 170 may be a collection (e.g., … one or more banks, thus the Memory Array shown in :
A subsection of Fig 1 of Akamatsu is included below for convenience:
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Thus the solution of Hall in view of Akamatsu may look as follows:
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Given each Memory Array 170-a through 170-N may consist of one or more memory banks, the solution of Hall in view of Akamatsu teaches a memory device (e.g. Memory System 104-1 combined with Channel 112-1 for example) that comprises a channel (e.g. Channel 112-1) coupled with a set of volatile memory devices which each contains a plurality of Memory Arrays 170-a to 170-N that in turn each contain one or more memory banks.
Thus Hall in view of Akamatsu teaches the claimed a memory that comprises a channel) coupled with a set of volatile memory banks as claimed.
Applicant further argues on page 8 of their remarks “Hall’s architecture uses separate devices connected via separate channels, not multiple banks within a single device sharing control channels.”
Examiner respectfully disagrees. The claimed Memory Device of Hall may be one of the Memory Systems (e.g. 104-1) and the associated channel (e.g. 112-1) associated with each Memory System. Each Memory Systems (104-1 to 104-N) contains multiple banks. For example Memory Device 104-1 contains Memory Devices 110-1 to 110-X each containing one or more multiple banks (given each memory device 110-1 contains one or more banks per Akamatsu). Thus the multiple banks in Memory System 104-1 share a single Channel 112-1.
Applicant further argues on page 8 of their remarks ‘Second, Hall does not teach or suggest "selecting the first volatile bank of the volatile memory device." Rather, Hall describes that " a first set of state machines can be used to execute commands on a first memory device ... a second set of state machines can be used to execute commands on a second memory device." Id., [0026]. Again, Hall is discussing selections of different memory devices and not selection of banks within a memory device. Therefore, the Office Action has not shown that Hall teaches or suggests "selecting the first volatile bank of the volatile memory device to perform the command based at least in part on receiving the command," as recited in amended independent claim 1 (emphasis added).
Examiner respectfully notes that Examiner cites Hall in view of Akamatsu to teaches a memory device comprises a channel coupled with a set of volatile banks. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
As detailed above when the system is selecting the first volatile device it is selecting a first volatile bank within the first volatile device and teaches or suggests "selecting the first volatile bank of the volatile memory device to perform the command based at least in part on receiving the command," as recited in amended independent claim 1. Hall Figs 1 & 2 and supporting paras [0009] and [0017]-[0025] (most notably [0020] that discloses a third address set to identify separate devices 110-1 to Y within the set of Y devices) discloses selecting a specific device based on an address range assigned to the device, where this selecting is performed within the Channel 112-1 and 104-1, that combined, are the claimed memory device. Additionally, examiner notes in the solution of Hall in view of Akamatsu the memory array may contain just one memory bank per array. There may be one array within each Memory Die, and there may be one memory die within each memory device 110. See Akamatsu col. 4, lines 45-60. Thus the solution of Hall in view of Akamatsu teaches selecting the first (and one and only) volatile bank of the volatile memory device 110-1 to perform the command based at least in part on receiving the command"
Applicant further argues on page 9 of their remarks ‘Third, Akamatsu does not cure the deficiencies of Hall. Akamatsu is generally directed to a delay calibration oscillator. See Akamatsu, Abstract. Akamatsu describes that "each memory die 160 may include local memory controller 165 ... and a memory array 170." Id., col. 4, 11. 47-51. For example, at a relevant portion, Akamatsu discusses that "memory array 170 may be a collection (e.g., one or more grids, one or more banks, one or more tiles, one or more sections) of memory cells." Id., col. 4, 11. 53-56. But the Office Action has not shown that Akamatsu teaches or suggests "selecting the first volatile bank of the volatile memory device to perform the command based at least in part on receiving the command," as recited in amended independent claim 1 (emphasis added).’… Akamatsu does not teach “selecting” described in the claims, especially at the bank level. Therefore, the Office action has not shown that Akamatsu teaches or suggests “selecting the first volatile bank of the volatile memory device to perform the command based at least in part on receiving the command” as recited in amended independent claim 1.
Examiner respectfully notes that Examiner cites Hall in view of Akamatsu to teaches a memory device comprises a channel coupled with a set of volatile banks. Hall teaches “selecting a first volatile device” based at least in part on receiving the command which includes an address to identify the target of the request and Akamatsu teaches that each volatile device may contain a memory array that contains one memory banks. As noted above, Hall Figs 1 & 2 and supporting paras [0009] and [0017]-[0025] (most notably [0020] that discloses a third address set to identify a single device within the set of devices), discloses a single memory device may be targeted per the address of the request. Akamatsu teaches that the device contains a memory bank. Additionally, examiner notes in the solution of Hall in view of Akamatsu the memory array may contain just one memory bank per array. There may be one array within each Memory Die, and there may be one memory die within each memory device 110. See Akamatsu col. 4, lines 45-60. Thus the solution of Hall in view of Akamatsu teaches selecting the first (and one and only) volatile bank of the volatile memory device 110-1 to perform the command based at least in part on receiving the command"
Examiner believes the above description of selecting a memory bank in the solution of Hall in view of Akamatsu is sufficient. Examiner believes the detail provided Akamatsu Fig. 1 Memory Device 110 and it’s channel description for channels 115 discloses an exemplary implementation option of Halls 104-1 and 112-1 components and corresponds to Fig.1 Memory Device 110 of the instant application.
Nevertheless, in response to applicant’s arguments, Examiner also notes the attached article “DDR4 Tutorial – Understanding the Basics” explains basic concepts that would be well known to POSITA, including Per the tutorial, page 2, line 14 through page 3 line 20, ‘DRAM memory is organized in Bank Groups and Banks, to access memory the requesting device will provide a logical address. This logical address will be converted to a physical address made of up the fields 1) Bank Group, 2) Bank, 3) Row, and 4) Column.’ Thus each and every request to a DRAM (as including the request by Hall) includes an address directed an access to an individual bank within a DRAM. This is a basic DRAM implementation concept. A POSITA would understand the selection signals of Hall are selecting a single bank in the solution of Hall in view of Akamatsu.
The applicant argues on page 9 of their remarks ‘the office Action has not demonstrated that none of the cited reference contemplated using these specific memory banks (e.g., volatile) to select and access.
Examiner respectfully notes, as detailed in the rejections and remarks above, when the solution of Hall in view of Akamatsu selects a Memory Device it is selecting a single volatile memory bank.
Applicant argues on pages 9 and 10 of their remarks ‘Fourth, the person having ordinary skill in the art would not combine Hall with Akamatsu to arrive at the features of amended independent claim 1. The Office Action asserts that "it would be obvious to one of ordinary skill in the art ... to incorporate the concept of a memory array including a plurality of memory banks for DRAM memory arrays." Office Action, p. 7. But the Office Action does not provide an explicit analysis to support such a conclusion. For example, the Office Action has not explained how the proposed modification of Hall would "support a plurality of memory banks typical of DRAM memory," as asserted. Id. Nor has the Office Action explained which features of Hall would be combined with Akamatsu to provide such a benefit. Rather, the Office Action merely refers to "one or more memory banks," a feature recited by independent claim 1, as allegedly supporting the conclusion. But rejections for obviousness cannot be sustained by mere conclusory statements; rather, the Office must articulate its reasoning with rational underpinnings to support the legal conclusion of obviousness. See MPEP 2141(111) (citing KSR Int'l, Co. v. Teleflex, Inc., 550 U.S. at 418, 82 USPQ2d at 396 (2007)).
Examiner respectfully disagrees. Applicant is misrepresenting the motivation to combine the art in the Office Action. Examiner notes on page 7 of the Office Action that the combination is using a known technique to improve similar devices (methods, or products) in the same way (such as supporting a plurality of banks within a memory array of a DRAM memory as taught by Akamatsu into the DRAM memory of Hall). One would be motivated to do so in order to support a plurality of memory banks typical of DRAM memory that enable concurrent DRAM access, thus reducing DRAM access latency. Thus the explicit feature of Hall incorporated is incorporating (one or more) memory banks within a memory device and the benefit would be to reduce DRAM latency. See page 49 of 18-447 Computer Architecture Lecture 21: Main Memory by Prof. Onur Mutlu included in the relevant art section that teaches the goal of DRAM memory banks enable bank interleaving that is directed to reducing the latency o memory array access and enable multiple accesses in parallel.
A person of ordinary skill in the art recognizes that memory banks are a component of a DRAM (See the attached article “DDR4 Tutorial – Understanding the Basics” which explains basic concepts that would be well known to POSITA. This article is directed toward basic principles for students studying computer architecture. The concepts would be well known to a person of ordinary skill in the art of general computer architecture and would be well understood by a person of ordinary skill in the art of memory computer architecture. Per the tutorial, page 2, line 14 through page 3 line 20, DRAM memory is organized in Bank Groups and Banks, to access memory the requesting device will provide a logical address. This logical address will be converted to a physical address made of up the fields 1) Bank Group, 2) Bank, 3) Row, and 4) Column. Thus a POSITA would recognize that each and every request to a DRAM (including the requests of Hall) is directing an access to an individual bank with DRAM and DRAMs contain one or more bank. The proposed modification would be made by implementing a plurality of banks within a memory device using well known DRAM architecture concepts.
Applicants arguments with respect to independent claims2-14 and 16-19 all rely upon perceived errors in independent claims 1 and 15 and have been addressed in the rejection and remarks relating to independent claims 1 and 15.
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is:
pages 70-76 of a presentation titled 18-447 Computer Architecture Lecture 21: Main Memory by Prof Onur Mutlu, with a publication date of 3/23/2015 that detail the structure of DRAM that is composed of Channels that contain chips (die) that contain a plurality of banks. See a screen shot of pages 70 and 76 below:
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(page 76)
The attached article “DDR4 Tutorial – Understanding the Basics” downloaded from www.systemverilog.io/design/ddr4-basics/ downloaded by arachive.org 3/19/2023. Per the tutorial, page 2, line 14 through page 3 line 20, DRAM memory is organized in Bank Groups and Banks, to access memory the requesting device will provide a logical address. This logical address will be converted to a physical address made of up the fields 1) Bank Group, 2) Bank, 3) Row, and 4) Column. Thus each and every request to a DRAM (as noted by Hall) is directing an access to an individual bank with DRAM and DRAMs contain one or more bank.
Conclusion
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/JANICE M. GIROUARD/Examiner, Art Unit 2138