DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/24/2026 has been entered.
Drawings
The drawings are objected to because drawing on page 2 and page 3, filed 03/15/2024, are both labeled as Fig. 2. Based on the Specification it appears drawing on page 3 should be labeled as Fig. 3. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Response to Arguments
Applicants’ arguments with respect to newly added claim limitations of “preceding clock cycle” and “a current clock cycle” have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 07/10/2026 with respect to newly added claim limitations have been fully considered but they are not persuasive.
Applicants argue (REMARKS, pg. 9) “Kenyon explicitly states that "the flip-flop 502 of FIG. 5 is an example of the data slicer 132," where Kenyon's flip-flop 502/data slicer 132 is the component that outputs a DFE output. Therefore, in the arrangement shown in Kenyon's FIG. 5, Kenyon's multiplexer 506 is not the component outputting a DFE output.”
The Office respectfully disagrees. Kenyon's FIG. 5 fairly suggest that the DFE 500 in which an output terminal “Y” of multiplexer 506 is clearly an output the DFE. In other words, terminal “Y” is the component outputting a DFE output. The claim language does not explicitly recite the outputs of multiplexers are the only direct outputs of the DFE. The Office asserts that if the claims were to be interpreted in such manner, the DFE 500 in Kenyon's FIG. 5 would simply require redefining the boundary of the DFE 500 to exclude the flip-flops 502 and/or 522 and still using the feedback selection signal as part of the DFE 500 which the courts have held “that the omission of an element and retention of its function is an indicium of nonobviousness” (See In re Edge, 359 F.2d 896, 149 USPQ 556 (CCPA 1966). Hence, the DFE 500 can be defined without the flip-flops 502 and/or 522.
Applicants further argue (REMARKS, pg. 12) “In Kenyon's FIG. 5, Kenyon's multiplexer 506 receives signals from flip-flops 508, 510, instead of directly from summation circuits. Therefore, Kenyon does not disclose or suggest "receive the first internal signal from the first summation circuit and the second internal signal from the second summation circuit" recited in claim 8.”
The Office respectfully disagrees. First the claims do not recite receiving “first internal signal” and “second internal signal” directly from summation circuits. Applicants disclosure does not support receiving “first internal signal” and “second internal signal” directly from summation circuits. Instead, applicants teach (e.g. Fig. 2 and 3) a multiplexer 205a receiving “first internal signal 110a+” and “second internal signal 110a-” from summation circuits via delay lines 203a, 203b and/or slicers 204a and 204b. Similar, Kenyon's FIG. 5 fairly suggests "receive the first internal signal from the first summation circuit (Fig. 5: first internal signal -output of first summation/selection block 512) and the second internal signal from the second summation circuit (Fig. 5: second internal signal-output of second summation/selection block 514)."
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 7-11 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kenyon (US 10305704 B1 previously cite, refer to text view version for citations) in view of Verkila et al. (US 10171270 B1 cited in PTO-892 mailed 04/24/2026).
Regarding Claim 1, Kenyon discloses;
An integrated circuit (Fig. 5: a decision feedback equalizer (DFE) circuit) comprising:
a first summation circuit (Fig. 5: selection block 512) configured to:
receive an analog signal (Fig. 5: 512 - selection block 512 receives analog signal V_IN); and
apply a positive offset to the analog signal to generate a first internal signal (Fig. 5, Para. [26], [33]: 512 - selection block 512 applies a positive offset, V_IN+αPD, to the analog signal V_IN) to generate a first internal signal, e.g., output of 512);
a second summation circuit (Fig. 5: 514 - selection block 514) configured to:
receive the analog signal (Fig. 5: selection block 514 receives the analog signal V_IN); and
apply a negative offset to the analog signal to generate a second internal signal (Fig. 5, Para. [28], [33]: selection block 514 each applies a negative offset, e.g., V_IN−αPD, to the analog signal V_IN) to generate a second internal signal, e.g. output of 514);
a first slicer (Fig. 5, Para. [22], [25], [33]: flip-flop 508) configured to sample the first internal signal to generate a first digital signal (Fig. 5, Para. [33]: “The flip-flop 508 is configured to sample a first possible data value [the first internal signal] (V_IN+αPD [the first internal signal], where PD is the previous V_DATA sample and +α is an equalization weight) provided by equalization selection block 512” and generates “the output sample (V_DATA) [first digital signal]”);
a second slicer (Fig. 5, Para. [22], [25], [33]: “the flip-flop 510 samples another possible data value (V_IN−αPD) provided by equalization selection block 514”) configured to sample the second internal signal to generate a second digital signal (Fig. 5, Para. [33]: “the flip-flop 510 samples another possible data value (V_IN−αPD) provided by equalization selection block 514” and generates “the output sample (V_DATA) [second digital signal]”); and
a multiplexer including input terminals (Fig. 5: multiplexer 506 includes input terminals “A” and “B”) coupled to the first slicer and the second slicer (Fig. 5: multiplexer 506 is coupled to the first slicer/DFF-flip-flop 508 and the second slicer/DFF-flip-flop 510), the multiplexer including an output terminal (Fig. 5: multiplexer 506 include output terminal “Y”) that is an output terminal of a decision feedback equalization (DFE) (Fig. 5, Para. [33]: “FIG. 5 shows a DFE circuit 500” where, as depicted, terminal “Y” is an output terminal of the DFE 500), and the multiplexer being configured to:
receive a selection signal (Fig. 5: the output sample (V_DATA) of the flip-flop 502 is received as a selection signal), wherein the selection signal is
select a specific signal between the first digital signal and the second digital signal (Para. [44]: “V_IN+αPD or V_IN−αPD is selected by multiplexer 506); and
output the selected specific signal at the output terminal of the DFE (Para. [34]: “if the sign of V_DATA (the output of flip-flop 502) is negative, the output of equalization selection block 512 and flip-flop 508 is selected by the multiplexer 506 as the input for flip-flop 502 (V_IN+αPD is selected when V_DATA is negative). Otherwise, if the sign of V_DATA is positive, the output of equalization selection block 514 and flip-flop 510 is selected by the multiplexer 506 as the input for flip-flop 502 (V_IN−αPD is selected when V_DATA is positive)”. That is, a specific V_IN+αPD or V_IN−αPD is selected as an output, based on the polarity of the selection signal fed into the “data feedback path 504 to control multiplexer 506”) as a digital signal…that represents a decoded bit value of the analog signal (Fig. 2, Para. [18]-[20]: the selected specific V_IN+αPD or V_IN−αPD signal is output as “a high-bit value (a logical “one”)” digital signal or “low-bit values (a logical “zero”)” digital signal that represents a decoded bit value of the analog RX SIGNAL 212).
Kenyon does not specifically teach the selection/V_DATA signal is a previous digital signal outputted by the multiplexer is:
“in a preceding clock cycle”; and the specific signal V_IN+αPD or V_IN−αPD is selected as the digital signal:
“in a current clock cycle.”
On the other hand, in the same field of endeavor (Abstract: “correcting pre-cursor intersymbol interference (ISI) and post-cursor ISI in a data signal received over a channel…using decision feedback equalization (DFE)”), Verkila et al. teaches;
a selection signal is a previous digital signal outputted by the multiplexer is:
“in a preceding clock cycle”(Fig. 3, Fig. 3, col. 2, line 49-54, col. 9, line 7-18: the selection signal, at terminal S1 of Multiplexer 318, is a previous digital signal d[n-3] outputted by the multiplexer 318 is in a preceding clock cycle/time interval, n-3); and the specific signal outputted by a multiplexer is selected as the digital signal:
“in a current clock cycle (Fig. 3, Fig. 3, col. 2, line 49-54, col. 9, line 7-18: “The multiplexer 318 receives the plurality of data bits (from the plurality of digital flip-flops 316) in parallel and selects one of the plurality of data bits as its output, where the output represents a data bit d[n−2] (322) retrieved from the input data signal 302” where the data bit d[n−2] is in a current clock cycle/time interval, n-2).”
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the selection/V_DATA signal and the specific signal V_IN+αPD or V_IN−αPD in Kenyon’s invention can be implemented in a preceding clock cycle and in a current clock cycle, respectively, as taught by Verkila et al. where doing so would (Verkila et al., col. 2, line 17-19) “provide for correcting pre-cursor intersymbol interference (ISI) and post-cursor ISI in an analog data signal.”
Regarding Claim 2, Kenyon in view of Verkila et al. discloses all as applied to claims 1 above, where Kenyon further teaches;
wherein the analog signal is a single ended signal (Fig. 5: input analog signal, V_IN, is a single ended signal).
Regarding Claim 3, Kenyon in view of Verkila et al. discloses all as applied to claims 1 above, where Kenyon further teaches;
wherein the analog signal is a differential signal (Fig. 10: analog input signal is a differential signal, i.e. +IN_1 and -IN_1).
Regarding Claim 4, Kenyon in view of Verkila et al. discloses all as applied to claims 1 above, where Kenyon further teaches;
wherein:
the first summation circuit is configured to apply the positive offset to the analog signal by adding a predefined offset to the analog signal (Fig. 5, Para. [0033]: equalization selection block 512 applies a predefined positive, i.e. “+α”, equalization weight”/offset to the analog V_IN signal); and
the second summation circuit is configured to apply the negative offset to the analog signal by subtracting the predefined offset from the analog signal (Fig. 5, Para. [0033]: equalization selection block 514 applies a predefined negative, i.e. “-α”, equalization weight”/offset to the analog V_IN signal).
Regarding Claim 7, Kenyon in view of Verkila et al. discloses all as applied to claims 1 above, where Kenyon further teaches;
wherein:
a first slicer is configured to sample the first internal signal according to a strobe signal (Fig. 10; Para. [46]: first slicer/flip-flop 508 uses CLK1, generated according to an REF CLK_IN/strobe signal, to sample the first internal signal) and
a second slicer configured to sample the second internal signal according to the strobe signal (Fig. 10; Para. [46]: second slicer/flip-flop 510 uses the CLK1, generated according to the REF CLK_IN/strobe signal, to sample the second internal signal).
Regarding Claim 8, Kenyon discloses;
An integrated circuit (Fig. 5: a decision feedback equalizer (DFE) circuit) comprising:
a first summation circuit (Fig. 5: 512 - selection block 512) configured to:
receive an analog signal (Fig. 5: 512 - selection block 512 receives analog signal V_IN); and
apply a positive offset to the analog signal to generate a first internal signal (Fig. 5, Para. [26], [33]: 512 - selection block 512 each applies a positive offset, e.g. V_IN+αPD, to the analog signal V_IN) to generate a first internal signal, e.g. output of 512);
a second summation circuit (Fig. 5: 514 - selection block 514) configured to:
receive the analog signal (Fig. 5: 512 - selection block 514 receives the analog signal V_IN); and
apply a negative offset to the analog signal to generate a second internal signal (Fig. 5, Para. [28], [33]: selection block 514 each applies a negative offset, e.g. V_IN−αPD, to the analog signal V_IN) to generate a first internal signal, e.g. output of 514);
a multiplexer (Fig. 5: multiplexer 506) configured to:
receive the first internal signal from the first summation circuit (Fig. 5, Para. [33]: “The flip-flop 508 [receive] is configured to sample a first possible data value (V_IN+αPD [first internal signal], where PD is the previous V_DATA sample and +α is an equalization weight) provided by equalization selection block 512”) and the second internal signal from the second summation circuit (Fig. 5, Para. [33]: “the flip-flop 510 [receives and] samples another possible data value (V_IN−αPD) [second internal signal] provided by equalization selection block 514”):
receive a selection signal (Fig. 5: the output sample (V_DATA) of the flip-flop 502), wherein the selection signal is
select one of the first internal signal and the second internal signal (Fig. 5, Para. [44]: “V_IN+αPD [input A] or V_IN−αPD [input B] is selected by multiplexer 506”); and
output the selected one of the first internal signal and the second internal signal as a third internal signal (Para. [34], [44]: either V_IN+αPD [input A] or V_IN−αPD [input B] is selected by multiplexer 506 and output as a third internal signal); and
a slicer (Fig. 5: the flip-flop 502) configured to sample the third internal signal (Fig. 5: flip-flop 502 samples output [either V_IN+αPD [input A] or V_IN−αPD [input B]] of multiplexer 506) to generate a digital signal that represents a decoded bit value of the analog signal (Fig. 2, Para. [18]-[20]: from the third signal/either V_IN+αPD [input A] or V_IN−αPD [input B]] a digital/V_DATA signal is generated as “a high-bit value (a logical “one”)” digital signal or “ low-bit values (a logical “zero”)”… that represents a decoded bit value of the analog RX SIGNAL 212).
Kenyon does not specifically teach the selection/V_DATA signal is a previous digital signal outputted by the multiplexer is:
“in a preceding clock cycle”; and the specific signal V_IN+αPD or V_IN−αPD is selected as the digital signal:
“in a current clock cycle.”
On the other hand, in the same field of endeavor (Abstract: “correcting pre-cursor intersymbol interference (ISI) and post-cursor ISI in a data signal received over a channel…using decision feedback equalization (DFE)”) Verkila et al. teaches;
a selection signal is a previous digital signal outputted by the multiplexer is:
“in a preceding clock cycle”(Fig. 3, Fig. 3, col. 2, line 49-54, col. 9, line 7-18: the selection signal, at terminal S1 of Multiplexer 318, is a previous digital signal d[n-3] outputted by the multiplexer 318 is in a preceding clock cycle/time interval, n-3); and the specific signal outputted by a multiplexer is selected as the digital signal:
“in a current clock cycle (Fig. 3, Fig. 3, col. 2, line 49-54, col. 9, line 7-18: “The multiplexer 318 receives the plurality of data bits (from the plurality of digital flip-flops 316) in parallel and selects one of the plurality of data bits as its output, where the output represents a data bit d[n−2] (322) retrieved from the input data signal 302” where the data bit d[n−2] is in a current clock cycle/time interval, n-2).”
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the selection/V_DATA signal and the specific signal V_IN+αPD or V_IN−αPD in Kenyon’s invention can be implemented in a preceding clock cycle and in a current clock cycle, respectively, as taught by Verkila et al. where doing so would (Verkila et al., col. 2, line 17-19) “provide for correcting pre-cursor intersymbol interference (ISI) and post-cursor ISI in an analog data signal.”
Regarding Claim 9, Kenyon in view of Verkila et al. discloses all as applied to claim 8 above, where Kenyon further teaches;
wherein the analog signal is a single ended signal (Fig. 5: input analog signal, V_IN, is a single ended signal).
Regarding Claim 10, Kenyon in view of Verkila et al. discloses all as applied to claim 8 above, where Kenyon further teaches;
wherein the analog signal is a differential signal (Fig. 10: analog input signal is a differential signal, i.e. +IN_1 and -IN_1).
Regarding Claim 11, Kenyon in view of Verkila et al. discloses all as applied to claim 8 above, where Kenyon further teaches;
wherein:
the first summation circuit is configured to apply the positive offset to the analog signal by adding a predefined offset to the analog signal (Fig. 5, Para. [0033]: equalization selection block 512 applies a predefined positive, i.e. “+α”, equalization weight”/offset to the analog V_IN signal); and
the second summation circuit is configured to apply the negative offset to the analog signal by subtracting the predefined offset from the analog signal (Fig. 5, Para. [0033]: equalization selection block 514 applies a predefined negative, i.e. “-α”, equalization weight”/offset to the analog V_IN signal).
Regarding Claim 14, Kenyon in view of Verkila et al. discloses all as applied to claim 8 above, where Kenyon further teaches;
wherein the slicer is configured to sample the third internal signal according to a strobe signal (Fig. 10; Para. [46]: slicer/flip-flop 502 uses CLK1 generated according to an REF CLK_IN/strobe signal to sample the third internal signal).
Regarding Claim 15, Kenyon discloses;
A system (Fig. 1: “a system with a decision feedback equalizer (DFE) circuit”) comprising:
a controller (Fig. 1: a clock recovery circuit 116) configured to generate a strobe signal (Fig. 1, 10, Para. [21]: clock recovery circuit 116 generates a CLK_1/strobe signal from the output of the VCO 124”);
a transmitter (Fig. 1: transmitter 104) configured to output an analog signal (Fig. 2: outputs transmitter-side analog/TX signal 202); and
a receiver (Fig. 1: receiver 110) comprising a decision feedback equalization (DFE) (Fig. 5, Para. [33]: “FIG. 5 shows a DFE circuit 500”) configured to:
receive the analog signal from the transmitter through a channel (Fig. 1: receiver 110 receives transmitter-side analog/TX signal 202 through a channel 106);
apply a positive offset to the analog signal to generate a first internal signal (Fig. 5, Para. [26], [33]: 512 - selection block 512 each applies a positive offset, e.g. V_IN+αPD, to the analog signal V_IN) to generate a first internal signal, e.g. output of 512);
apply a negative offset to the analog signal to generate a second internal signal (Fig. 5, Para. [28], [33]: 514 - selection block 514 each applies a negative offset, e.g. V_IN−αPD, to the analog signal V_IN) to generate a first internal signal, e.g. output of 514);
sample at least one of the first internal signal and the second internal signal according to the strobe signal (Fig. 5, Para. [33]: “The flip-flop 508 is configured to sample a first possible data value [the first internal signal] (V_IN+αPD [the first internal signal], where PD is the previous V_DATA sample and +α is an equalization weight) provided by equalization selection block 512” and generates “the output sample (V_DATA) [first digital signal]”)] and “the flip-flop 510 samples another possible data value (V_IN−αPD) provided by equalization selection block 514”and generates “the output sample (V_DATA) [second digital signal]”);
use a previous digital signal outputted by the DFE … as a selection signal (Fig. 5, Para. [33]: “a flip-flop 502 that samples based on CLK1, where the output sample (V_DATA) of the flip-flop 502 is fed (previous digital signal outputted by the DFE 500) into a data feedback path 504 to control [as a selection signal] multiplexer 506”) to select a specific signal from the first internal signal and the second internal signal that decodes the analog signal (Fig. 5, Para. [34]: “V_IN+αPD”- first internal signal/output of 512 or “V_IN−αPD”- second internal signal/output of 514 is selected by multiplexer 506” as a specific signal that decodes the analog RX SIGNAL 212); and
based on the sample and the selection, generate a digital signal … that represents a decoded bit value of the analog signal (Fig. 2, Para. [18]-[20]: the sampled and selected specific V_DATA signal is output as “a high-bit value (a logical “one”)” digital signal or “low-bit values (a logical “zero”)” digital signal that represents a decoded bit value of the analog RX SIGNAL 212).
Kenyon does not specifically teach the selection/V_DATA signal is a previous digital signal outputted by the DFE 500 is:
“in a preceding clock cycle”; and the specific signal V_IN+αPD or V_IN−αPD is selected as the digital signal:
“in a current clock cycle.”
On the other hand, in the same field of endeavor (Abstract: “correcting pre-cursor intersymbol interference (ISI) and post-cursor ISI in a data signal received over a channel…using decision feedback equalization (DFE)”) Verkila et al. teaches;
a selection signal is a previous digital signal outputted by the multiplexer is:
“in a preceding clock cycle”(Fig. 3, Fig. 3, col. 2, line 49-54, col. 9, line 7-18: the selection signal, at terminal S1 of Multiplexer 318, is a previous digital signal d[n-3] outputted by the multiplexer 318 is in a preceding clock cycle/time interval, n-3); and the specific signal outputted by a multiplexer is selected as the digital signal:
“in a current clock cycle (Fig. 3, Fig. 3, col. 2, line 49-54, col. 9, line 7-18: “The multiplexer 318 receives the plurality of data bits (from the plurality of digital flip-flops 316) in parallel and selects one of the plurality of data bits as its output, where the output represents a data bit d[n−2] (322) retrieved from the input data signal 302” where the data bit d[n−2] is in a current clock cycle/time interval, n-2).”
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the selection/V_DATA signal and the specific signal V_IN+αPD or V_IN−αPD in Kenyon’s invention can be implemented in a preceding clock cycle and in a current clock cycle, respectively, as taught by Verkila et al. where doing so would (Verkila et al., col. 2, line 17-19) “provide for correcting pre-cursor intersymbol interference (ISI) and post-cursor ISI in an analog data signal.”
Regarding Claim 16, Kenyon in view of Verkila et al. discloses all as applied to claim 15 above, where Kenyon further teaches;
wherein the receiver comprises:
a first slicer (Fig. 5, Para. [22], [25], [33]: flip-flop 508) configured to sample the first internal signal to generate a first digital signal (Fig. 5, Para. [33]: “The flip-flop 508 is configured to sample a first possible data value [the first internal signal] (V_IN+αPD [the first internal signal], where PD is the previous V_DATA sample and +α is an equalization weight) provided by equalization selection block 512” and generates “the output sample (V_DATA) [first digital signal]”);
a second slicer (Fig. 5, Para. [22], [25], [33]: “the flip-flop 510 samples another possible data value (V_IN−αPD) provided by equalization selection block 514”) configured to sample the second internal signal to generate a second digital signal (Fig. 5, Para. [33]: “the flip-flop 510 samples another possible data value (V_IN−αPD) provided by equalization selection block 514” and generates “the output sample (V_DATA) [second digital signal]”); and
a multiplexer (Fig. 5: multiplexer 506) configured to:
receive the previous digital signal as the selection signal (Fig. 2, 5, Para. [33]: “a flip-flop 502 that samples based on CLK1, where the output sample (V_DATA) of the flip-flop 502 is fed (previous digital signal) into a data feedback path 504 to control [as a selection signal] multiplexer 506”), wherein the previous digital signal is outputted by the multiplexer (Fig. 2, 5, Para. [33]: where the output sample (V_DATA) of the flip-flop 502 is fed (previous digital signal) into a data feedback path 504 to control multiplexer 506”));
select one of the first digital signal and the second digital signal as the specific signal (Fig. 5, Para. [44]: “V_IN+αPD or V_IN−αPD is selected by multiplexer 506); and
output the selected specific signal (Para. [34]: “if the sign of V_DATA (the output of flip-flop 502) is negative, the output of equalization selection block 512 and flip-flop 508 is selected by the multiplexer 506 as the input for flip-flop 502 (V_IN+αPD is selected when V_DATA is negative). Otherwise, if the sign of V_DATA is positive, the output of equalization selection block 514 and flip-flop 510 is selected by the multiplexer 506 as the input for flip-flop 502 (V_IN−αPD is selected when V_DATA is positive)”. That is, a specific V_DATA signal is selected as an output) as a digital signal that represents a decoded bit value of the analog signal (Fig. 2, Para. [18]-[20]: the selected specific V_DATA signal is output as “a high-bit value (a logical “one”)” digital signal or “low-bit values (a logical “zero”)” digital signal that digital signal that represents a decoded bit value of the analog RX SIGNAL 212).
Regarding Claim 17, Kenyon in view of Verkila et al. discloses all as applied to claim 15 above, where Kenyon further teaches;
wherein the receiver comprises:
a multiplexer (Fig. 5: multiplexer 506) configured to:
receive the previous digital signal as the selection signal (Fig. 2, 5, Para. [0033]: “a flip-flop 502 that samples based on CLK1, where the output sample (V_DATA) of the flip-flop 502 is fed (previous digital signal) into a data feedback path 504 to control [as a selection signal] multiplexer 506”), wherein the previous digital signal is outputted by the multiplexer (Fig. 2, 5, Para. [33]: where the output sample (V_DATA) of the flip-flop 502 is fed (previous digital signal) into a data feedback path 504 to control multiplexer 506”));
select one of the first digital signal and the second digital signal as the specific signal (Fig. 5, Para. [44]: “V_IN+αPD or V_IN−αPD is selected by multiplexer 506); and
a slicer (Fig. 5: the flip-flop 502) configured to sample the selected specific signal (Fig. 5: flip-flop 502 samples output [the selected specific signal/either V_IN+αPD [input A] or V_IN−αPD [input B]] of multiplexer 506) to generate a digital signal that represents a decoded bit value of the analog signal (Fig. 2, Para. [18]-[20]: from the selected specific signal/either V_IN+αPD [input A] or V_IN−αPD [input B]] a digital/V_DATA signal is generated as “a high-bit value (a logical “one”)” digital signal or “ low-bit values (a logical “zero”)” that represents a decoded bit value of the analog RX SIGNAL 212).
Regarding Claim 18, Kenyon in view of Verkila et al. discloses all as applied to claim 15 above, where Kenyon further teaches;
wherein the analog signal is a single ended signal (Fig. 5: input analog signal, V_IN, is a single ended signal).
Regarding Claim 19, Kenyon in view of Verkila et al. discloses all as applied to claim 15 above, where Kenyon further teaches;
wherein the analog signal is a differential signal (Fig. 10: analog input signal is a differential signal, i.e. +IN_1 and -IN_1).
Claims 5, 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kenyon (US 10305704 B1 previously cite, refer to text version for citations) in view of Verkila et al. (US 10171270 B1 cited in PTO-892 mailed 04/24/2026) further in view of Kimura et al. (NPL titled: “28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS,” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 2014, pp. 38-39, previously cited).
Regarding Claim 5 and 12, Kenyon in view of Verkila et al. discloses all as applied to claims 1 and 8 further teaching (Para. [3]) “In DFE, a delay element is introduced into the receiver circuitry and equalization values are combined with an input data stream,” however Kenyon does not teach;
a first delay line configured to apply a first delay to the first internal signal;
a second delay line configured to apply the first delay to the second internal signal; and
a third delay line configured to apply a second delay to a strobe signal being used by the first slicer to sample the first internal signal and by the second slicer to sample the second internal signal.
On the other hand, in the same field of endeavor (Fig. 2.1.1, First paragraph: “decision-feedback equalizer (DFE)”) Kimura et al. teaches;
a first delay line (See below -Modified Fig. 2.1.1: 1st Delay Line or Buffer) configured to apply a first delay to the first internal signal (See below - Modified Fig. 2.1.1: 1st Delay Line or Buffer applies a signal stage delay to first input/internal signal to first slicer);
a second delay line (See below -Modified Fig. 2.1.1: 2nd Delay Line or Buffer) configured to apply the first delay to the second internal signal (See below - Modified Fig. 2.1.1: 2nd Delay Line or Buffer applies the signal stage delay to second input/internal signal to second slicer); and
a third delay line (See below -Modified Fig. 2.1.1: 3rd Delay Line or Buffer) configured to apply a second delay to a strobe signal (See below - Modified Fig. 2.1.1: 3rd Delay Lines or Buffers applies a second delay to a strobe/clock signal, e.g. CK1) being used by the first slicer to sample the first internal signal (See below - Modified Fig. 2.1.1, Fig. 2.1.4: strobe/clock signal, e.g. CK1 is used by a first slicer to sample the first input/internal signal ) and by the second slicer to sample the second internal signal (See below - Modified Fig. 2.1.1, Fig. 2.1.4: strobe/clock signal, e.g. CK1 is used by a second slicer to sample the second input/internal signal).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the delay element in the DFE in Kenyon in view of Verkila et al.’s invention may include a first, a second and a third delay lines configured as taught by Kimura et al. where doing so would (by Kimura et al., first and second paragraph) provide “capability to control output common-mode voltage to optimize circuit operating points” and “to maintain clock quality”
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Modified Fig. 2.1.1
Regarding Claim 20, Kenyon in view of Verkila et al. discloses all as applied to claim 15, further teaching (Para. [3]) “In DFE, a delay element is introduced into the receiver circuitry and equalization values are combined with an input data stream,” however Kenyon does not teach;
apply a first delay to the first internal signal;
apply the first delay to the second internal signal; and
apply a second delay to the strobe signal to align the strobe signal with at least one of the first internal signal and the second internal signal being sampled.
On the other hand, in the same field of endeavor (Fig. 2.1.1, First paragraph: “decision-feedback equalizer (DFE)”) Kimura et al. teaches;
apply a first delay to the first internal signal (See below - Modified Fig. 2.1.1: 1st Delay Line or Buffer applies a signal stage delay to first input/internal signal to first slicer);
apply the first delay to the second internal signal (See below - Modified Fig. 2.1.1: 2nd Delay Line or Buffer applies the signal stage delay to second input/internal signal to second slicer); and
apply a second delay to the strobe signal to align the strobe signal with at least one of the first internal signal and the second internal signal being sampled.
apply a second delay to the strobe signal (See below - Modified Fig. 2.1.1: 3rd Delay Lines or Buffers applies a second delay (two stage delay/buffer e.g., 2nd paragraph: “There are several buffer stages before and after the PI to maintain clock quality”) to the strobe/clock signal, e.g. CK1) to align the strobe signal with at least one of the first internal signal and the second internal signal being sampled (See below - Modified Fig. 2.1.1, Fig. 2.1.4: strobe/clock signal, e.g. CK1 is used by a first slicer and second slicer to align the strobe/CK1 signal with the first input/internal signal being sampled and the second input/internal signal being sampled).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the delay element in the DFE in Kenyon in view of Verkila et al.’s invention may include a first, a second and a third delay lines configured as taught by Kimura et al. where doing so would (Kimura et al., first and second paragraph) provide “capability to control output common-mode voltage to optimize circuit operating points” and “to maintain clock quality”
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Modified Fig. 2.1.1
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kenyon (US 10305704 B1 previously cite, refer to text version for citations) in view of Verkila et al. (US 10171270 B1 cited in PTO-892 mailed 04/24/2026) in view of Hollis (US 20220329464 A1 previously cited).
Regarding Claim 6 and 13, Kenyon in view of Verkila et al. discloses all as applied to claims 1 and 8 above, further teaching (Fig. 5, Para. [34]) the multiplexer 506 is configured to: in response to the previous digital signal (V_DATA) being negative (i.e. low voltage), the first digital/V_IN+αPD signal is selected and in response to the previous digital signal (V_DATA) being positive (i.e. high voltage), the second digital/V_IN-αPD signal is selected rather than:
in response to the previous digital signal indicating a high voltage, select the first digital signal and
in response to the previous digital signal indicating a low voltage, select the second digital signal.
On the other hand, in the same field of endeavor (Abstract, Fig. 2: “a control signal to select a mode of decision feedback equalization to be applied to an input data bit”) Hollis teaches ( Para. [0044]-[0045]) “the voltage of the input bit is recognized to be greater than the reference voltage VrefHi, a result signal corresponding to a logical high signal (e.g., “1”)” and “when the voltage of the input bit is recognized to be less than the reference voltage VrefLo, a result signal corresponding to a logical low signal (e.g., “0”)” and that (Fig. 2) multiplexer 58 is configured to;
in response to the previous digital signal digital indicating a high voltage, select the first digital signal (Fig. 2, Para. [0046]: “when the signal received at the control input 82 [the previous digital] corresponds to a logical high signal [i.e. having high voltage], the result signal received at input 78 [first digital signal] is transmitted from the output 84 of the selection circuit 58 as the selected signal to an input 86 of the latch 60”) and
in response to the previous digital signal indicating a low voltage, select the second digital signal (Fig. 2, Para. [0046]: “when the signal received at the control input 82 [the previous digital] corresponds to a logical low signal [i.e. having low voltage], the result signal received at input 80 is transmitted as a selected signal from the output 84 of the selection circuit 58 to an input 86 of the latch 60”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the multiplexer 506 can be controlled to output the first digital/V_IN+αPD signal and the second digital/V_IN-αPD in Kenyon in view of Verkila et al.’s invention when the previous digital/V_DATA signal indicate a high voltage and low voltage, respectively as taught by Hollis where doing so would (Hollis., Para. [0002]) “offset (i.e., undo, mitigate) the effect of the channel on the transmitted data”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
KIM et al. (US 20090175328 A1) discloses (Fig. 2, 6-8, Para. [0051], [0064], [0081], [0092]) “the DFE unit 100…the data 1 having a high level selects any one of outputs of the first and second samplers 112 and 114 in response to an output DI-S of the second MUX 124 as previous data input just before. In this case, when the previous data DI-S has a high level, an output of the second sampler 114 is selected, and when the previous data DI-S has a low level, an output of the first sampler 112 is selected. Then, an output DI-F of the first MUX 122 becomes a high level.” “The DFE unit 200 samples and outputs transmission data according to sampling reference level that is configured to change responsive to a level of previous data (i.e., that is previously input).” “the DFE unit 300 comprises a sampling block 310 and a selection block 350.” “the DFE unit 400 comprises a sampling block 410, a selection block 410 and a delay block 460.”
Hekmat et al. (US 20150349984 A1) discloses (Fig. 5A, 6A, Apra. [0048], [0051]) “a predictive DFE circuit" with output of multiplexer “Mux”/“MuxL” as the output of the “predictive DFE circuit.”
WU et al. (US 20210218604 A1) discloses (Fig. 4, Para. [0034]-[0036]) “an example DFE 400” that includes a number N of parallel paths 410 that is different from four parallel paths, and the DFE operates at a clock rate that is a fraction 1/N of the symbol rate. The parallel paths 410 include a first path 410a configured to process a sample x.sub.0 of the input signal, a second path 410b configured to process a sample x.sub.1, a third path 410c configured to process a sample x.sub.3 of the input signal, and a fourth path 410d configured to process a sample x.sub.4 of the input signal, in the illustrated embodiment. Each of the paths 410 includes a respective feedback filter 411, a respective set of slicers 416, and a respective multiplexer 418” where an output of multiplexer 418 is an output of the DFE output.
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/AMNEET SINGH/Examiner, Art Unit 2633 /SAM K AHN/Supervisory Patent Examiner, Art Unit 2633
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