DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see REMARKS, filed 01/02/2026, with respect to 35 U.S.C 112(b) rejection of claim 7 have been fully considered and are persuasive in view of the filed amendments. The rejection of claim 735 under U.S.C 112(b) has been withdrawn.
Applicant's arguments filed 01/02/2026, with respect to rejection of claims 1-20 under 35 U.S.C 102(a)(1) and/or 35 U.S.C. 103 have been fully considered but they are not persuasive.
Applicant argue, REMAKS page12, the “Thus, if flip- flops 502 and 522 are the slicers (as Kenyon explicitly states), there is no structure in Kenyon in which a multiplexer receives two digital slicer outputs and selects between them, as claim 1 requires.”
The Office respectfully disagrees. Kenyon explicitly teaches, at least in embodiment of figure 5 (as previously cited), digital flip flops (labeled as DFF) 508 and 510 performing the functions as slicers (digital flip flops 508 and 510 having same structure/configuration as digital flip- flops (DFF) 502 and 522 slicers, thus having same functionality as a slicer), provides two digital slicer outputs, i.e. digital outputs of 508 and 510 to a multiplexer 506 that makes a selection therebetween.
Applicant argue, REMAKS page15, “In contrast, claim 8 requires that the first and second internal signals be generated by the summation circuits, and that the multiplexer select between those two internal signals. Kenyon does not disclose a multiplexer selecting between the outputs of summation circuits 304 and 314.”
The Office respectfully disagrees. Kenyon explicitly teaches, at least in embodiment of figure 5 (as previously cited), that the first and second internal signals, i.e. outputs of 512 and 514 are generated by the summation circuits 512 and 514 (see previously cited Para. [33]: blocks 512 and 514 preforms summation as “V_IN+αPD” and “V_IN−αPD”), respectively, where the multiplexer 506 select between those two internal signals.
Generally, applicant appears to present arguments based on combining features from different embodiments, e.g. Fig. 1, 3, 5, of the cited prior art, where the claims were rejected under is 35 U.S.C. 102(a)(1) as being anticipated by Kenyon (US 10305704 B1). That is, the Office cited each embodiment, i.e. Fig. 1, 3 and 5, of Kenyon as each teaching the recited claim limitations and not in combination (hence a 102(a)(1) rejection). The Office asserts that at least embodiment of Fig. 5 teaches each of the recited limitations as previously presented. For clarity, the Office presents the previous rejection only in view of embodiment of Fig. 5 of Kenyon.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-11 and 14-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kenyon (US 10305704 B1 previously cited).
Regarding Claim 1, Kenyon discloses;
An integrated circuit (Fig. 5: a decision feedback equalizer (DFE) circuit) comprising:
a first summation circuit (Fig. 5: 512 - selection block 512) configured to:
receive an analog signal (Fig. 5: 512 - selection block 512 receives analog signal V_IN); and
apply a positive offset to the analog signal to generate a first internal signal (Fig. 5, Para. [26], [33]: 512 - selection block 512 applies a positive offset, V_IN+αPD, to the analog signal V_IN) to generate a first internal signal, e.g., output of 512);
a second summation circuit (Fig. 5: 514 - selection block 514) configured to:
receive the analog signal (Fig. 5: 514 - selection block 514 receives the analog signal V_IN); and
apply a negative offset to the analog signal to generate a second internal signal (Fig. 5, Para. [28], [33]: 512 - selection block 514 each applies a negative offset, e.g., V_IN−αPD, to the analog signal V_IN) to generate a second internal signal, e.g. output of 514);
a first slicer (Fig. 5, Para. [22], [25], [33]: flip-flop 508) configured to sample the first internal signal to generate a first digital signal (Fig. 5, Para. [33]: “The flip-flop 508 is configured to sample a first possible data value [the first internal signal] (V_IN+αPD [the first internal signal], where PD is the previous V_DATA sample and +α is an equalization weight) provided by equalization selection block 512” and generates “the output sample (V_DATA) [first digital signal]”);
a second slicer (Fig. 5, Para. [22], [25], [33]: “the flip-flop 510 samples another possible data value (V_IN−αPD) provided by equalization selection block 514”) configured to sample the second internal signal to generate a second digital signal (Fig. 5, Para. [33]: “the flip-flop 510 samples another possible data value (V_IN−αPD) provided by equalization selection block 514” and generates “the output sample (V_DATA) [second digital signal]”); and
a multiplexer (Fig. 5: multiplexer 506) coupled to the first slicer and the second slicer (Fig. 5: multiplexer 506 is coupled to the first slicer/DFF-flip-flop 508 and the second slicer/DFF-flip-flop 510), the multiplexer being configured to:
receive a selection signal (Fig. 5: the output sample (V_DATA) of the flip-flop 502), wherein the selection signal is a feedback of a previous digital signal outputted by the multiplexer (Fig. 5, Para. [33]: “a flip-flop 502 that samples based on CLK1, where the output sample (V_DATA) of the flip-flop 502 is fed into a data feedback path 504 to control multiplexer 506”);
select a specific signal between the first digital signal and the second digital signal (Para. [44]: “V_IN+αPD or V_IN−αPD is selected by multiplexer 506); and
output the selected specific signal (Para. [34]: “if the sign of V_DATA (the output of flip-flop 502) is negative, the output of equalization selection block 512 and flip-flop 508 is selected by the multiplexer 506 as the input for flip-flop 502 (V_IN+αPD is selected when V_DATA is negative). Otherwise, if the sign of V_DATA is positive, the output of equalization selection block 514 and flip-flop 510 is selected by the multiplexer 506 as the input for flip-flop 502 (V_IN−αPD is selected when V_DATA is positive)”. That is, a specific V_DATA signal is selected as an output) as a digital signal that represents a decoded bit value of the analog signal (Fig. 2, Para. [18]-[20]: the selected specific V_DATA signal is output as “a high-bit value (a logical “one”)” digital signal or “ low-bit values (a logical “zero”)” digital signal that represents a decoded bit value of the analog RX SIGNAL 212).
Regarding Claim 2, Kenyon discloses;
wherein the analog signal is a single ended signal (Fig. 5: input analog signal, V_IN, is a single ended signal).
Regarding Claim 3, Kenyon discloses;
wherein the analog signal is a differential signal (Fig. 10: analog input signal is a differential signal, i.e. +IN_1 and -IN_1).
Regarding Claim 4, Kenyon discloses;
wherein:
the first summation circuit is configured to apply the positive offset to the analog signal by adding a predefined offset to the analog signal (Fig. 5, Para. [0033]: equalization selection block 512 applies a predefined positive, i.e. “+α”, equalization weight”/offset to the analog V_IN signal); and
the second summation circuit is configured to apply the negative offset to the analog signal by subtracting the predefined offset from the analog signal (Fig. 5, Para. [0033]: equalization selection block 514 applies a predefined negative, i.e. “-α”, equalization weight”/offset to the analog V_IN signal).
Regarding Claim 7, Kenyon discloses;
wherein:
a first slicer is configured to sample the first internal signal according to a strobe signal (Fig. 10; Para. [46]: first slicer/flip-flop 508 uses CLK1, generated according to an REF CLK_IN/strobe signal, to sample the first internal signal) and
a second slicer configured to sample the second internal signal according to the strobe signal (Fig. 10; Para. [46]: second slicer/flip-flop 510 uses the CLK1, generated according to the REF CLK_IN/strobe signal, to sample the second internal signal).
Regarding Claim 8, Kenyon discloses;
An integrated circuit (Fig. 5: a decision feedback equalizer (DFE) circuit) comprising:
a first summation circuit (Fig. 5: 512 - selection block 512) configured to:
receive an analog signal (Fig. 5: 512 - selection block 512 receives analog signal V_IN); and
apply a positive offset to the analog signal to generate a first internal signal (Fig. 5, Para. [26], [33]: 512 - selection block 512 each applies a positive offset, e.g. V_IN+αPD, to the analog signal V_IN) to generate a first internal signal, e.g. output of 512);
a second summation circuit (Fig. 5: 514 - selection block 514) configured to:
receive the analog signal (Fig. 5: 512 - selection block 514 receives the analog signal V_IN); and
apply a negative offset to the analog signal to generate a second internal signal (Fig. 5, Para. [28], [33]: selection block 514 each applies a negative offset, e.g. V_IN−αPD, to the analog signal V_IN) to generate a first internal signal, e.g. output of 514);
a multiplexer (Fig. 5: multiplexer 506) configured to:
receive a selection signal (Fig. 5: the output sample (V_DATA) of the flip-flop 502), wherein the selection signal is a feedback of a previous digital signal outputted by the multiplexer (Fig. 5, Para. [33]: “a flip-flop 502 that samples based on CLK1, where the output sample (V_DATA) of the flip-flop 502 is fed into a data feedback path 504 to control multiplexer 506”);
select one of the first internal signal and the second internal signal (Fig. 5, Para. [44]: “V_IN+αPD [input A] or V_IN−αPD [input B] is selected by multiplexer 506” ); and
output the selected one of the first internal signal and the second internal signal as a third internal signal (Para. [34], [44]: either V_IN+αPD [input A] or V_IN−αPD [input B] is selected by multiplexer 506 and output as a third internal signal); and
a slicer (Fig. 5: the flip-flop 502) configured to sample the third internal signal (Fig. 5: flip-flop 502 samples output [either V_IN+αPD [input A] or V_IN−αPD [input B]] of multiplexer 506) to generate a digital signal that represents a decoded bit value of the analog signal (Fig. 2, Para. [18]-[20]: from the third signal/either V_IN+αPD [input A] or V_IN−αPD [input B]] a digital/V_DATA signal is generated as “a high-bit value (a logical “one”)” digital signal or “ low-bit values (a logical “zero”)” that represents a decoded bit value of the analog RX SIGNAL 212).
Regarding Claim 9, Kenyon discloses;
wherein the analog signal is a single ended signal (Fig. 5: input analog signal, V_IN, is a single ended signal).
Regarding Claim 10, Kenyon discloses;
wherein the analog signal is a differential signal (Fig. 10: analog input signal is a differential signal, i.e. +IN_1 and -IN_1).
Regarding Claim 11, Kenyon discloses;
wherein:
the first summation circuit is configured to apply the positive offset to the analog signal by adding a predefined offset to the analog signal (Fig. 5, Para. [0033]: equalization selection block 512 applies a predefined positive, i.e. “+α”, equalization weight”/offset to the analog V_IN signal); and
the second summation circuit is configured to apply the negative offset to the analog signal by subtracting the predefined offset from the analog signal (Fig. 5, Para. [0033]: equalization selection block 514 applies a predefined negative, i.e. “-α”, equalization weight”/offset to the analog V_IN signal).
Regarding Claim 14, Kenyon discloses;
wherein the slicer is configured to sample the third internal signal according to a strobe signal (Fig. 10; Para. [46]: slicer/flip-flop 502 uses CLK1 generated according to an REF CLK_IN/strobe signal to sample the third internal signal).
Regarding Claim 15, Kenyon discloses;
A system (Fig. 1: “a system with a decision feedback equalizer (DFE) circuit”) comprising:
a controller (Fig. 1: a clock recovery circuit 116) configured to generate a strobe signal (Fig. 1, 10, Para. [21]: clock recovery circuit 116 generates a CLK_1/strobe signal from the output of the VCO 124”);
a transmitter (Fig. 1: transmitter 104) configured to output an analog signal (Fig. 2: outputs transmitter-side analog/TX signal 202); and
a receiver (Fig. 1: receiver 110) configured to:
receive the analog signal from the transmitter through a channel (Fig. 1: receiver 110 receives transmitter-side analog/TX signal 202 through a channel 106);
apply a positive offset to the analog signal to generate a first internal signal (Fig. 5, Para. [26], [33]: 512 - selection block 512 each applies a positive offset, e.g. V_IN+αPD, to the analog signal V_IN) to generate a first internal signal, e.g. output of 512);
apply a negative offset to the analog signal to generate a second internal signal (Fig. 5, Para. [28], [33]: 514 - selection block 514 each applies a negative offset, e.g. V_IN−αPD, to the analog signal V_IN) to generate a first internal signal, e.g. output of 514);
sample at least one of the first internal signal and the second internal signal according to the strobe signal (Fig. 5, Para. [33]: “The flip-flop 508 is configured to sample a first possible data value [the first internal signal] (V_IN+αPD [the first internal signal], where PD is the previous V_DATA sample and +α is an equalization weight) provided by equalization selection block 512” and generates “the output sample (V_DATA) [first digital signal]”)] and “the flip-flop 510 samples another possible data value (V_IN−αPD) provided by equalization selection block 514”and generates “the output sample (V_DATA) [second digital signal]”);
use a previous digital signal as a selection signal (Fig. 5, Para. [33]: “a flip-flop 502 that samples based on CLK1, where the output sample (V_DATA) of the flip-flop 502 is fed (previous digital signal) into a data feedback path 504 to control [as a selection signal] multiplexer 506”) to select a specific signal from the first internal signal and the second internal signal that decodes the analog signal (Fig. 5, Para. [34]: “V_IN+αPD”- first internal signal/output of 512 or “V_IN−αPD”- second internal signal/output of 514 is selected by multiplexer 506” as a specific signal that decodes the analog RX SIGNAL 212); and
based on the sample and the selection, generate a digital signal that represents a decoded bit value of the analog signal (Fig. 2, Para. [18]-[20]: the sampled and selected specific V_DATA signal is output as “a high-bit value (a logical “one”)” digital signal or “low-bit values (a logical “zero”)” digital signal that represents a decoded bit value of the analog RX SIGNAL 212).
Regarding Claim 16, Kenyon discloses;
wherein the receiver comprises:
a first slicer (Fig. 5, Para. [22], [25], [33]: flip-flop 508) configured to sample the first internal signal to generate a first digital signal (Fig. 5, Para. [33]: “The flip-flop 508 is configured to sample a first possible data value [the first internal signal] (V_IN+αPD [the first internal signal], where PD is the previous V_DATA sample and +α is an equalization weight) provided by equalization selection block 512” and generates “the output sample (V_DATA) [first digital signal]”);
a second slicer (Fig. 5, Para. [22], [25], [33]: “the flip-flop 510 samples another possible data value (V_IN−αPD) provided by equalization selection block 514”) configured to sample the second internal signal to generate a second digital signal (Fig. 5, Para. [33]: “the flip-flop 510 samples another possible data value (V_IN−αPD) provided by equalization selection block 514” and generates “the output sample (V_DATA) [second digital signal]”); and
a multiplexer (Fig. 5: multiplexer 506) configured to:
receive the previous digital signal as the selection signal (Fig. 2, 5, Para. [33]: “a flip-flop 502 that samples based on CLK1, where the output sample (V_DATA) of the flip-flop 502 is fed (previous digital signal) into a data feedback path 504 to control [as a selection signal] multiplexer 506”), wherein the previous digital signal is outputted by the multiplexer (Fig. 2, 5, Para. [33]: where the output sample (V_DATA) of the flip-flop 502 is fed (previous digital signal) into a data feedback path 504 to control multiplexer 506”));
select one of the first digital signal and the second digital signal as the specific signal (Fig. 5, Para. [44]: “V_IN+αPD or V_IN−αPD is selected by multiplexer 506); and
output the selected specific signal (Para. [34]: “if the sign of V_DATA (the output of flip-flop 502) is negative, the output of equalization selection block 512 and flip-flop 508 is selected by the multiplexer 506 as the input for flip-flop 502 (V_IN+αPD is selected when V_DATA is negative). Otherwise, if the sign of V_DATA is positive, the output of equalization selection block 514 and flip-flop 510 is selected by the multiplexer 506 as the input for flip-flop 502 (V_IN−αPD is selected when V_DATA is positive)”. That is, a specific V_DATA signal is selected as an output) as a digital signal that represents a decoded bit value of the analog signal (Fig. 2, Para. [18]-[20]: the selected specific V_DATA signal is output as “a high-bit value (a logical “one”)” digital signal or “ low-bit values (a logical “zero”)” digital signal that digital signal that represents a decoded bit value of the analog RX SIGNAL 212).
Regarding Claim 17, Kenyon discloses;
wherein the receiver comprises:
a multiplexer (Fig. 5: multiplexer 506) configured to:
receive the previous digital signal as the selection signal (Fig. 2, 5, Para. [33]: “a flip-flop 502 that samples based on CLK1, where the output sample (V_DATA) of the flip-flop 502 is fed (previous digital signal) into a data feedback path 504 to control [as a selection signal] multiplexer 506”), wherein the previous digital signal is outputted by the multiplexer (Fig. 2, 5, Para. [33]: where the output sample (V_DATA) of the flip-flop 502 is fed (previous digital signal) into a data feedback path 504 to control multiplexer 506”));
select one of the first digital signal and the second digital signal as the specific signal (Fig. 5, Para. [44]: “V_IN+αPD or V_IN−αPD is selected by multiplexer 506); and
a slicer (Fig. 5: the flip-flop 502) configured to sample the selected specific signal (Fig. 5: flip-flop 502 samples output [the selected specific signal/either V_IN+αPD [input A] or V_IN−αPD [input B]] of multiplexer 506) to generate a digital signal that represents a decoded bit value of the analog signal (Fig. 2, Para. [18]-[20]: from the selected specific signal/either V_IN+αPD [input A] or V_IN−αPD [input B]] a digital/V_DATA signal is generated as “a high-bit value (a logical “one”)” digital signal or “ low-bit values (a logical “zero”)” that represents a decoded bit value of the analog RX SIGNAL 212).
Regarding Claim 18, Kenyon discloses;
wherein the analog signal is a single ended signal (Fig. 5: input analog signal, V_IN, is a single ended signal).
Regarding Claim 19, Kenyon discloses;
wherein the analog signal is a differential signal (Fig. 10: analog input signal is a differential signal, i.e. +IN_1 and -IN_1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5, 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kenyon (US 10305704 B1 previously cited) in view of Kimura et al. (NPL titled: “28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS,” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 2014, pp. 38-39, previously cited).
Regarding Claim 5 and 12, Kenyon discloses all as applied to claims 1 and 8 further teaching (Para. [3]) “In DFE, a delay element is introduced into the receiver circuitry and equalization values are combined with an input data stream,” however Kenyon does not teach;
a first delay line configured to apply a first delay to the first internal signal;
a second delay line configured to apply the first delay to the second internal signal; and
a third delay line configured to apply a second delay to a strobe signal being used by the first slicer to sample the first internal signal and by the second slicer to sample the second internal signal.
On the other hand, in the same field of endeavor (Fig. 2.1.1, First paragraph: “decision-feedback equalizer (DFE)”) Kimura et al. teaches;
a first delay line (See below -Modified Fig. 2.1.1: 1st Delay Line or Buffer) configured to apply a first delay to the first internal signal (See below - Modified Fig. 2.1.1: 1st Delay Line or Buffer applies a signal stage delay to first input/internal signal to first slicer);
a second delay line (See below -Modified Fig. 2.1.1: 2nd Delay Line or Buffer) configured to apply the first delay to the second internal signal (See below - Modified Fig. 2.1.1: 2nd Delay Line or Buffer applies the signal stage delay to second input/internal signal to second slicer); and
a third delay line (See below -Modified Fig. 2.1.1: 3rd Delay Line or Buffer) configured to apply a second delay to a strobe signal (See below - Modified Fig. 2.1.1: 3rd Delay Lines or Buffers applies a second delay to a strobe/clock signal, e.g. CK1) being used by the first slicer to sample the first internal signal (See below - Modified Fig. 2.1.1, Fig. 2.1.4: strobe/clock signal, e.g. CK1 is used by a first slicer to sample the first input/internal signal ) and by the second slicer to sample the second internal signal (See below - Modified Fig. 2.1.1, Fig. 2.1.4: strobe/clock signal, e.g. CK1 is used by a second slicer to sample the second input/internal signal).
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Modified Fig. 2.1.1
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the delay element in the DFE in Kenyon’s invention may include a first, a second and a third delay lines configured as taught by Kimura et al. where doing so would (by Kimura et al., first and second paragraph) provide “capability to control output common-mode voltage to optimize circuit operating points” and “to maintain clock quality”
Regarding Claim 20, Kenyon discloses all as applied to claims 15, further teaching (Para. [3]) “In DFE, a delay element is introduced into the receiver circuitry and equalization values are combined with an input data stream,” however Kenyon does not teach;
apply a first delay to the first internal signal;
apply the first delay to the second internal signal; and
apply a second delay to the strobe signal to align the strobe signal with at least one of the first internal signal and the second internal signal being sampled.
On the other hand, in the same field of endeavor (Fig. 2.1.1, First paragraph: “decision-feedback equalizer (DFE)”) Kimura et al. teaches;
apply a first delay to the first internal signal (See below - Modified Fig. 2.1.1: 1st Delay Line or Buffer applies a signal stage delay to first input/internal signal to first slicer);
apply the first delay to the second internal signal (See below - Modified Fig. 2.1.1: 2nd Delay Line or Buffer applies the signal stage delay to second input/internal signal to second slicer); and
apply a second delay to the strobe signal to align the strobe signal with at least one of the first internal signal and the second internal signal being sampled.
apply a second delay to the strobe signal (See below - Modified Fig. 2.1.1: 3rd Delay Lines or Buffers applies a second delay (two stage delay/buffer eg, 2nd paragraph: “There are several buffer stages before and after the PI to maintain clock quality”) to the strobe/clock signal, e.g. CK1) to align the strobe signal with at least one of the first internal signal and the second internal signal being sampled (See below - Modified Fig. 2.1.1, Fig. 2.1.4: strobe/clock signal, e.g. CK1 is used by a first slicer and second slicer to align the strobe/CK1 signal with the first input/internal signal being sampled and the second input/internal signal being sampled).
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Modified Fig. 2.1.1
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the delay element in the DFE in Kenyon’s invention may include a first, a second and a third delay lines configured as taught by Kimura et al. where doing so would (Kimura et al., first and second paragraph) provide “capability to control output common-mode voltage to optimize circuit operating points” and “to maintain clock quality”
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kenyon (US 10305704 B1 previously cited) in view of Hollis (US 20220329464 A1 previously cited).
Regarding Claim 6 and 13, Kenyon discloses all as applied to claim 1 and 8 above, further teaching (Fig. 5, Para. [34]) the multiplexer 506 is configured to: in response to the previous digital signal (V_DATA) being negative (i.e. low voltage), the first digital/V_IN+αPD signal is selected and in response to the previous digital signal (V_DATA) being positive (i.e. high voltage), the second digital/V_IN-αPD signal is selected rather than:
in response to the previous digital signal indicating a high voltage, select the first digital signal and
in response to the previous digital signal indicating a low voltage, select the second digital signal.
On the other hand, in the same field of endeavor (Abstract, Fig. 2: “a control signal to select a mode of decision feedback equalization to be applied to an input data bit”) Hollis teaches ( Para. [0044]-[0045]) “the voltage of the input bit is recognized to be greater than the reference voltage VrefHi, a result signal corresponding to a logical high signal (e.g., “1”)” and “when the voltage of the input bit is recognized to be less than the reference voltage VrefLo, a result signal corresponding to a logical low signal (e.g., “0”)” and that (Fig. 2) multiplexer 58 is configured to;
in response to the previous digital signal digital indicating a high voltage, select the first digital signal (Fig. 2, Para. [0046]: “when the signal received at the control input 82 [the previous digital] corresponds to a logical high signal [i.e. having high voltage], the result signal received at input 78 [first digital signal] is transmitted from the output 84 of the selection circuit 58 as the selected signal to an input 86 of the latch 60”) and
in response to the previous digital signal indicating a low voltage, select the second digital signal (Fig. 2, Para. [0046]: “when the signal received at the control input 82 [the previous digital] corresponds to a logical low signal [i.e. having low voltage], the result signal received at input 80 is transmitted as a selected signal from the output 84 of the selection circuit 58 to an input 86 of the latch 60”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the multiplexer 506 can be controlled to output the first digital/V_IN+αPD signal and the second digital/V_IN-αPD in Kenyon’s invention when the previous digital/V_DATA signal indicate a high voltage and low voltage, respectively as taught by Hollis where doing so would (Hollis., Para. [0002]) “offset (i.e., undo, mitigate) the effect of the channel on the transmitted data”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Verkila et al. (US 10171270 B1) discloses (Fig. 3, col. 6, line 40-58) “DFE 300 comprises a main data path 310 and an auxiliary data path 340. The main data path 310 includes a plurality of addition circuits 312, a plurality of slicers 314, a plurality of digital flip-flops 316, a multiplexer 318, and a digital flip-flop 320. The plurality of addition circuits 312 is coupled to the plurality of slicers 314, the plurality of slicers 314 is coupled to the plurality of digital flip-flops 316, the plurality of digital flip-flops 316 is coupled to the multiplexer 318, and the multiplexer 318 coupled to digital flip-flop 320.”
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMNEET SINGH whose telephone number is (571)272-2414. The examiner can normally be reached 9:30am to 5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sam K Ahn can be reached at 5712723044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AMNEET SINGH/Examiner, Art Unit 2633 /SAM K AHN/Supervisory Patent Examiner, Art Unit 2633
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