DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-7, 9-12, and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US PGPub 2023/0153026, hereafter “Lee,” in view of Ramesh et al., US PGPub 2022/0215235, hereafter “Ramesh.”
With respect to claim 1, Lee teaches a memory controller comprising:
an external device interface configured to receive system configuration setting information from a first external device (par. 92, the storage device 1000 receives HMB allocation information (system configuration setting information) from the host 11 via the communication interface shown in fig. 1, (first external device). The communication interface is shown connecting the Host interface 1160, the HMB controller, the CPU 1110, FTL 1120, ECC Engine 1130, AES Engine 1140, buffer memory 1150 and Memory interface 1170);
a logical address feature map storage circuit configured to generate a logical address feature map by extracting, from the system configuration setting information, logical address feature data that defines a preprocessing type for each logical address range specified by the first external device (pars. 92-96, the HMB mapping table HMBMT (logical address feature map) is generated by extracting the allocation information from the set feature command to define data processing policies (preprocessing types) for each region of the host memory buffer, the regions being the logical address ranges);
a computational core configured to preprocess write-requested data according to the preprocessing type, in response to a write request from the first external device for a logical address included in the logical address feature map (pars. 98-101, the HMB controller receives a write request, checks the data processing policy for the region in the HMB mapping table HMBMT, and performs the data processing operation based on the data processing policy); and
a memory interface configured to transmit the preprocessed write-requested data to a second external device (par. 102, sending the write command and the encoded data to the HMB 14),
wherein
the computational core is configured to preprocess the write-requested data into a format suitable for neural network operation (par. 294, the data processing policy for each region is used to preprocess the write data for a neural network),
the preprocessing of the write-requested data proceeds according to the preprocessing type specified, by the first external device, in each logical address range of the logical address feature map (par. 294, the data processing policy for each region is used to preprocess the write data, the regions comprising logical address ranges of the logical address feature map, as discussed in pars. 98-101)
Lee fails to teach the preprocessed write-requested data is input to the second external device to be processed by the neural network operation.
Ramesh teaches:
the preprocessed write-requested data is input to the second external device to be processed by the neural network operation (par. 60, the data being written is pre-processed for the neural network).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Ramesh before him before the earliest effective filing date, to modify the neural network memory system of Lee with the neural network memory system of Ramesh, in order to optimize the amount of time, processing resources , and/or power consumed in training of neural networks by utilizing multiple memory devices during the training process, as taught by Ramesh in par. 19.
With respect to claim 3, Lee teaches the memory controller according to claim 1, wherein the system configuration setting information is included in a set features command (par. 92).
With respect to claim 4, Lee teaches the memory controller according to claim 3, wherein the logical address feature map storage circuit is configured to generate the logical address feature map by extracting, from the logical address feature data of the set features command, at least a feature field (par. 170, the characteristic information), an attribute field (par. 163, deallocation information), a starting logical address field (par. 178, buffer address), a logical address number field (par. 178, buffer size information), and a logical area identifier field (par. 178, first to fifth memory address ranges MR1 to MR5).
With respect to claim 5, Lee teaches the memory controller according to claim 4, wherein the logical address feature map storage circuit is configured to extract the preprocessing type from a vendor specific value of the feature field (pars. 170-176, the characteristic information includes information about a type of a memory device corresponding to the HMB, and is therefore vendor-specific value. In the example, the fifth characteristic C5, indicating a type of the changed memory device, is extracted and used to update the HMPB allocation table. Based on the updated HMBP allocation table, the data processing policy for the region is changed to a new policy).
With respect to claim 6, Lee teaches the memory controller according to claim 1, wherein the first external device includes a host (par. 92, host 11) and the second external device includes a nonvolatile memory apparatus (par. 42, storage device 1000 includes nonvolatile memory device 1200).
With respect to claim 7, Lee teaches a computational memory apparatus comprising:
a memory controller configured to receive, from an external device, system configuration setting information that defines a preprocessing type for each logical address range (pars. 92-96, the storage device 1000 receives HMB allocation information (system configuration setting information) from the host 11 via the communication interface shown in fig. 1, (external device), that defines data processing policies (preprocessing types) for each region of the host memory buffer, the regions being the logical address ranges. The communication interface is shown connecting the Host interface 1160, the HMB controller, the CPU 1110, FTL 1120, ECC Engine 1130, AES Engine 1140, buffer memory 1150 and Memory interface 1170)
extract logical address feature data that defines the preprocessing type for each logical address range specified by the external device (pars. 92-96, the HMB mapping table HMBMT extracts the allocation information (feature data) from the set feature command to define data processing policies (preprocessing types) for each region of the host memory buffer, the regions being the logical address ranges), and
preprocess write-requested data by the external device based on the preprocessing type corresponding to a logical address of the write-requested data (pars. 98-101, the HMB controller receives a write request, checks the data processing policy for the region in the HMB mapping table HMBMT, and performs the data processing operation based on the data processing policy); and
a nonvolatile memory apparatus configured to store the preprocessed write-requested data (par. 42, memory of storage device 1000 contains nonvolatile memory 1200, and stores the processed write data in pars. 98-102),
wherein
the memory core is configured to preprocess the write-requested data into a format suitable for neural network operation (par. 294, the data processing policy for each region is used to preprocess the write data for a neural network).
the preprocessing of the write-requested data proceeds according to the preprocessing type specified, by the first external device, in each logical address range of the logical address feature map (par. 294, the data processing policy for each region is used to preprocess the write data, the regions comprising logical address ranges of the logical address feature map, as discussed in pars. 98-101)
Lee fails to teach the preprocessed write-requested data is input to a second external device to be processed by the neural network operation.
Ramesh teaches:
the preprocessed write-requested data is input to a second external device to be processed by the neural network operation (par. 60, the data being written is pre-processed for the neural network).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Ramesh before him before the earliest effective filing date, to modify the neural network memory system of Lee with the neural network memory system of Ramesh, in order to optimize the amount of time, processing resources , and/or power consumed in training of neural networks by utilizing multiple memory devices during the training process, as taught by Ramesh in par. 19.
With respect to claim 9, Lee teaches the computational memory apparatus according to claim 7, wherein the system configuration setting information is included in a set features command (par. 92).
With respect to claim 10, Lee teaches the computational memory apparatus according to claim 9, wherein the memory controller is configured to generate a logical address feature map by extracting, from the logical address feature data of the set features command, at least a feature field (par. 170, the characteristic information), an attribute field (par. 163, deallocation information), a starting logical address field (par. 178, buffer address), a logical address number field (par. 178, buffer size information), and a logical area identifier field (par. 178, first to fifth memory address ranges MR1 to MR5).
With respect to claim 11, Lee teaches the computational memory apparatus according to claim 10, wherein the memory controller is configured to extract the preprocessing type from a vendor specific value of the feature field (pars. 170-176, the characteristic information includes information about a type of a memory device corresponding to the HMB, and is therefore vendor-specific value. In the example, the fifth characteristic C5, indicating a type of the changed memory device, is extracted and used to update the HMPB allocation table. Based on the updated HMBP allocation table, the data processing policy for the region is changed to a new policy).
With respect to claim 12, Lee teaches an operation method of a memory controller that communicates with a first external device, the operation method comprising:
receiving system configuration setting information from the first external device (par. 92, the storage device 1000 receives HMB allocation information (system configuration setting information) from the host 11 via the communication interface shown in fig. 1, (first external device). The communication interface is shown connecting the Host interface 1160, the HMB controller, the CPU 1110, FTL 1120, ECC Engine 1130, AES Engine 1140, buffer memory 1150 and Memory interface 1170));
generating a logical address feature map by extracting, from the system configuration setting information, logical address feature data that defines a preprocessing type for each logical address range specified by the first external device (pars. 92-96, the HMB mapping table HMBMT (logical address feature map) is generated by extracting the allocation information from the set feature command to define data processing policies (preprocessing types) for each region of the host memory buffer, the regions being the logical address ranges);
preprocessing write-requested data in a corresponding preprocessing type, in response to a write request from the first external device for a logical address included in the logical address feature map (pars. 98-101, the HMB controller receives a write request, checks the data processing policy for the region in the HMB mapping table HMBMT, and performs the data processing operation based on the data processing policy); and
transmitting the preprocessed write-requested data to a second external device (par. 102, sending the write command and the encoded data to the HMB 14),
wherein the preprocessing the write-requested data comprises:
preprocessing the write-requested data into a format suitable for neural network operation (par. 294, the data processing policy for each region is used to preprocess the write data for a neural network).
the preprocessing of the write-requested data proceeds according to the preprocessing type specified, by the first external device, in each logical address range of the logical address feature map (par. 294, the data processing policy for each region is used to preprocess the write data, the regions comprising logical address ranges of the logical address feature map, as discussed in pars. 98-101)
Lee fails to teach the preprocessed write-requested data is input to the second external device to be processed by the neural network operation.
Ramesh teaches:
the preprocessed write-requested data is input to the second external device to be processed by the neural network operation (par. 60, the data being written is pre-processed for the neural network).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Ramesh before him before the earliest effective filing date, to modify the neural network memory system of Lee with the neural network memory system of Ramesh, in order to optimize the amount of time, processing resources , and/or power consumed in training of neural networks by utilizing multiple memory devices during the training process, as taught by Ramesh in par. 19.
With respect to claim 14, Lee teaches the operation method according to claim 12, wherein the receiving the system configuration setting information comprises receiving a set features command (par. 92).
With respect to claim 15, Lee teaches the operation method according to claim 14, wherein the generating the logical address feature map comprises generating the logical address feature map by extracting, from the logical address feature data of the set features command, at least a feature field (par. 170, the characteristic information), an attribute field (par. 163, deallocation information), a starting logical address field (par. 178, buffer address), a logical address number field (par. 178, buffer size information), and a logical area identifier field (par. 178, first to fifth memory address ranges MR1 to MR5).
With respect to claim 16, Lee teaches the operation method according to claim 15, wherein the generating the logical address feature map further comprises extracting the preprocessing type from a vendor specific value of the feature field (pars. 170-176, the characteristic information includes information about a type of a memory device corresponding to the HMB, and is therefore vendor-specific value. In the example, the fifth characteristic C5, indicating a type of the changed memory device, is extracted and used to update the HMPB allocation table. Based on the updated HMBP allocation table, the data processing policy for the region is changed to a new policy).
With respect to claim 17, Lee teaches the operation method according to claim 12, wherein the first external device includes a host (par. 92, host 11) and the second external device includes a nonvolatile memory apparatus (par. 42, storage device 1000 includes nonvolatile memory device 1200).
Response to Arguments
Applicant's arguments filed 05/26/2026 have been fully considered but they are not persuasive. Firstly, the rejection under of claims 1, 3-7, 9-12 and 14-17 under 35 USC 112(b) for being indefinite are withdrawn, due to the claim amendments dated 05/26/2026. Applicant’s arguments on 9-11, with respect to the rejection of claims 1, 3-7, 9-12 and 14-17 under 35 USC 102(a)(1), are directed towards Lee allegedly failing to teach “"the preprocessed write-requested data is input to the second external device to be processed by the neural network operation,” as found in independent claim 1, and similarly in independent claims 7 and 12. These arguments are moot, as these claims are now rejected under 35 USC 103 as being unpatentable over Lee in view of Ramesh, with Ramesh teaching this new limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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