Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-7, 9-12 and 14-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the processed write-requested data" in line 11. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation "the processed write data" in line 9. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the processed write-requested data" in line 10. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the processing the write-requested data" in line 11. There is insufficient antecedent basis for this limitation in the claim.
The remaining claims mentioned in the header but not specifically addressed depend from the above independent claims and do not resolve the deficiencies of the parent claim, and are therefore also rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-7, 9-12 and 14-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al., US PGPub 2023/0153026.
With respect to claim 1, Lee teaches a memory controller comprising:
an external device interface configured to receive system configuration setting information from a first external device (par. 92, the storage device 1000 receives HMB allocation information (system configuration setting information) from the host 11 via the communication interface shown in fig. 1, (first external device). The communication interface is shown connecting the Host interface 1160, the HMB controller, the CPU 1110, FTL 1120, ECC Engine 1130, AES Engine 1140, buffer memory 1150 and Memory interface 1170);
a logical address feature map storage circuit configured to generate a logical address feature map by extracting, from the system configuration setting information, logical address feature data that defines a preprocessing type for each logical address range specified by the first external device (pars. 92-96, the HMB mapping table HMBMT (logical address feature map) is generated by extracting the allocation information from the set feature command to define data processing policies (preprocessing types) for each region of the host memory buffer, the regions being the logical address ranges);
a computational core configured to preprocess write-requested data according to the preprocessing type, in response to a write request from the first external device for a logical address included in the logical address feature map (pars. 98-101, the HMB controller receives a write request, checks the data processing policy for the region in the HMB mapping table HMBMT, and performs the data processing operation based on the data processing policy); and
a memory interface configured to transmit the processed write-requested data to a second external device (par. 102, sending the write command and the encoded data to the HMB 14),
wherein
the computational core is configured to preprocess the write-requested data into a format suitable for neural network operation (par. 294, the data processing policy for each region is used to preprocess the write data for a neural network).
the preprocessing of the write-requested data proceeds according to the preprocessing type specified, by the first external device, in each logical address range of the logical address feature map (par. 294, the data processing policy for each region is used to preprocess the write data, the regions comprising logical address ranges of the logical address feature map, as discussed in pars. 98-101)
With respect to claim 3, Lee teaches the memory controller according to claim 1, wherein the system configuration setting information is included in a set features command (par. 92).
With respect to claim 4, Lee teaches the memory controller according to claim 3, wherein the logical address feature map storage circuit is configured to generate the logical address feature map by extracting, from the logical address feature data of the set features command, at least a feature field (par. 170, the characteristic information), an attribute field (par. 163, deallocation information), a starting logical address field (par. 178, buffer address), a logical address number field (par. 178, buffer size information), and a logical area identifier field (par. 178, first to fifth memory address ranges MR1 to MR5).
With respect to claim 5, Lee teaches the memory controller according to claim 4, wherein the logical address feature map storage circuit is configured to extract the preprocessing type from a vendor specific value of the feature field (pars. 170-176, the characteristic information includes information about a type of a memory device corresponding to the HMB, and is therefore vendor-specific value. In the example, the fifth characteristic C5, indicating a type of the changed memory device, is extracted and used to update the HMPB allocation table. Based on the updated HMBP allocation table, the data processing policy for the region is changed to a new policy).
With respect to claim 6, Lee teaches the memory controller according to claim 1, wherein the first external device includes a host (par. 92, host 11) and the second external device includes a nonvolatile memory apparatus (par. 42, storage device 1000 includes nonvolatile memory device 1200).
With respect to claim 7, Lee teaches a computational memory apparatus comprising:
a memory controller configured to receive, from an external device, system configuration setting information that defines a preprocessing type for each logical address range (pars. 92-96, the storage device 1000 receives HMB allocation information (system configuration setting information) from the host 11 via the communication interface shown in fig. 1, (external device), that defines data processing policies (preprocessing types) for each region of the host memory buffer, the regions being the logical address ranges. The communication interface is shown connecting the Host interface 1160, the HMB controller, the CPU 1110, FTL 1120, ECC Engine 1130, AES Engine 1140, buffer memory 1150 and Memory interface 1170)
extract logical address feature data that defines the preprocessing type for each logical address range specified by the external device (pars. 92-96, the HMB mapping table HMBMT extracts the allocation information (feature data) from the set feature command to define data processing policies (preprocessing types) for each region of the host memory buffer, the regions being the logical address ranges), and
preprocess write data write-requested by the external device based on the preprocessing type corresponding to a logical address of the write data (pars. 98-101, the HMB controller receives a write request, checks the data processing policy for the region in the HMB mapping table HMBMT, and performs the data processing operation based on the data processing policy); and
a nonvolatile memory apparatus configured to store the processed write data (par. 42, memory of storage device 1000 contains nonvolatile memory 1200, and stores the processed write data in pars. 98-102),
wherein
the computational core is configured to preprocess the write-requested data into a format suitable for neural network operation (par. 294, the data processing policy for each region is used to preprocess the write data for a neural network).
the preprocessing of the write-requested data proceeds according to the preprocessing type specified, by the first external device, in each logical address range of the logical address feature map (par. 294, the data processing policy for each region is used to preprocess the write data, the regions comprising logical address ranges of the logical address feature map, as discussed in pars. 98-101)
With respect to claim 9, Lee teaches the computational memory apparatus according to claim 7, wherein the system configuration setting information is included in a set features command (par. 92).
With respect to claim 10, Lee teaches the computational memory apparatus according to claim 9, wherein the memory controller is configured to generate a logical address feature map by extracting, from the logical address feature data of the set features command, at least a feature field (par. 170, the characteristic information), an attribute field (par. 163, deallocation information), a starting logical address field (par. 178, buffer address), a logical address number field (par. 178, buffer size information), and a logical area identifier field (par. 178, first to fifth memory address ranges MR1 to MR5).
With respect to claim 11, Lee teaches the computational memory apparatus according to claim 10, wherein the memory controller is configured to extract the preprocessing type from a vendor specific value of the feature field (pars. 170-176, the characteristic information includes information about a type of a memory device corresponding to the HMB, and is therefore vendor-specific value. In the example, the fifth characteristic C5, indicating a type of the changed memory device, is extracted and used to update the HMPB allocation table. Based on the updated HMBP allocation table, the data processing policy for the region is changed to a new policy).
With respect to claim 12, Lee teaches an operation method of a memory controller that communicates with a first external device, the operation method comprising:
receiving system configuration setting information from the first external device (par. 92, the storage device 1000 receives HMB allocation information (system configuration setting information) from the host 11 via the communication interface shown in fig. 1, (first external device). The communication interface is shown connecting the Host interface 1160, the HMB controller, the CPU 1110, FTL 1120, ECC Engine 1130, AES Engine 1140, buffer memory 1150 and Memory interface 1170));
generating a logical address feature map by extracting, from the system configuration setting information, logical address feature data that defines a preprocessing type for each logical address range specified by the first external device (pars. 92-96, the HMB mapping table HMBMT (logical address feature map) is generated by extracting the allocation information from the set feature command to define data processing policies (preprocessing types) for each region of the host memory buffer, the regions being the logical address ranges);
preprocessing write-requested data in a corresponding preprocessing type, in response to a write request from the first external device for a logical address included in the logical address feature map (pars. 98-101, the HMB controller receives a write request, checks the data processing policy for the region in the HMB mapping table HMBMT, and performs the data processing operation based on the data processing policy); and
transmitting the processed write-requested data to a second external device (par. 102, sending the write command and the encoded data to the HMB 14),
wherein the processing the write-requested data comprises:
preprocessing the write-requested data into a format suitable for neural network operation (par. 294, the data processing policy for each region is used to preprocess the write data for a neural network).
the preprocessing of the write-requested data proceeds according to the preprocessing type specified, by the first external device, in each logical address range of the logical address feature map (par. 294, the data processing policy for each region is used to preprocess the write data, the regions comprising logical address ranges of the logical address feature map, as discussed in pars. 98-101)
With respect to claim 14, Lee teaches the operation method according to claim 12, wherein the receiving the system configuration setting information comprises receiving a set features command (par. 92).
With respect to claim 15, Lee teaches the operation method according to claim 14, wherein the generating the logical address feature map comprises generating the logical address feature map by extracting, from the logical address feature data of the set features command, at least a feature field (par. 170, the characteristic information), an attribute field (par. 163, deallocation information), a starting logical address field (par. 178, buffer address), a logical address number field (par. 178, buffer size information), and a logical area identifier field (par. 178, first to fifth memory address ranges MR1 to MR5).
With respect to claim 16, Lee teaches the operation method according to claim 15, wherein the generating the logical address feature map further comprises extracting the preprocessing type from a vendor specific value of the feature field (pars. 170-176, the characteristic information includes information about a type of a memory device corresponding to the HMB, and is therefore vendor-specific value. In the example, the fifth characteristic C5, indicating a type of the changed memory device, is extracted and used to update the HMPB allocation table. Based on the updated HMBP allocation table, the data processing policy for the region is changed to a new policy).
With respect to claim 17, Lee teaches the operation method according to claim 12, wherein the first external device includes a host (par. 92, host 11) and the second external device includes a nonvolatile memory apparatus (par. 42, storage device 1000 includes nonvolatile memory device 1200).
Response to Arguments
Applicant's arguments filed 01/09/2026 have been fully considered but they are not persuasive. Applicant argues on pages 8-12, with respect to the independent claims 1, 7 and 12, that Lee allegedly fails to teach the computational core is configured to preprocess the write-requested data into a format suitable for neural network operation by the first external device, according to the preprocessing type. Applicant cites pars. 33-35 of their specification to specify what they mean by suitable for neural network operation. Finally, Applicant describes on par. 11 that Lee discloses that the HMB controller 1180 performs the encoding operation based on the data processing policy and selects the best data processing policy for each of the plurality of regions by using the machine learning model. Lee describes in par. 294 that the machine learning may be a neural network. By using the neural network to select the preprocessing type/data processing policy and preprocessing the data, Lee is preprocessing the write-requested data into a format suitable for neural network operation. Applicant’s citation of pars. 33-35 and arguments on pages 9-10 appear to more narrowly defining “format suitable for neural network operation” to mean that it produces data that serves as an input to be processed by a neural network. This is not required by the broadest reasonable interpretation of “suitable for neural network operation.”
Conclusion
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132