DETAILED ACTION
1. This Office action is in response to the amendment filed on 02/02/2026.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
5. Claims 2 and 3 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 2 recites “wherein the second control circuit comprises a second comparator that outputs a signal”. This limitation makes claim 2 improper because it directly contradicts the limitation from claim 1 that “wherein the second control circuit comprises an error amplifier”.
Claim 3 depends from claim 2 and this is likewise in improper dependent form as it inherits the above deficiencies.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claim(s) 1 - 3, 5 - 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshio (US Pub. No. 2008/0100272 A1) in view of Yano et al (US Pub. No. 2013/0134954 A1) and Fukui (Pub. No. 2003/0076697 A1); (hereinafter Yoshio, Yano et al and Fukui).
Regarding claim 1, Yoshio [e.g., Figs. 1, 2 and 8] discloses a DC-DC converter [e.g., -- refer to Fig. 2 --, power supply device 116 containing C-Pump 134 and LDO 135], comprising: a first input terminal [e.g., -- refer to Fig. 8 for charge pump part 134 --, BAT+ terminal], a second input terminal [e.g., PAC+], a first output terminal [e.g., grounded terminal of resistor R13], and a second output terminal [e.g., BAT- terminal]; a charge pump circuit [e.g., charge pump 134], comprising an oscillation circuit [e.g., oscillator 132 connected to charge pump control circuit 143A via CLK signal] and provided between the first input terminal and the first output terminal [e.g., between BAT+ terminal and grounded terminal of resistor R13]; a first control circuit, comprising a first comparator [e.g., comparator 142] and outputs a signal comprising two signal levels [e.g., signal W_DET] based on a magnitude relationship between a voltage proportional to an output voltage between the first output terminal and the second output terminal and a first reference voltage [e.g., output signal based on VOPO and reference voltage VBG], and generating a first control signal that controls switching of the signal between ON and OFF of an oscillation operation of the oscillation circuit [e.g., control switching operation of charge pump control circuit 143A, p. 0152 recites “The comparison circuit 148 compares the power detecting signal W_SENS with the reference voltage VBG and outputs the comparison result as a signal W_DET. In other words, if the power detecting signal W_SENS is higher than the reference voltage VBG, a high-level signal W_DET is output, and if the power detecting signal W_SENS is lower than the reference voltage VBG, a low-level signal..” Examiner note: paragraph presented above mistakenly call the comparison circuit as “148”. However, this is a typo and paragraph is referring to comparison circuit “142”, not “148”]; and a second control circuit [e.g., comparator 144], outputting a signal [e.g., signal VBT_DET1] based on a voltage proportional to an input voltage between the first input terminal and the second input terminal and a second reference voltage [e.g., based on voltage V11 and reference voltage VGB] as a second control signal that controls the oscillation operation of the oscillation circuit [e.g., control switching operation of charge pump control circuit 143A, p. 0135 recites “The comparison circuit 144 compares the voltage VII with the reference voltage VBG and outputs a signal VBT_DET1 corresponding to the comparison result. In other words, if the voltage VII is higher than the reference voltage VBG, a high-level signal VBT_DET1 is output, and if the voltage VII is lower than the reference voltage VBG, a low-level signal VBT_DET1 is output.”].
Yoshio does not disclose an error amplifier that outputs a signal that amplifies a difference between the voltage proportional to the input voltage and the second reference voltage, and outputs a signal as the second control signal that controls an oscillation frequency of the oscillation circuit, wherein the signal output from the error amplifier as the second control signal controls adjusting the oscillation frequency of the oscillation circuit within a predetermined range.
Yano et al [e.g., Figs. 2A and 5A] teaches a control circuit comprises an error amplifier [e.g., -- refer to Fig. 5A for a constant voltage circuit --, error amplifier 11] that outputs a signal that amplifies a difference between the voltage proportional to the input voltage and the second reference voltage [e.g., amplifies difference between Vout (voltage proportional to VDD) and reference voltage (Vref)], and outputs a signal as the second control signal that controls an oscillation frequency of the oscillation circuit [e.g., control oscillation circuit 15B], wherein the signal output from the error amplifier as the second control signal controls adjusting the oscillation frequency of the oscillation circuit within a predetermined range [e.g., controls oscillation frequency proportional to input current p. 0044 recites “The ring oscillator depicted in FIG. 2A has P-channel transistors 21, 23, and 25 and N-channel transistors 22, 24, and 26, and outputs an oscillation signal having an oscillation frequency corresponding to the current I21 that corresponds to an input current.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Yoshio with wherein the second control circuit comprises an error amplifier that outputs a signal that amplifies a difference between the voltage proportional to the input voltage and the second reference voltage, and outputs a signal as the second control signal that controls an oscillation frequency of the oscillation circuit, wherein the signal output from the error amplifier as the second control signal controls adjusting the oscillation frequency of the oscillation circuit within a predetermined range as suggested by Yano et al to amplify a difference between a voltage and a reference voltage to control the oscillation circuit based on the output of the error amplifier circuit.
Additionally, Yoshio does not discloses a first comparator that has a hysteresis characteristic.
Fukui [e.g., Fig. 1] teaches a comparator [e.g., CMP2] that has a hysteresis characteristic [e.g., p. 0054 recites "In comparator CMP2, a hysteresis characteristic is given to the differential circuit by resistor elements R21, R22, R23, and R24. That is, the output of comparator CMP2 remains independent of output differential voltage V1 of comparator CMP1 and is kept constant until output differential voltage V1 of comparator CMP1 reaches a fixed value or higher"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Yoshio with a first comparator that has a hysteresis characteristic since it is known in the art the benefits of to minimize the influence of noise within the comparator.
Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Yoshio with a first comparator that has a hysteresis characteristic as suggested by Fukui to allow the comparator to restrain parasitic oscillations to stabilize the circuit and realize a desired operating characteristic [e.g., p. 0070 recites "Furthermore, the present invention is advantageous in that parasitic oscillation can be restrained by providing the charge pump driver circuit with a comparator having a hysteresis characteristic, the hysteresis characteristic can be realized easily using resistor elements, the circuit characteristic can be stabilized, and a desired operating characteristic can be realized"].
Regarding claim 2, Yoshio [e.g., Figs. 1, 2 and 8] discloses wherein the second control circuit comprises a second comparator [e.g., comparator 144] that outputs a signal [e.g., VBT_DET1] comprising two signal levels based on a magnitude relationship between the voltage proportional to the input voltage and the first reference voltage[e.g., outputs VBT_DET1 based on voltage V11 and reference voltage VGB] as the second control signal [e.g., signal VBT_DET1], and the second control signal is a control signal that controls switching between ON and OFF of the oscillation operation of the oscillation circuit [e.g., control switching operation of charge pump control circuit 143A, p. 0135 recites “The comparison circuit 144 compares the voltage VII with the reference voltage VBG and outputs a signal VBT_DET1 corresponding to the comparison result. In other words, if the voltage VII is higher than the reference voltage VBG, a high-level signal VBT_DET1 is output, and if the voltage VII is lower than the reference voltage VBG, a low-level signal VBT_DET1 is output.”].
Regarding claim 3, Yoshio discloses the claimed invention except for wherein the second comparator is a hysteresis comparator having a hysteresis characteristic.
Fukui [e.g., Fig. 1] teaches a comparator [e.g., CMP2] that has a hysteresis characteristic [e.g., p. 0054 recites "In comparator CMP2, a hysteresis characteristic is given to the differential circuit by resistor elements R21, R22, R23, and R24. That is, the output of comparator CMP2 remains independent of output differential voltage V1 of comparator CMP1 and is kept constant until output differential voltage V1 of comparator CMP1 reaches a fixed value or higher"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Yoshio with wherein the second comparator is a hysteresis comparator having a hysteresis characteristic as suggested by Fukui to allow the comparator to restrain parasitic oscillations to stabilize the circuit and realize a desired operating characteristic [e.g., p. 0070 recites "Furthermore, the present invention is advantageous in that parasitic oscillation can be restrained by providing the charge pump driver circuit with a comparator having a hysteresis characteristic, the hysteresis characteristic can be realized easily using resistor elements, the circuit characteristic can be stabilized, and a desired operating characteristic can be realized"]. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Yoshio since it is known in the art the benefits of a comparator that has a hysteresis characteristic to minimize the influence of noise within the comparator
Regarding claim 5, Yoshio discloses the claimed invention except for wherein the predetermined range of the oscillation frequency of the oscillation circuit that the second control circuit controls comprises 0 Hertz; and the signal output from the error amplifier is output as the second control signal that controls switching between ON in which the oscillation circuit oscillates at a predetermined oscillation frequency and OFF in which the oscillation frequency is in a non-oscillating state of 0 Hertz.
Yano et al [e.g., Figs. 2A and 5A] teaches wherein the predetermined range of the oscillation frequency of the oscillation circuit that the second control circuit controls comprises 0 Hertz [e.g., range of oscillation frequency corresponding to input current , 0 Hertz when clock signal is low and circuit is non-operational]; and the signal output from the error amplifier [e.g., output signal output transistor 12] is output as the second control signal that controls switching between ON in which the oscillation circuit oscillates at a predetermined oscillation frequency [e.g., output of error amplifier 12 controls oscillation circuit 15B corresponding to the range of input current, p.0065 recites “The oscillation circuit 15B, similarly to the oscillation circuit 15A in the first embodiment, outputs an oscillation signal having an oscillation frequency corresponding to a current to be input. Further, the charge pump circuit 16B, similarly to the charge pump circuit 16A in the first embodiment, receives the oscillation signal output from the oscillation circuit 15B as an input clock to output a voltage corresponding to the input clock as an output CPO.”] and OFF in which the oscillation frequency is in a non-oscillating state of 0 Hertz [e.g., 0 Hertz when is not operating].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Yoshio wherein the predetermined range of the oscillation frequency of the oscillation circuit that the second control circuit controls comprises 0 Hertz; and the signal output from the error amplifier is output as the second control signal that controls switching between ON in which the oscillation circuit oscillates at a predetermined oscillation frequency and OFF in which the oscillation frequency is in a non-oscillating state of 0 Hertz as suggested by Yano et al to amplify a difference voltage between an voltage and a reference voltage to control the output voltage based on an output of the error amplifier circuit.
Regarding claim 6, Yoshio [e.g., Figs. 1, 2 and 8] discloses wherein the second control circuit [e.g., comparator 144] is configured to be capable of generating the second control signal [e.g., generated VBT_DET1].
Yoshio does not disclose which the oscillation frequency of the oscillation circuit increases as a voltage input to the first input terminal and the second input terminal increases, and the oscillation frequency of the oscillation circuit decreases as to the voltage input to the first input terminal and the second input terminal decreases.
Yano et al [e.g., Figs. 2A and 5A] teaches which the oscillation frequency of the oscillation circuit increases as a voltage input to the first input terminal and the second input terminal increases, and the oscillation frequency of the oscillation circuit decreases as to the voltage input to the first input terminal and the second input terminal decreases [e.g., p. 0063 recites “The oscillation circuit 15B and the charge pump circuit 16B configure a voltage generation circuit. The oscillation circuit 15B, similarly to the oscillation circuit 15A in the first embodiment, outputs an oscillation signal having an oscillation frequency corresponding to a current to be input. Further, the charge pump circuit 16B, similarly to the charge pump circuit 16A in the first embodiment, receives the oscillation signal output from the oscillation circuit 15B as an input clock to output a voltage corresponding to the input clock as an output CPO.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Yoshio with which the oscillation frequency of the oscillation circuit increases as a voltage input to the first input terminal and the second input terminal increases, and the oscillation frequency of the oscillation circuit decreases as to the voltage input to the first input terminal and the second input terminal decreases as suggested by Yano et al to linearly change and control the voltage to be supplied to the output transistor and to reduce the leakage current while suppressing a fluctuation in the output voltage.
Regarding claim 7, Yoshio discloses the claimed invention except for wherein at least one of the first control circuit and the second control circuit comprises two field-effect transistors.
Yano et al [e.g., Figs. 2A and 5A] teaches wherein at least one of the first control circuit and the second control circuit comprises two field-effect transistors [e.g. transistors 51 - 53].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Yoshio wherein at least one of the first control circuit and the second control circuit comprises two field-effect transistors as suggested by Yano et al to control the oscillation of the oscillation circuit depending on the signal received via the input terminal of the inverter circuit [p. 0063 recites “The oscillation circuit 15B, similarly to the oscillation circuit 15A in the first embodiment, outputs an oscillation signal having an oscillation frequency corresponding to a current to be input.”].
Regarding claim 9, Yoshio [e.g., Figs. 1, 2 and 8] discloses oscillation control circuit [e.g., oscillation 132 controlled by charge pump control circuit 143A], comprising a first input port connected to an output terminal of the error amplifier [e.g., first input connected to control circuit containing differential amplifying circuit 149 and comparator 142 receiving W_DET signal], and a second input port connected to an output terminal of the first control circuit [e.g., second input of control circuit 143A connected to output of comparator 144].
Yoshio does not discloses wherein the oscillation circuit comprises a ring oscillator including a plurality of inverters connected in a ring shape, and wherein the oscillation control circuit comprises a transistor including a gate connected to an output terminal of the error amplifier, a source connected to the first input terminal, and a drain connected to a power supply terminal of each of the plurality of inverters of the ring oscillator.
Yano et al [e.g., Figs. 2A and 5A] teaches wherein the oscillation circuit comprises a ring oscillator including a plurality of inverters connected in a ring shape [e.g., -- refer to FIG. 2A for a circuit diagram depicting a configuration example of an oscillation circuit -- , oscillation circuit 15B containing ring oscillator circuit], and wherein the oscillation control circuit comprises a transistor [e.g., transistor 53 controlling oscillation circuit 15B] including a gate connected to an output terminal of the error amplifier [e.g., gate of transistor 53 connected to error amplifier 11], a source connected to the first input terminal [e.g., source connected to supply voltage VDD], and a drain connected to a power supply terminal of each of the plurality of inverters of the ring oscillator [e.g., drain of transistor 53 connected to oscillation circuit 15B].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Yoshio with wherein the oscillation circuit comprises a ring oscillator including a plurality of inverters connected in a ring shape, and wherein the oscillation control circuit comprises a transistor including a gate connected to an output terminal of the error amplifier, a source connected to the first input terminal, and a drain connected to a power supply terminal of each of the plurality of inverters of the ring oscillator as suggested by Yano et al to output an oscillation signal having an oscillation frequency corresponding to a current value.
9. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshio (US Pub. No. 2008/0100272 A1) in view of Yano et al (US Pub. No. 2013/0134954 A1), Fukui (US Patent No. 7,567,140 B2) and Ishino et al (US Pub. No. 2012/0235623 A1); (hereinafter Yoshio, Yano et al, Fukui and Ishino et al).
Regarding claim 8, Yoshio [e.g., Figs. 1, 2 and 8] discloses wherein the second control circuit comprises a reference voltage circuit that generates the second reference voltage [e.g., voltage received by comparator 144 generated by reference voltage generating circuit 114].
Yoshio does not disclose the reference voltage circuit has a temperature characteristic matched with a temperature characteristic of a power generation element comprised in a circuit connected to the first input terminal and the second input terminal.
Ishino et al [e.g., Fig. 7] teaches the reference voltage circuit [e.g., voltage COREVDD] has a temperature characteristic matched with a temperature characteristic of a power generation element comprised in a circuit connected to the first input terminal and the second input terminal [e.g., p. 108 recites “Furthermore, by optimizing the size W/L of each transistor, such an arrangement provides a threshold voltage VTH having temperature characteristics that conform to the temperature characteristics of the voltage Vin output from the solar battery 4.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Yoshio with the reference voltage circuit has a temperature characteristic matched with a temperature characteristic of a power generation element comprised in a circuit connected to the first input terminal and the second input terminal as suggested by Ishino et al such an arrangement allows the threshold voltage to have the same temperature dependence as the temperature dependence of the open voltage of the solar battery.
Response to Arguments
10. Applicant’s arguments with respect to claim(s) 1 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner’s Note
11. Examiner has cited particular paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
12. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Pub. No. 2008/0266917 A1 (Lin et al) discloses a DC/DC converting system, comprising a charge pump adapted to provide an operation voltage to the DC/DC converter.
US Pub. No. 2019/0199216 A1 (Hayashi) discloses a power supply apparatus that can boost input voltage from a low-power input source.
US Pub. No. 2016/0233770 A1 (Arakawa et al) discloses a charge pump circuit and an output voltage control circuit which comprises offset free comparator circuits and differential amplifiers.
14. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ULARISLAO CORDOVA whose telephone number is (571)272-4690. The examiner can normally be reached Monday-Friday 7:30 - 5:00 ET.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
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