DETAILED ACTION
1. This Office action is in response to the amendment filed on 02/05/2026.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claim(s) 1- 6 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US Pub. No. 2013/0069607 A1) in view of Takada et al (US 2017/0269622 A1); (hereinafter Suzuki and Takada et al)
Regarding claim 1, Suzuki [e.g., Fig. 6] discloses a voltage regulator [e.g., --refer to Fig. 6 for voltage regulator --], comprising: an error amplification circuit [e.g., differential amplifier 20], outputting a signal amplifying a difference between a reference voltage and a feedback voltage [e.g., output signal based on reference voltage Vref (10) and feedback voltage Vfb]; a source ground amplification circuit [e.g., MOS transistor 23a, current source 24a, resistor 21 and capacitor 22, p. 0027 recites “Moreover, the drain of the MOS transistor 23a is connected to the gate terminal of the MOS transistor 14 constituting a second source ground amplifier circuit.”], amplifying the signal supplied from the error amplification circuit and outputting the signal as a control signal [e.g., supplies control signal to gate of MOS transistor 14]; and an output transistor [e.g., MOS transistor 14], including a gate to which the control signal is supplied and outputting an output voltage [e.g., control signal supplied to gate of MOS transistor 14 to generate output voltage], the source ground amplification circuit, including a phase advance compensation circuit containing a first resistor and a capacitor [e.g., resistor 21 and capacitor 22], …, and a first transistor [e.g., MOS transistor 23a] containing a gate receiving the signal output from the error amplification circuit [e.g., gate of MOS transistor 23a receives signal from differential amplifier 20], a source connected with a first end of the first resistor and a first end of the capacitor [e.g., source of MOS transistor 23a connected to first end of resistor 21 and capacitor 22 via when conducting, Examiner’s note: For examination purposes, the examiner will interpret the term “connected” in its broadest sense to refer as electrical components that are connected directly or indirectly in a way that allows for the transfer of electrical energy or signals between them], the first resistor and the capacitor being contained in the phase advance compensation circuit [e.g., p. 0032 recites “The MOS transistor 23 and the constant current source 24 of the first source ground amplifier circuit control the gate terminal of the MOS transistor 14 via the resistor 21 and the capacitor 22, which constitute a phase compensation circuit.”],
Suzuki does not disclose a load containing a second resistor and an offset generation element generating an offset voltage, and a drain connected with the load.
Takada et al [e.g., Fig. 1] teaches a load [e.g., voltage generating unit 129] containing a second resistor [e.g., resistor 122] and an offset generation element [e.g., PMOS transistor 123] generating an offset voltage [e.g., generates voltage VG2, p. 0033 recites “…, the current I2 is supplied to the voltage generating unit 129, and hence the voltage VG2, which is generated at the one end of the voltage generating unit 129, also has a small value.”], and a drain connected with the load [e.g., drain of PMOS transistor 112 connected to voltage generating unit 129].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Suzuki with a load containing a second resistor and an offset generation element generating an offset voltage, and a drain connected with the load as suggested by Takada et al to suppress or reduce large fluctuations in the limited current caused by threshold voltage fluctuations.
Regarding claim 2, Suzuki [e.g., Fig. 6] discloses comprising an overcurrent protection circuit [e.g., combination of output load current detection circuit 30, constant current source 25 with respective switch and constant current source 24a with respective switch, p. 0052 recites “…,in the case of an increase in an output load current, the output load current detection circuit 30 turns on the switch circuit of the constant current source 25 to supply electric current to the gate terminal of the MOS transistor 23 and the gate terminal of the MOS transistor 23a from the constant current source 25”. It continues on p. 0055 recites “For example, in the case of an increase in an output load current, the output load current detection circuit 30 supplies electric current from the constant current source 25 to decrease the electric current flowing into the gate terminal of the MOS transistor 14.”] including a switch [e.g., switch connected between constant current source 25 and output load current detection circuit 30] switching a path between a conductive state and an open state in accordance with a voltage based on the control signal [e.g., controls switch to open or close generated based on the control signal supplied by differential amplifier 20], the path connecting an output terminal of the error amplification circuit and a power terminal supplying a power voltage as a reference of a circuit operation [e.g., connects output of differential amplifier 20 with input rail 15].
Regarding claim 3, Suzuki [e.g., Fig. 6] discloses comprising an overcurrent protection circuit [e.g., combination of output load current detection circuit 30, constant current source 25 with respective switch and constant current source 24a with respective switch] including: a voltage generation circuit [e.g., gate voltage generated by constant current source 24a with respective switch, p. 0055 recites “In addition, the output load current detection circuit 30 is able to set the voltage at the gate terminal of the MOS transistor 14 to a desired voltage quickly by increasing the current value of the constant current source 24a, thus improving the transient response characteristics of the voltage regulator.”] connected between a first power terminal supplying a first power voltage [e.g., connected between input rail] and a second power terminal supplying a second power voltage [e.g., grounded rail], and generating a voltage based on the control signal [e.g., generates voltage at the gate terminal of MOS transistor 14 based on signal received by differential amplifier 20, p. 0055 recites “In addition, the output load current detection circuit 30 is able to set the voltage at the gate terminal of the MOS transistor 14 to a desired voltage quickly by increasing the current value of the constant current source 24a, thus improving the transient response characteristics of the voltage regulator.”]; and a switch [e.g., switch connected between constant current source 25 and gate of 23a], switching a path between a conductive state and an open state in accordance with a voltage generated by the voltage generation circuit [e.g., output load current detection circuit 30 opens or closes switch connected between constant current source 25 and gate of 23a depending on the output load current corresponding to the gate voltage of MOS transistor 14, p. 0052 recites “…,in the case of an increase in an output load current, the output load current detection circuit 30 turns on the switch circuit of the constant current source 25 to supply electric current to the gate terminal of the MOS transistor 23 and the gate terminal of the MOS transistor 23a from the constant current source 25”. It continues on p. 0055 recites “For example, in the case of an increase in an output load current, the output load current detection circuit 30 supplies electric current from the constant current source 25 to decrease the electric current flowing into the gate terminal of the MOS transistor 14.”], the path connecting an output voltage of the error amplification circuit and the first power terminal [e.g., connects output of differential amplifier 20 with input rail].
Regarding claim 4, Suzuki discloses the claimed invention except for wherein the offset generation element is configured by a second transistor containing a gate and a drain connected to the gate of the second transistor.
Takada et al [e.g., Fig. 1] teaches wherein the offset generation element [e.g., PMOS transistor 123] is configured by a second transistor containing a gate and a drain connected to the gate of the second transistor [e.g., p. 0028 recites “The PMOS transistor 123 has a gate connected to a drain thereof and one end of the resistor 122.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Suzuki with wherein the offset generation element is configured by a second transistor containing a gate and a drain connected to the gate of the second transistor as suggested by Takada et al to suppress or reduce large fluctuations in the limited current caused by threshold voltage fluctuations.
Regarding claim 5, Suzuki discloses the claimed invention except for wherein the offset generation element is configured by a second transistor containing a gate and a drain connected to the gate of the second transistor.
Takada et al [e.g., Fig. 1] teaches Takada et al [e.g., Fig. 1] teaches wherein the offset generation element [e.g., PMOS transistor 123] is configured by a second transistor containing a gate and a drain connected to the gate of the second transistor [e.g., p. 0028 recites “The PMOS transistor 123 has a gate connected to a drain thereof and one end of the resistor 122.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Suzuki with wherein the offset generation element is configured by a second transistor containing a gate and a drain connected to the gate of the second transistor as suggested by Takada et al to suppress or reduce large fluctuations in the limited current caused by threshold voltage fluctuations.
Regarding claim 6, Suzuki discloses the claimed invention except for wherein the offset generation element is configured by a second transistor containing a gate and a drain connected to the gate of the second transistor.
Takada et al [e.g., Fig. 1] teaches Takada et al [e.g., Fig. 1] teaches wherein the offset generation element [e.g., PMOS transistor 123] is configured by a second transistor containing a gate and a drain connected to the gate of the second transistor [e.g., p. 0028 recites “The PMOS transistor 123 has a gate connected to a drain thereof and one end of the resistor 122.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Suzuki with wherein the offset generation element is configured by a second transistor containing a gate and a drain connected to the gate of the second transistor as suggested by Takada et al to suppress or reduce large fluctuations in the limited current caused by threshold voltage fluctuations.
Examiner’s Note
7. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
8. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
9. Applicant’s arguments with respect to claim(s) 1 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Pub. No. 2008/0180079 A1 (Kurozo et al) discloses a voltage regulator including a phase compensation circuit.
US Pub. No. 2009/0201618 A1 (Hasegawa et al) discloses an overcurrent protection circuit.
US Pub. No. 2014/0239928 A1 (Taniguchi) discloses a phase compensation of a voltage regulator.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
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