DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishida et al. (2020/0072903 hereinafter Nishida), in view of Konmoto (US 2008/0191747 hereinafter Konmoto)
As to claim 1, Nishida discloses in Figs. 1, an integrated circuit (1 as shown in Fig. 1), comprising: an output circuit (11 as show in Fig. 1) that outputs an inspection signal (ST1 as shown in Fig. 1); a logic circuit (12 as shown in Fig. 1) that is supplied with power from a power supply (para 0030) and outputs a result signal based on the inspection signal and a state of the power supply in response to the inspection signal being input (ST1 as shown in Fig. 1); and a determination circuit (13 as shown in Fig. 1) determines a state of the logic circuit based on the inspection signal (ST1 as shown in Fig. 1) and the result signal respectively input from the output circuit and the logic circuit (12 as shown in Fig. 1, para 0044).
Nishida does not disclose a power from another power supply for the determination circuit.
However, Konmoto discloses a power from another power supply (30 as shown in fig. 1) for the determination circuit.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify the system of Nishida and provide another power supply (30 as shown in Fig. 1) for the determination circuit, as taught by Konmoto for keeping stably power during self-testing.
As to the claim 7, Konmoto discloses in Fig. 1, wherein the output circuit is supplied with power from another power supply (30 as shown in Fig. 1).
Allowable Subject Matter
Claims 2-6, 8 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claims 2-6, 8, the prior art does not disclose a plurality of the logic circuits that are connected in parallel to the determination circuit and are respectively supplied with power from power supplies different from the power supply, wherein the output circuit outputs the inspection signal to each of the plurality of logic circuits, and the determination circuit determines states of the plurality of logic circuits based on the inspection signal and a plurality of the result signals respectively output from the plurality of logic circuits, as recited in claim 2; a plurality of the logic circuits that are connected in series and are respectively supplied with power from power supplies different from the power supply, wherein the output circuit outputs the inspection signal to the first logic circuit in an order among the plurality of logic circuits connected in series, and the determination circuit determines states of the plurality of logic circuits based on the inspection signal and the result signal output from the last logic circuit in the order among the plurality of logic circuits connected in series, as recited in claim 3; wherein the logic circuit is a delay circuit in which a delay time changes based on a voltage from the power supply, and the determination circuit determines the state of the logic circuit after a predetermined time elapses since the inspection signal is input, as recited in claims 4-6; and wherein the determination circuit comprises a first flip-flop circuit to which the inspection signal is input, and a second flip-flop circuit to which the result signal is input, as recited in claim 8.
Conclusion
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/TUNG X NGUYEN/ Primary Examiner, Art Unit 2858 9/30/2025
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