DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: element 4 in Fig. 2C and 7C. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Election/Restrictions
Applicant’s election without traverse of claims 1-15 and the cancellation of claims 16-20 in the reply filed on June 06, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
Claim(s) 7, 9, 10, 14, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jo et al (US 20230352529 hereinafter referred to as Jo), .
Regarding Claim 7, Jo teaches a semiconductor structure (10, Fig. 1A-1E, para [0029]) comprising: a top field-effect transistor (FET) (10U, Fig. 1A & 1B, para [0031]) on a portion of a bottom FET (10L, Fig. 1A & 1B, para [0031]); a middle dielectric isolation layer (130, Fig. 1A & 1B &1C, para [0033]) over a top surface of a gate of the bottom FET (10L, Fig. 1A & 1B, para [0031]); an isolation layer (160, Fig. 1A & 1B, para [0039]) connecting sidewalls of adjacent portions of the middle dielectric isolation (See Fig. 1A below for reference), wherein the isolation layer (160, Fig. 1A & 1B, para [0039]) separates (See Fig. 1A bellow for reference) one or more top source/drains (122, Fig. 1A-1D, para [0037]) of the top FET from one or more bottom source/drains (112, Fig. 1A-1D, para [0037]) of the bottom FET.
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Regarding Claim 9, Jo teaches the semiconductor structure of claim 7 (10, Fig. 1A, para [0029]), wherein the isolation layer (160, Fig. 1A &1B, para [0039]) has a top surface and a bottom surface that are each concave (see figure 1A below for reference).
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Regarding Claim 10, Jo teaches the semiconductor structure of claim 7 (10, Fig. 1A, para [0029]), wherein the isolation layer sidewalls (160, Fig. 1A &1B, para [0039]) have a same height as the height of sidewalls of the middle dielectric isolation (130, Fig. 1A & 1B, para [0033], see figure 1A below for reference; the broadest reasonable interpretation of the claim above is that the height of the sidewalls of the middle dielectric isolation is the same as a portion of the height of the sidewalls of the isolation layer).
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Regarding Claim 14, Jo teaches the semiconductor structure of claim 7 (10, Fig. 1E, para [0029]), wherein the top FET is an NFET (10U, Fig. 1A-1C, para [0038]) and the bottom FET is a PFET (10L, Fig. 1A-1C, para [0038]).
Regarding Claim 15, Jo teaches the semiconductor structure of claim 7 (10, Fig. 1E, para [0029]), wherein the top FET is a PFET (10U, Fig. 1A-1C, para [0038]) and the bottom FET is an NFET (10L, Fig. 1A-1C, para [0038]).
Claim Rejections - 35 USC § 103
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al (US 20230352529), in view of Chung et al (US 11862701 hereinafter referred to as Chung).
Regarding Claim 1, Jo teaches a semiconductor structure (10, Fig. 1E, para [0029]) comprising: an isolation layer (160, Fig. 1A & 1B, para [0039]) contacting a top source/drain (122, Fig. 1A & 1B, para [0039]) and a bottom source/drain (112, Fig. 1A & 1B, para {0039}).
Jo does not explicitly teach an air gap between a middle portion of each of the top source/drain, the bottom source/drain, and the isolation layer.
However, in a field of similar endeavor in a similar SFET configuration, Chung teaches
an air gap (249, Fig. 103A-103D, para (39)) between a middle portion of each of the top source/drain (248 S/D, Fig. 103A-103D, para (39)), the bottom source/drain (228 S/D, Fig. 103A-103D, para (39)), and the isolation layer (242, Fig. 103A-103D, para (39); the airgap is caused by merging source drain features from epitaxial growth from the channel sidewalls and would contact both S/D and isolation layer element 242).
The motivation is discussed in the applicant’s case para [0056] wherein it discusses that it is known in the art that air gaps improve the effective capacitance of completed stacked FET devices.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the
effective filing date to combine the teachings of Jo and Chung, to enable the air gap in Jo
according to the teachings of Chung, because the selection of a known material based on its
suitability for its intended use is supported by a prima facie case of obviousness (see MPEP
2144.07).
Regarding Claim 2, Jo teaches the semiconductor structure of claim 1 (10, Fig. 1E, para [0029]), wherein the top source/drain (122, Fig. 1A & 1B, para [0039]), the bottom source/drain (112, Fig. 1A & 1B, para {0039}), and the isolation layer (160, Fig. 1A & 1B, para [0039]) are vertically aligned (See figure below).
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Regarding Claim 3, Jo teaches a semiconductor structure of claim 1 (10, Fig. 1A-1E, para [0029]), wherein the isolation layer (160, Fig. 1A & 1B, para [0039]) has a top surface and a bottom surface that are concave (see figure 1A below for reference)
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Regarding Claim 5, Jo teaches the semiconductor structure of claim 4 (10, Fig. 1E, para [0029]), wherein the middle dielectric isolation (130, Fig. 1A & 1B, para [0033]) resides between a plurality of channels of a top field-effect transistor (FET) and a plurality of channels of a bottom FET (See element 130 in figure 1C below).
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Claim(s) 8, 11, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al (US 20230352529) as applied to claim 7, 10, 14, and 15 above, and further in view of Xie et al (US 11069684 hereinafter referred to as Xie).
Regarding Claim 8, Jo teaches the semiconductor structure of claim 7 (10, Fig. 1E, para [0029]), further comprising: a gate structure (115, Fig. 1A-1C, para [0044]) around the plurality of channels of the top FET (10U, Fig. 1A-1D, para [0031]) and the bottom FET (10L, Fig. 1A-1D, para [0031]).
Jo does not explicitly teach a top source/drain contact contacting each of the one or more top source/drains; and a bottom source/drain contact contacting each of the one or more bottom source/drains not under a portion of the top FET.
However, in a field of similar endeavor in a similar SFET configuration, Xie teaches a top source/drain contact (Xie, 138, Fig. 14, para (51)) contacting each of the one or more top source/drains (Xie, 130, Fig. 14, para (46)); and a bottom source/drain contact (Xie, 140, para (51)) contacting each of the one or more bottom source/drains (Xie, 126, para (42)) not under a portion of the top FET (Xie, 106b, para (28)).
Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to modify Jo in view of Xie and add a source/drain contact directly on the respective source/drain for various added advantages; for example, reduce current leakage while still maintaining good contact conductivity.
Regarding Claim 11, Jo teaches the semiconductor structure of claim 7 (10, Fig. 1A, para [0029]),
Jo does not explicitly teach wherein the isolation layer is composed of a different oxide material than the middle dielectric isolation.
However, in a field of similar endeavor in a similar SFET configuration, Xie teaches wherein the isolation layer and the middle dielectric isolation are composed of different oxide dielectric materials (120 & 128, Fig. 12, para (38) & (45)).
In Xie paragraph (45) it is disclosed that element 128 and element 120 can be made of “TiOx, AlOx, GeOx and the like,” which are oxide dielectric materials and while the embodiment used in Xie describes element 120 and 128 as using the same material, it is implied that the materials can be different. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to use different oxide dielectric materials for element 120 and 128 since the selection of a known material based on its suitability for its intended use is supported by a prima facie case of obviousness (see MPEP 2144.07).
Regarding Claim 13, Jo teaches the semiconductor structure of claim 7 (10, Fig. 1E, para [0029]), wherein: the bottom FET (10L, Fig. 1A-1C, para [0031]) is wider than the top FET (10U, Fig. 1A-1C, para [0031]).
Jo does not explicitly teach wherein each of the bottom source/drain contacts contacts the sidewalls of the middle dielectric isolation.
However, in a field of similar endeavor in a similar SFET configuration, Xie teaches each of the bottom source/drain contacts (Xie, 140, Fig. 14, para (51)) contacts the sidewalls of the middle dielectric isolation (Xie, 146 & 148, Fig. 14, para (54) &(55)). The airgap elements in Xie 146 and 148 are one and the same.
Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to modify Jo in view of Xie and create a middle dielectric isolation that
contacts the bottom source/drain contacts with its sidewalls to improve SFET performance.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al (US 20230352529) as applied to claim 7 above, and further in view of Chung et al (US 11862701).
Regarding Claim 12, Jo teaches the semiconductor structure of claim 7 (10, Fig. 1E, para [0029]).
Jo does not explicitly teach wherein the one or more bottom source/drain top surfaces contact an air gap, wherein the one or more bottom source/drain top surfaces are curved.
However, in a field of similar endeavor in a similar SFET configuration as well as similar source/drain manufacture process, Chung teaches wherein the one or more bottom source/drain top surfaces (Chung, 228S/D, Fig. 103A-103D, para (39)) contact an air gap (Chung, 249, Fig. 103A-103D, para (39)), wherein the one or more bottom source/drain top surfaces (Chung, 228S/D, Fig. 103A-103D, para (39)) are curved.
Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to modify Jo in view of Chung to include a bottom source/drain top surface that contacts an air gap and is curved for the well-known advantage of increasing effective capacitance in a stacked FET.
Claim(s) 4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al (US 20230352529) and Chung et al (US 11862701) as applied to claim 1, 2, 3, 5, and 12 above, and further in view of Xie et al (US 11069684).
Regarding Claim 4, Jo teaches the semiconductor structure of claim 1 (10, Fig. 1E, para [0029]), wherein the isolation layer sidewalls (160, Fig. 1A & 1B, para [0039]) contact a middle dielectric isolation (130, Fig. 1A & 1B, para [0033]; see figure below for contacts)
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Jo does not explicitly teach wherein the isolation layer and the middle dielectric isolation are composed of different oxide dielectric materials.
However, in a field of similar endeavor in a similar SFET configuration, Xie teaches wherein the isolation layer sidewalls (118, Fig. 4 & 12, para (38); referred to as sacrificial layer) contact (see figure below for contact regions) a middle dielectric isolation (128, Fig. 7 & 12, para (45); referred to as sacrificial isolation layer), wherein the isolation layer and the middle dielectric isolation are composed of different oxide dielectric materials (120 & 128, Fig. 12, para (38) & (45)).
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In Xie paragraph (45) it is disclosed that element 128 and element 120 can be made of “TiOx, AlOx, GeOx and the like,” which are oxide dielectric materials and while the embodiment used in Xie describes element 120 and 128 as using the same material, it is implied that the materials can be different. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to use different oxide dielectric materials for element 120 and 128 since the selection of a known material based on its suitability for its intended use is supported by a prima facie case of obviousness (see MPEP 2144.07).
Further, the identified isolation elements of Jo perform the same function as the identified isolation elements of Xie, that being; isolating upper and lower source/drain regions (Jo, para [0039]; Xie, para (46)) and isolating the upper and lower channel structures (Jo, para [0033]; Xie, para (38)). Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to combine the teachings of Jo and Xie, to enable the use of different oxide dielectric materials of the isolation layer and the middle dielectric isolation of Jo according to the teachings of Xie, because the selection of a known material based on its suitability for its intended use is supported by a prima facie case of obviousness (see MPEP 2144.07).
Regarding Claim 6, Jo teaches the semiconductor structure of claim 4 (10, Fig. 1E, para [0029]), wherein the bottom FET is wider than the top FET (See figure 1C below), further comprising: a gate structure (115, Fig. 1A-1C, para [0044]) around the plurality of channels of the top FET and the bottom FET (See figure 1 C below).
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Jo does not explicitly teach a source/drain contact directly on the top source/drain.
However, in a field of similar endeavor in a similar SFET configuration, Xie teaches a source/drain contact (Xie, 138, Fig. 14, para (51)) directly on the top source/drain (Xie, 130, Fig. 14, para (46)).
Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to modify Jo in view of Xie and add a source/drain contact directly on the top source/drain for various added advantages; for example, reduce current leakage while still maintaining good contact conductivity.
Conclusion
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/ONASIS MORA/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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