DETAILED ACTION
1. Claims 1-17 and 20 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
3. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a non-statutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-17 and 19-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-23 of US Pat. 11,934,798. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are directed to the broader version of the limitations with the limitations of the instant application found in the ‘798 patent.
4. Example mapping below:
Application 18/607,653
US Pat. 11,934,798
1. A device, comprising:
at least one memory array; and
a plurality of memory cells of the at least one memory array, the plurality of memory cells accessible via a plurality of bit lines and a plurality of word lines, device is configured to store at least one multiplicand or multiplier in the memory array,
wherein the device is configured to generate a sum of the at least one multiplicand or multiplier based on an operation performed on the at least one multiplicand or multiplier.
2. The device of claim 1, wherein the sum is generated based on a plurality of popcount operations.
3. The device of claim 2, wherein each of the plurality of popcount operations is configured to determine a total number of high bits present in a single word line of the plurality of word lines.
5. The device of claim 1, wherein the device is further configured to generate a multiplication result based on the sum.
6. The device of claim 5, wherein the multiplication result is generated based on sequencing through bits of the multiplier.
1. A system comprising:
at least one memory device; at least one memory array of a memory device; a plurality of memory cells of the at least one memory array, the plurality of memory cells accessible via a plurality of bit lines and a plurality of word lines, wherein at least one multiplicand is stored in the memory array and at least one multiplier is stored in the memory device; the at least one memory device being configured to: generate a sum of the at least one multiplicand based on a plurality of popcount operations performed on the at least one multiplicand, wherein each of the plurality of popcount operations is configured to determine a total number of high bits present in a single word line of the plurality of word lines; and generate a multiplication result based on the sum and by sequencing through bits of the multiplier.
7. The device of claim 1, wherein the sum is generated based on accumulation of a current sum value with a popcount result, in response to a first bit of the multiplier having a first predefined value.
The system of claim 1, wherein the sum is generated based on accumulation of a current sum value with the popcount result, in response to the first bit of multiplier having a first predefined value at a corresponding position.
8. The device of claim 1, wherein at least one multiplicand is stored along a bit line of the plurality of bit lines.
4. The system of claim 1, wherein at least one multiplicand is stored along a corresponding bit line.
9. The device of claim 8, wherein the sum is generated based on a plurality of popcount operations and further wherein the plurality of popcount operations comprises counting the number of bits having the first predefined value for each bit position of the at least one multiplicand.
5. The system of claim 4, wherein the plurality of popcount operations comprises counting the number of bits having the first predefined value for each bit position of the at least one multiplicand.
10. The device of claim 9, wherein bit positions of the at least one multiplicand are stored along a same word line.
6. The system of claim 5, wherein the bit positions of the at least one multiplicand are stored along the same word line.
11. The device of claim 8, further comprising a plurality of sense amplifiers, wherein each sense amplifier is coupled to a respective bit line of the plurality of bit lines, wherein the plurality of sense amplifiers are configured to perform the plurality of popcount operations.
7. The system of claim 4, further comprising a plurality of sense amplifiers, wherein each sense amplifier is coupled to a corresponding bit line, wherein the plurality of sense amplifiers are used to perform the plurality of popcount operations.
Allowable Subject Matter
5. Claims 1-17 and 19-20 would be allowable if rewritten or amended to overcome the rejection(s) under Double Patenting, set forth in this Office action.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
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/MICHAEL D. YAARY/Primary Examiner, Art Unit 2151
