DETAILED ACTION
1. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/26/2026 has been entered.
Response to Arguments
4. Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
5. Applicant is advised that should claims 12 be found allowable, claim 17 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Double Patenting
6. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a non-statutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-23 of US Pat. 11,934,798. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are directed to the broader version of the limitations with the limitations of the instant application found in the ‘798 patent.
7. Example mapping below:
Application 18/607,653
US Pat. 11,934,798
1. A device, comprising:
at least one memory array; and
a plurality of memory cells of the at least one memory array, the plurality of memory cells accessible via a plurality of bit lines and a plurality of word lines.
2. The device of claim 1, wherein the device is configured to store at least one multiplicand or multiplier in the memory array, and
wherein the device is configured to generate a sum of the at least one multiplicand or multiplier based on an operation performed on the at least one multiplicand or multiplier; and wherein the sum is generated based on a plurality of popcount operations.
3. The device of claim 2, wherein each of the plurality of popcount operations is configured to determine a total number of high bits present in a single word line of the plurality of word lines.
5. The device of claim 1, wherein the device is further configured to generate a multiplication result based on the sum.
6. The device of claim 5, wherein the multiplication result is generated based on sequencing through bits of the multiplier.
1. A system comprising:
at least one memory device; at least one memory array of a memory device; a plurality of memory cells of the at least one memory array, the plurality of memory cells accessible via a plurality of bit lines and a plurality of word lines, wherein at least one multiplicand is stored in the memory array and at least one multiplier is stored in the memory device; the at least one memory device being configured to: generate a sum of the at least one multiplicand based on a plurality of popcount operations performed on the at least one multiplicand, wherein each of the plurality of popcount operations is configured to determine a total number of high bits present in a single word line of the plurality of word lines; and generate a multiplication result based on the sum and by sequencing through bits of the multiplier.
7. The device of claim 1, wherein the sum is generated based on accumulation of a current sum value with a popcount result, in response to a first bit of the multiplier having a first predefined value.
The system of claim 1, wherein the sum is generated based on accumulation of a current sum value with the popcount result, in response to the first bit of multiplier having a first predefined value at a corresponding position.
8. The device of claim 1, wherein at least one multiplicand is stored along a bit line of the plurality of bit lines.
4. The system of claim 1, wherein at least one multiplicand is stored along a corresponding bit line.
9. The device of claim 8, wherein the sum is generated based on a plurality of popcount operations and further wherein the plurality of popcount operations comprises counting the number of bits having the first predefined value for each bit position of the at least one multiplicand.
5. The system of claim 4, wherein the plurality of popcount operations comprises counting the number of bits having the first predefined value for each bit position of the at least one multiplicand.
10. The device of claim 9, wherein bit positions of the at least one multiplicand are stored along a same word line.
6. The system of claim 5, wherein the bit positions of the at least one multiplicand are stored along the same word line.
11. The device of claim 8, further comprising a plurality of sense amplifiers, wherein each sense amplifier is coupled to a respective bit line of the plurality of bit lines, wherein the plurality of sense amplifiers are configured to perform the plurality of popcount operations.
7. The system of claim 4, further comprising a plurality of sense amplifiers, wherein each sense amplifier is coupled to a corresponding bit line, wherein the plurality of sense amplifiers are used to perform the plurality of popcount operations.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claim(s) 1, 5, 8, 12, and 15-17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Eilert et al (hereafter Eilert)(US Pub. 20210072957).
10. As to claim 1, Eilert discloses a device (abstract), comprising:
at least one memory array ([0022] memory device may include multiple memory arrays); and
a plurality of memory cells of the at least one memory array ([0022], [0033]-[0034] may include a memory array 130, i.e., including memory cells), the plurality of memory cells accessible via a plurality of bit lines and a plurality of word lines ([0033] Memory array 130 may include memory cells arranged in rows coupled by access lines, which may also be referred to herein as word lines or select lines, and columns coupled by sense lines, which may also be referred to herein as data lines, digit lines, or bit lines.), wherein the device is configured to store at least one multiplicand or multiplier in the memory array ([0041] data stored in memory array 130; [0058] multiplicand and multiplier).
11. As to claim 5, Eilert discloses wherein the device is further configured to generate a multiplication result based on the sum ([0059] Bit values of bits of result 306 are obtained by summing bit values in columns of respective bit positions of result 306.
12. As to claim 8, Eilert discloses wherein at least one multiplicand is stored along a bit line of the plurality of bit lines ([0062] stored in a portion of a memory array along a bit line).
13. As to claims 12 and 17, Eilert discloses an apparatus (abstract) comprising:
a memory array having a plurality of memory cells accessible via a plurality of bit lines and a plurality of word lines ([0022], [0033]-[0034] may include a memory array 130, i.e., including memory cells; 0033] Memory array 130 may include memory cells arranged in rows coupled by access lines, which may also be referred to herein as word lines or select lines, and columns coupled by sense lines, which may also be referred to herein as data lines, digit lines, or bit lines.);
a controller connected to each of the plurality of word lines (fig. 1 and [0024]-[0029] controller); and
a plurality of sense amplifiers ([0064]-[0067] sense amplifiers, i.e. sense amplifier 404 and 410).
14. As to claim 15, Eilert discloses an accumulator in communication with the controller and the plurality of sense amplifiers ([0039], compute component, i.e. accumulator).
15. As to claim 16, Eilert discloses wherein the accumulator comprises a fused multiply-accumulate (FMA) unit ([0145] FMA units).
Allowable Subject Matter
16. Claims 2-4, 6-7, 9-11, 13-14, and 18-20 would be allowable if rewritten to overcome the rejection(s) under Double Patenting, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
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/MICHAEL D. YAARY/Primary Examiner, Art Unit 2151
Prosecution Insights