DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0158346 A1 (Marr) in view of US 2024/0012107 A1 (Yin).
Regarding Claim 1, Marr teaches a power management system for radar RF amplifiers that monitors the amplifier's characteristics and dynamically adjusts both the drain voltage (supply voltage) and gate bias voltage or current (Fig. 8C; [0005], [0348]). Marr explicitly teaches adjusting these values to "increase drain/power efficiency and linearity for a target output power" ([0006]).
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Fig. 8C of Marr reproduced for ease of reference.
While Marr describes the goal of adjusting the supply and bias to maximize efficiency for a specific target power, it relies heavily on current sensing (Fig. 4A, sensor 415; Fig. 8C, sensors 840, 842; [0317], [0349]) rather than a dedicated detector connected to the output terminal to measure the RF power level. Furthermore, Marr does not explicitly disclose the exact, step-by-step algorithmic sequence of maxing out the bias current, sweeping the supply voltage to hit the target power, and then backing down the bias current to hit the target power.
In a similar field of endeavor, Yin teaches a transmit power monitor for a vehicle radar system utilizing a coupler (Fig. 2, 212) connected to a power amplifier's (Fig. 2, 210) output terminal to feed a peak-to-peak detector (Fig. 2, 214; [0022], [0024]), which directly produces a signal corresponding to the power level of the output signal. Yin utilizes this to calibrate a digital threshold value for a comparator to trigger safety alerts when power falls too low, rather than calibrating the power amplifier's supply voltage or bias currents to minimize current consumption.
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Fig. 2 of Yin reproduced for ease of reference.
It would have been obvious to a person having ordinary skill in the art (PHOSITA) to modify the power management system of Marr by incorporating the physical peak-to-peak output power detector taught by Yin (Fig. 2; [0024]) to provide accurate, closed-loop feedback regarding the target output power. The motivation to incorporate Yin's detector into Marr's system is to provide highly accurate, time-continuous monitoring of the actual RF output power, ensuring the system reliably hits the target output power described by Marr.
Furthermore, it would be an obvious algorithmic design choice to implement Marr's directive to optimize power efficiency by utilizing a sequential sweep routine: holding the bias current at a maximum (to ensure the transistor is fully saturated/on), sweeping the supply voltage to reach the target output power, and subsequently reducing the bias current to the absolute minimum magnitude that sustains that target output power. The motivation to implement this specific calibration sequence is derived directly from Marr's explicit instruction to maximize power efficiency for a given target power ([0006]). A PHOSITA understands that maximizing power efficiency inherently requires minimizing the consumed bias currents while satisfying the required RF output power threshold. Because the output power is a multi-variable function of both supply voltage and bias current, establishing a baseline target power by holding the bias high and sweeping the supply voltage, followed by a secondary sweep to minimize the bias current, represents a standard, highly predictable mathematical optimization algorithm to achieve the exact efficiency goals taught by Marr.
Claims 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of Marr.
Regarding Claim 13, Yin discloses a method of calibrating the output power of a power amplifier in a vehicle radar system (Fig. 1, 102; Fig. 4, 400; [0014], [0050]-[0051]). During a calibration routine, a controller sets a digital threshold value to its maximum and transmits it to a digital-to-analog converter (DAC) (Fig. 5, 502, 504; [0058]). Yin iteratively decrements this digital value until an analog reference signal matches the amplifier's measured DC power signal, effectively determining and storing a calibrated value equal to the target minimum allowable output power (Fig. 5, 506-512; [0059]-[0061]).
While Yin sets a threshold for output power using a calibration loop, Yin does not detail providing a first control signal to a current source to maintain a maximum magnitude biasing current while separately determining a second calibrated supply voltage, nor determining a current value that minimizes the sum of biasing magnitudes for a target power level.
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Fig. 5 of Yin reproduced for ease of reference.
However, Marr teaches controlling RF amplifier biasing using a master-slave architecture with DACs that supply finely tuned offset voltages and biasing currents to the amplifier terminals (Fig. 4A, 309, 410, 413; [0315]-[0317]). Marr dynamically adjusts both the drain bias voltage (supply voltage) and gate bias voltage (biasing current) via control signals to optimize figures of merit such as output power and drain efficiency (Fig. 8C, 828, 830, 832; [0006], [0348], [0368]). In an auto-calibration mode, Marr’s smart slave circuit uses current sensor feedback to iteratively tune bias voltage offsets via a DAC until an optimal current is reached that achieves the target maximum power output and optimized efficiency, corresponding to the minimal optimal current for saturated RF power (Fig. 4A, 415; [0317]).
Regarding Claim 16, Yin discloses a vehicle radar subsystem comprising a radar transmitter with a power amplifier outputting an amplified signal (Fig. 2, 210; [0022]). A digital controller receives a detector signal indicative of the output power level via a peak-to-peak detector and a comparator during calibration, determining a calibrated threshold by varying a control signal across a range until the detector signal meets the target (Fig. 2, 204, 214, 224; Fig. 5; [0024]-[0029], [0059]-[0061]).
Yin does not explicitly describe internal power amplifier stages comprising first and second MOSFET devices receiving specific cascode voltages and bias currents, nor their concurrent calibration.
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Fig. 4A of Yin reproduced for ease of reference.
Marr describes solid-state power amplifiers composed of field-effect transistors (FETs/MOSFETs) containing gate, drain, and source terminals (Fig. 4A, 410; Fig. 8C, 828; [0312], [0348]). A power management system provides a bias voltage to the drain terminal and a bias current/voltage to the gate terminal of the FET stages (Fig. 8C; [0348]). A smart slave FPGA controller sends control signals to a DAC to generate varying bias currents and to a power sequencer to regulate supply voltages (Fig. 4A, 105, 309, 413; [0315]-[0317]). By sweeping bias signal magnitudes until sensor feedback indicates target optimal power, Marr identifies and stores optimal calibrated bias currents for normal operation (Fig. 4A; [0317]).
It would have been obvious to a person of ordinary skill in the art to modify Yin’s radar calibration system by incorporating Marr’s multi-stage MOSFET amplifier architecture and dual-parameter (voltage and current) bias tuning calibration. The motivation to combine is to improve power efficiency and thermal management in Yin’s radar system using Marr’s granular master-slave DAC calibration routines, which actively identify optimal set points to minimize unnecessary leakage and quiescent currents while maintaining the target output power.
Claims 2, 3, 5, 6, 12, 14, 15, 17, 18, and 19 are rejected under 35 U.S.C. § 103 as being unpatentable over Yin (US 2024/0012107 A1) in view of Marr (US 2022/0158346 A1).
Regarding these claims, Yin discloses a time-continuous power monitoring and calibration system for a vehicle radar subsystem comprising a radar transmitter equipped with a power amplifier (Fig. 1, 102, 110; [0014]-[0016]). During a calibration operation, Yin describes incrementally varying a digital control signal across a range of values until a measured output from a detector meets a target power threshold (Fig. 4, 408; Fig. 5, 502-512; [0050]-[0061]). To sample this signal, Yin employs a peak-to-peak detector (PPD) connected to a coupler at the power amplifier's output terminal (Fig. 2, 211, 212, 214; [0022]-[0024]). For the calibration search, Yin explains that the iterative algorithm can begin at a maximum value and decrement, or "be reversed such that in the initial step... the digital reference value is instead set to a minimum value and the algorithm could be implemented so that the digital reference value is continuously increased or incremented" ([0062]).
Yin, however, focuses on establishing an analog threshold reference voltage for an alarm comparator. It does not explicitly teach routing multi-layered calibration search algorithms directly to voltage regulators (LDOs) or current digital-to-analog converters (IDACs) to physically manipulate the supply voltage and biasing currents of amplifier stages in order to minimize current draw. Additionally, Yin lacks an explicit disclosure regarding the optimization of search efficiency using a binary search.
Marr, in a similar filed of endeavor, teaches the adaptive generation of high-power RF radiation utilizing master-slave architectures that dynamically adjust the biasing power provided to a solid-state amplifier (Fig. 3, 309, 311; [0308]-[0309]). To provide precise, sequential offset voltages and currents to the gate and drain terminals of the amplifiers, Marr uses Digital-to-Analog Converters (DACs) (Fig. 4A, 413; Fig. 8C, 830, 832; [0315]-[0317], [0348]). To optimize performance and minimize current during off-states, Marr describes an auto-calibration routine that actively monitors sensor feedback, making "10 mV adjustments above and below the pre-programmed voltage... until the optimal voltage is achieved" (Fig. 13, 1308-1310; [0317], [0360]). Marr also details routing power from a main bus through power distributors to step down and regulate voltages for the amplifier components (Fig. 1, 108; [0304]).
It would have been obvious to a person of ordinary skill in the art to combine the iterative radar calibration loops of Yin with the direct voltage and DAC bias-current optimization architecture of Marr. The motivation for this combination is to minimize unnecessary power dissipation and improve the thermal efficiency of the radar's power amplifier. Therefore,
Regarding Claim 2: Yin details an iterative loop that checks a detector signal against a threshold, updating and subsequently storing a digital control code once a match is achieved (Fig. 5, 506-512; [0059]-[0061]). Applying this algorithmic approach to Marr's supply voltage control (Fig. 8C; [0348]) satisfies all limitations of this claim.
Regarding Claims 3, 14, & 18: These claims require a Low Drop-Out (LDO) voltage regulator receiving sequenced codes, beginning from a minimum value. Marr discloses using power distributors and sequencers to regulate voltages for amplifier components (Fig. 1, 105, 108; [0304]). Furthermore, Yin discloses reversing the calibration loop to start at a minimum value and increment upwards ([0062]). Utilizing an LDO (a highly standard voltage regulator) as the specific regulatory component represents a routine design choice.
Regarding Claim 5: Requires an iterative search algorithm stepping up and down. Marr discloses making "10 mV adjustments above and below the pre-programmed voltage... until the optimal voltage is achieved" ([0360]).
Claims 6, 15, & 19: Require applying DAC codes via a binary search algorithm using an IDAC. Marr teaches employing a DAC to supply and tune gate bias voltages and currents (Fig. 4A, 413; [0315]-[0317]). While the exact phrase "binary search" is absent from the references, executing the sequential search taught by Yin (Fig. 5; [0058]-[0062]) as a binary search is a standard, predictable software optimization in digital electronics implemented to reduce calibration execution time.
Claim 12: Yin explicitly shows a "peak-to-peak detector (PPD) 214" connected to the coupled port of a "coupler 212" at the "output terminals 211 of power amplifier 210" (Fig. 2; [0022]-[0024]).
Claim 17: Requires minimizing the sum of the magnitudes of the bias currents while maintaining target power. Marr explains that optimizing the calibration set points via the smart slave modules minimizes quiescent and leakage currents, thereby maximizing overall power efficiency (Fig. 8C; [0006], [0315], [0343], [0360]).
Claims 4, 7, 8, 9, 10, 11, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of Marr, and further in view of Bowers (US 2014/0354350).
Regarding the base system and calibration methods (Claims 7, 9, 10, and 11): Yin discloses a system for a vehicle radar subsystem (Title; Fig. 1) comprising a power amplifier (210) generating an output signal, a detector (peak-to-peak detector 214) producing a detector signal corresponding to the power level, and a controller (ARM7 block 208 / ISM 206) (Yin [0022]-[0024], [0047]). Yin further discloses executing a calibration routine using a digital-to-analog converter (DAC 230) receiving a control signal (digital threshold value / DAC code) that is sequentially arranged (iteratively incremented or decremented) to test and calibrate the system until a target power threshold is met (Yin [0057]-[0063]; Claim 7). Furthermore, Yin discloses using registers/memory (276) to store these calibrated sets of values (Yin [0047]).
Marr discloses an adaptive power management system for high-frequency RF power amplifiers that precisely adjusts supply voltages and biasing currents to optimize figures of merit like target output power and power efficiency (Marr [0364]-[0370]). Marr teaches using a controller and memory (202) storing lookup tables (LUT 206) for various control signal values (Claim 11). Marr further teaches sequentially modulating/testing bias and supply voltages to determine calibrated magnitudes that yield optimal amplifier efficiency at a target RF output power (Marr [0330]-[0340]; Claim 9).
While Yin and Marr do not explicitly state the use of a "binary search algorithm" (Claim 10) by name, optimizing an array of values in a digital controller using standard search algorithms (such as sequential stepping or binary search) to quickly lock onto a calibrated DAC code is a well-known, ordinary engineering choice in firmware design that yields predictable results.
It would have been obvious to a person of ordinary skill in the art at the time of the invention to integrate the adaptive biasing and supply-voltage optimization methods of Marr into the vehicle radar subsystem of Yin. The motivation would be to maximize the power efficiency and linearity of the radar's power amplifier across varying environmental conditions, as explicitly suggested by Marr (Marr [0339]-[0340]).
Regarding the cascoded transistor topology (Claims 4, 8, and 20): Neither Yin nor Marr explicitly detail the internal transistor-level topology of the RF power amplifier stages as being a cascoded configuration. However, Bowers discloses self-healing monolithic integrated high-frequency (mm-wave) RF circuits. Bowers explicitly teaches implementing power amplifier stages using a cascoded transistor topology consisting of a common-source transistor coupled to a common-gate (cascode) transistor (Bowers [0091], [0204]; Fig. 33C, noting the severing of "a common-source transistor and... a cascode transistor"). Furthermore, providing a cascode voltage generator tied to the main supply voltage to bias the common-gate device is an inherent and standard requirement for operating cascode amplifiers.
It would have been obvious to a person of ordinary skill in the art to implement the power amplifier stages of the Yin/Marr combination using the cascoded transistor topology of Bowers. The motivation for utilizing a cascode architecture in a high-frequency vehicle radar amplifier is to improve reverse isolation, increase voltage-handling capability, and enable dynamic self-healing/biasing techniques at mm-wave frequencies, as taught by Bowers (Bowers [0102], [0204]-[0205]).
The combination of Yin, Marr, and Bowers teaches all the limitations of the claims. One of ordinary skill would have readily combined Yin’s radar output power calibration, Marr’s adaptive biasing and supply voltage control logic, and Bowers's cascode PA topology to arrive at the claimed invention using known methods to yield a highly efficient, high-frequency vehicle radar system.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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