Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6-9, 12 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Ogihara et al (US 2024/0154857) (hereinafter Ogihara) in view of Uzawa et al (US 2024/0356825) (hereinafter Uzawa) and further in view of Canion et al (US 2013/0346628) (hereinafter Canion).
Regarding claim 1, Ogihara discloses a Radio Unit (RU) (e.g., Fig. 1, O-RU 20) comprising: a memory unit; a control unit, communicatively coupled with the memory unit, and a Programmable Logic (PL) unit (see Ogihara, p. [0016-0017], e.g., radio unit 20) configured to:
capture each of the plurality of data packets exchanged between the RU and the DU upon receiving a trigger command from the control unit (see Ogihara, Fig. 2, p. [0023], e.g., The protocol check circuit 11 also performs detection of an error in the control plane and the user plane transmitted and received to and from the radio unit 20 (e.g., O-RU) that performs radio frequency processing and the base band unit 30 (e.g., O-DU) that performs base band frequency processing);
determine a timestamp and a data size of each of the plurality of data packets (see Ogihara, Fig. 2, p. [0024], e.g., the order, the size, the format, and the parameter settings of the data are checked for normality. Then, in a case where the protocol check circuit 11 detects an error, it notifies the failure detection packet generation unit 12 of the error factor, the ether head of the control plane or the user plane in which the error has been detected, and the timestamp);
generate a data packet header corresponding to each of the plurality of data packets, wherein the data packet header comprises the timestamp and the data size of each of the plurality of data packets (see Ogihara, Fig. 3, p. [0029], e.g., the failure detection packet consists of an ether header unique to the failure detection packet, a packet header indicating that it is a failure detection packet, error information in which the error factor, the ether header of the plane in which the error has been detected, and timestamp information are stored); and
append the data packet header to each of the plurality of data packets and transmit each of the plurality of data packets to store in the memory unit (e.g., recording area 13), wherein the control unit is further configured to: retrieve each of the plurality of data packets stored in the memory unit according to the timestamp and the data size of each of the plurality of data packets (see Ogihara, Fig. 2, p. [0026], e.g., The failure detection packet generation unit 12 then records, in the recording area 13, the error factor information, the ether header of the control plane or the user plane in which the error has been detected and a timestamp, and p. [0031], e.g., the failure detection packet generation unit 12 sequentially records information such as the error factor on which the failure detection packet is based in the recording area 13, generates a failure detection packet based on the error factor information recorded in the recording area 13, and p. [0032]);
However, Ogihara does not expressly disclose generate a Packet Capture (PCAP) data file by converting each of the plurality of data packets into a PCAP format to validate the plurality of data packets exchanged between the RU and the DU.
Uzawa discloses the above recited limitations (see Uzawa, p. [0051], e.g., The captured file generation unit 23 of the normal capturing function unit 2 extracts the packets accumulated in the buffer unit 22 and converts them into a captured file in the pcap format (Step S304 in FIG. 4) when the file generation instruction signal is input form the capturing control unit 24 (YES in Step S302 in FIG. 4) and a file generation condition is satisfied (Step S303 in FIG. 4)).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Uzawa’s teachings into Ogihara. The suggestion/motivation would have been to convert the packets into a captured file in order to
register the conditions of the target flow designated by the instruction to start capturing in the first flow table and a second flow table of the second capturing function unit as suggested by Uzawa.
At paragraph [0016], Ogihara discloses each element/structural component illustrated in the drawings as a functional block that performs various processes can be composed of a CPU (Central Processing Unit), a memory, and other circuits in terms of hardware configuration, and can be realized by a program loaded in the memory. However, the combined teaching of Ogihara and Uzawa do not expressly disclose the memory is a Double Data Rate (DDR) memory unit.
Canion discloses that RAM 332 may be double data rate (DDR3) memory (see Canion, p. [0305].
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Canion’s teachings into the combined teachings of Ogihara and Uzawa. The suggestion/motivation would have been to use a DDR memory to increase the storage density as suggested by Canion.
Regarding claim 3, the combined teachings of Ogihara, Uzawa and Canion disclose the RU of claim 1, wherein the PL unit is further configured to: monitor a packet size of each of the plurality of data packets to prevent an overflow of the plurality of data packets (see Uzawa, p. [0044], e.g., the capturing control unit 24 of the normal capturing function unit 2 registers conditions of the capturing target flow in the flow table 20, and p. [0057], e.g., After the deletion from the flow table 20 is completed, the capturing control unit 24 outputs a file stop instruction signal to the captured file generation unit 23 of the normal capturing function unit 2 (Step S206 in FIG. 3)).
Regarding claim 6, the combined teachings of Ogihara, Uzawa and Canion disclose the RU of claim 1, wherein the trigger command comprises at least one of a total number of data packets to be captured by the PL unit, a capture duration and an indication to capture at least one of downlink data packets and uplink data packets (see Ogihara, p. [0024], e.g., the protocol check circuit 11 performs signal processing with respect to the control plane and the user plane using the configuration information indicated by the management plane).
Regarding claim 7, the combined teachings of Ogihara, Uzawa and Canion disclose the RU of claim 1, wherein the plurality of data packets includes one or more uplink data packets and one or more downlink data packets, wherein the one or more uplink data packets are stored in a first region of the DDR memory unit, which is different from a second region of the DDR memory unit used to store the one or more downlink data packets (see Canion, p. [0107], e.g., individual programmable logic units or clusters of such units may include memory blocks. Some configurable logic devices may include multiple arrangements of memory).
Regarding claim 8, the combined teachings of Ogihara, Uzawa and Canion disclose the RU of claim 1, wherein the control unit generates the PCAP data file by merging each of the one or more uplink data packets and each of the one or more downlink data packets according to the timestamp of each of the one or more uplink data packets and each of the one or more downlink data packets (see Ogihara, Fig. 3, p. [0026], [0029], e.g., the failure detection packet consists of an ether header unique to the failure detection packet, a packet header indicating that it is a failure detection packet, error information in which the error factor, the ether header of the plane in which the error has been detected, and timestamp information are stored, and p. [0031-0032]).
Regarding claim 9, Ogihara discloses a method comprising:
capturing, by a Programmable Logic (PL) unit configured in a Radio Unit (RU) (see Ogihara, e.g., radio unit 20), each of a plurality of data packets exchanged between the RU and a Distributed Unit (DU) connected to the RU, upon receiving a trigger command from a control unit of the RU (see Ogihara, Fig. 2, p. [0023], e.g., The protocol check circuit 11 also performs detection of an error in the control plane and the user plane transmitted and received to and from the radio unit 20 (e.g., O-RU) that performs radio frequency processing and the base band unit 30 (e.g., O-DU) that performs base band frequency processing);
determining, by the PL, a timestamp and a data size of each of the plurality of data packets (see Ogihara, Fig. 2, p. [0024], e.g., the order, the size, the format, and the parameter settings of the data are checked for normality. Then, in a case where the protocol check circuit 11 detects an error, it notifies the failure detection packet generation unit 12 of the error factor, the ether head of the control plane or the user plane in which the error has been detected, and the timestamp); generating, by the PL, a data packet header corresponding to each of the plurality of data packets, wherein the data packet header comprises the timestamp and the data size of each of the plurality of data packets (see Ogihara, Fig. 3, p. [0029], e.g., the failure detection packet consists of an ether header unique to the failure detection packet, a packet header indicating that it is a failure detection packet, error information in which the error factor, the ether header of the plane in which the error has been detected, and timestamp information are stored);
appending, by the PL, the data packet header to each of the plurality of data packets; transmitting, by the PL, each of the plurality of data packets, appended with the data packet header, to a memory unit (e.g., recording area 13) of the RU (see Ogihara, Fig. 2, p. [0026], e.g., the failure detection packet generation unit 12 then records, in the recording area 13, the error factor information, the ether header of the control plane or the user plane in which the error has been detected and a timestamp, and p. [0031], e.g., the failure detection packet generation unit 12 sequentially records information such as the error factor on which the failure detection packet is based in the recording area 13, generates a failure detection packet based on the error factor information recorded in the recording area 13, and p. [0032]);
However, Ogihara does not expressly disclose generating, by the control unit, a Packet Capture (PCAP) data file corresponding to the plurality of data packets by converting each of the plurality of data packets into a PCAP format for validating the plurality of data packets exchanged between the RU and the DU.
Uzawa discloses the above recited limitations (see Uzawa, p. [0051], e.g., The captured file generation unit 23 of the normal capturing function unit 2 extracts the packets accumulated in the buffer unit 22 and converts them into a captured file in the pcap format (Step S304 in FIG. 4) when the file generation instruction signal is input form the capturing control unit 24 (YES in Step S302 in FIG. 4) and a file generation condition is satisfied (Step S303 in FIG. 4)).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Uzawa’s teachings into Ogihara. The suggestion/motivation would have been to convert the packets into a captured file in order to
register the conditions of the target flow designated by the instruction to start capturing in the first flow table and a second flow table of the second capturing function unit as suggested by Uzawa.
At paragraph [0016], Ogihara discloses each element/structural component illustrated in the drawings as a functional block that performs various processes can be composed of a CPU (Central Processing Unit), a memory, and other circuits in terms of hardware configuration, and can be realized by a program loaded in the memory. However, the combined teaching of Ogihara and Uzawa do not expressly disclose the memory is a Double Data Rate (DDR) memory unit.
Canion discloses that RAM 332 may be double data rate (DDR3) memory (see Canion, p. [0305].
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Canion’s teachings into the combined teachings of Ogihara and Uzawa. The suggestion/motivation would have been to use a DDR memory to increase the storage density as suggested by Canion.
Regarding claim 12, the combined teachings of Ogihara, Uzawa and Canion disclose the method of claim 9, further comprises monitoring, by the PL unit, a packet size of each of the plurality of data packets to prevent an overflow of the plurality of data packets (see Uzawa, p. [0044], e.g., the capturing control unit 24 of the normal capturing function unit 2 registers conditions of the capturing target flow in the flow table 20, and p. [0057], e.g., After the deletion from the flow table 20 is completed, the capturing control unit 24 outputs a file stop instruction signal to the captured file generation unit 23 of the normal capturing function unit 2 (Step S206 in FIG. 3)).
Regarding claim 15, the combined teachings of Ogihara, Uzawa and Canion disclose the method of claim 9, wherein the trigger command comprises at least one of a total number of data packets to be captured by the PL unit, a capture duration and an indication to capture at least one of downlink data packets and uplink data packets (see Ogihara, p. [0024], e.g., the protocol check circuit 11 performs signal processing with respect to the control plane and the user plane using the configuration information indicated by the management plane).
Regarding claim 16, the combined teachings of Ogihara, Uzawa and Canion disclose the method of claim 9, wherein the plurality of data packets includes one or more uplink data packets and one or more downlink data packets, wherein the one or more uplink data packets are stored in a first region of the DDR memory unit, which is different from a second region of the DDR memory unit used to store the one or more downlink data packets (see Canion, p. [0107], e.g., individual programmable logic units or clusters of such units may include memory blocks. Some configurable logic devices may include multiple arrangements of memory).
Regarding claim 17, the combined teachings of Ogihara, Uzawa and Canion disclose the method of claim 9, wherein the PCAP data file is generated by merging each of the one or more uplink data packets and each of the one or more downlink data packets according to the timestamp of each of the one or more uplink data packets and each of the one or more downlink data packets (see Ogihara, Fig. 3, p. [0026], [0029], e.g., the failure detection packet consists of an ether header unique to the failure detection packet, a packet header indicating that it is a failure detection packet, error information in which the error factor, the ether header of the plane in which the error has been detected, and timestamp information are stored, and p. [0031-0032]).
Regarding claim 18, Ogihara discloses a non-transitory computer readable storage medium (see Ogihara, p. [0017]) including instructions stored thereon, that when processed by at least one processor, cause a Programmable Logic (PL) unit of a Radio Unit (RU) (e.g., radio unit 20) to perform operations comprising: capturing each of a plurality of data packets exchanged between the RU and a Distributed Unit (DU) connected to the RU, upon receiving a trigger command from a control unit of the RU (see Ogihara, Fig. 2, p. [0023], e.g., The protocol check circuit 11 also performs detection of an error in the control plane and the user plane transmitted and received to and from the radio unit 20 (e.g., O-RU) that performs radio frequency processing and the base band unit 30 (e.g., O-DU) that performs base band frequency processing); determining a timestamp and a data size of each of the plurality of data packets (see Ogihara, Fig. 2, p. [0024], e.g., the order, the size, the format, and the parameter settings of the data are checked for normality. Then, in a case where the protocol check circuit 11 detects an error, it notifies the failure detection packet generation unit 12 of the error factor, the ether head of the control plane or the user plane in which the error has been detected, and the timestamp); generating a data packet header corresponding to each of the plurality of data packets, wherein the data packet header comprises the timestamp and the data size of each of the plurality of data packets (see Ogihara, Fig. 3, p. [0029], e.g., the failure detection packet consists of an ether header unique to the failure detection packet, a packet header indicating that it is a failure detection packet, error information in which the error factor, the ether header of the plane in which the error has been detected, and timestamp information are stored); appending the data packet header to each of the plurality of data packets; transmitting each of the plurality of data packets, appended with the data packet header, to a memory unit of the RU (see Ogihara, Fig. 2, p. [0026], e.g., The failure detection packet generation unit 12 then records, in the recording area 13, the error factor information, the ether header of the control plane or the user plane in which the error has been detected and a timestamp, and p. [0031], e.g., the failure detection packet generation unit 12 sequentially records information such as the error factor on which the failure detection packet is based in the recording area 13, generates a failure detection packet based on the error factor information recorded in the recording area 13, and p. [0032]).
However, Ogihara does not expressly disclose generating a Packet Capture (PCAP) data file corresponding to the plurality of data packets by converting each of the plurality of data packets into a PCAP format for validating the plurality of data packets exchanged between the RU and the DU.
Uzawa discloses the above recited limitations (see Uzawa, p. [0051], e.g., The captured file generation unit 23 of the normal capturing function unit 2 extracts the packets accumulated in the buffer unit 22 and converts them into a captured file in the pcap format (Step S304 in FIG. 4) when the file generation instruction signal is input form the capturing control unit 24 (YES in Step S302 in FIG. 4) and a file generation condition is satisfied (Step S303 in FIG. 4)).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Uzawa’s teachings into Ogihara. The suggestion/motivation would have been to convert the packets into a captured file in order to
register the conditions of the target flow designated by the instruction to start capturing in the first flow table and a second flow table of the second capturing function unit as suggested by Uzawa.
At paragraph [0016], Ogihara discloses each element/structural component illustrated in the drawings as a functional block that performs various processes can be composed of a CPU (Central Processing Unit), a memory, and other circuits in terms of hardware configuration, and can be realized by a program loaded in the memory. However, the combined teaching of Ogihara and Uzawa do not expressly disclose the memory is a Double Data Rate (DDR) memory unit.
Canion discloses that RAM 332 may be double data rate (DDR3) memory (see Canion, p. [0305].
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Canion’s teachings into the combined teachings of Ogihara and Uzawa. The suggestion/motivation would have been to use a DDR memory to increase the storage density as suggested by Canion.
Claims 5, 10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over the combined teachings of Ogihara, Uzawa and Canion as applied to claims 1, 3, 6-9, 12 and 15-18 above, and further in view of Liu et al (US 2022/0222115) (hereinafter Liu).
Regarding claim 5, the combined teachings of Ogihara, Uzawa, Canion disclose the DDR memory (see Canion, p. [0305]). However, the combined teachings of Ogihara, Uzawa, Canion do not expressly disclose the RU of claim 1, wherein the predefined size of the memory region reserved on the DDR memory unit is determined based on bandwidth of a communication channel established between the RU and the DU.
Liu discloses the above recited limitations (see Liu, p. [0013], e.g., Liu discloses a High Bandwidth Memory (HBM) resource, which is a special memory resource that supports memory bandwidth-intensive workloads of an operating system executing on the computing device, and Fig. 4B, p. [0039], e.g., step 412, a region of a predefined size of the HBM is selected).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Liu’s teachings into the combined teachings of Ogihara, Uzawa, Canion. The suggestion/motivation would have been to provide HBM as available memory as suggested by Liu.
Regarding claim 10, the combined teachings of Ogihara, Uzawa, Canion and Liu disclose the method of claim 9, further comprises reserving, by the control unit, a memory region of predefined size on the DDR memory unit to store the plurality of data packets exchanged between the RU and the DU (see Liu, p. [0013], e.g., Liu discloses a High Bandwidth Memory (HBM) resource, which is a special memory resource that supports memory bandwidth-intensive workloads of an operating system executing on the computing device, and Fig. 4B, p. [0039], e.g., step 412, a region of a predefined size of the HBM is selected).
Regarding claim 14, the combined teachings of Ogihara, Uzawa, Canion and Liu disclose the method of claim 9, wherein the predefined size of the memory region reserved on the DDR memory unit is determined based on bandwidth of a communication channel established between the RU and the DU(see Liu, p. [0013], e.g., Liu discloses a High Bandwidth Memory (HBM) resource, which is a special memory resource that supports memory bandwidth-intensive workloads of an operating system executing on the computing device, and Fig. 4B, p. [0039], e.g., step 412, a region of a predefined size of the HBM is selected).
Allowable Subject Matter
Claims 2, 4, 11, 13 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MINH TRANG T NGUYEN whose telephone number is (571)270-5248. The examiner can normally be reached M-F 8:30am-6:00pm.
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/MINH TRANG T NGUYEN/Primary Examiner, Art Unit 2477