Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-3, 13, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over KUNZ et al. Pub. No. US 2022/0342838 A1 (hereafter KUNZ) in view of Xu et al. Pub. No. US 2025/0224723 A1 (hereafter Xu).
4. Examiner notes that Xu has priority to a provisional application filed on January 4th, 2024.
5. Regarding claim 1, KUNZ teaches “A system, comprising a network device application-specific integrated circuit (ASIC) ([0005-0010] teaches a network switch including various controllers, [0081] implies that controllers may be part of an ASIC to provide functionality such that the network switch may implement an ASIC including the controllers), which includes: a microcontroller to provide a command to a hardware accelerator to perform a job including gathering telemetry data from at least one hardware unit and write the gathered telemetry data to a memory ([0005] teaches an endpoint controller receiving a descriptor, the descriptor containing an address of the buffer in host memory, and then sending the address to a DMA controller in order to independently control data transfer from a network device to the indicated address); and the hardware accelerator to gather the telemetry data from the at least one hardware unit and write the gathered telemetry data to the memory … ([0015] teaches transferring data from a medium access control device connected to the switch via ethernet switch; [0036-0040] teach the DMA controller receiving data from the hardware units such as the ethernet switch, MAC receivers, [0048] teaches the ethernet switch including registers, TCAM, ingress port, egress port, FIFO buffers, etc.)”.
KUNZ does not explicitly teach the endpoint controller issuing a command to the DMA.
Xu teaches a command for a parameter monitor circuitry to receive the requested parameter data such that it teaches the limitation “the hardware accelerator to gather the telemetry data from the at least one hardware unit and write the gathered telemetry data to the memory based on the command ([0027-0028] teaches receiving a JSON input file containing instructions/commands to read data from field devices, the command forwarded to field controllers)”.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of Xu to the invention of KUNZ for including instructions in the descriptor sent from the host to the endpoint controller, to then command the DMA controller to collect data from the specified locations. A person having ordinary skill in the art would have been motivated to make this combination in order to facilitate constant data transfer without the need of multiple requests from a client, reducing usage of network resources (Xu [0041]). Together, Xu in combination with KUNZ teach every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
6. Regarding claim 23, it is similar to claim 1 and is rejected for similar reasons. Claim 23 is directed towards a “method (KUNZ [0014-0019])”.
7. Regarding claim 2, wherein the combination, KUNZ teaches “The system according to claim 1, wherein the network device ASIC includes the at least one hardware unit ([0048-0049] teaches the ethernet switch containing ports, buffers, TCAM, and registers).”
8. Regarding claim 3, wherein the combination, KUNZ teaches “The system according to claim 2, wherein the at least one hardware unit includes ports, buffers, and packet processing circuitry ([0048-0049]).”
9. Regarding claim 13, the combination does not explicitly teach a hardware accelerator sampling telemetry data including a timestamp. “The system according to claim 1, wherein the hardware accelerator is to sample the telemetry data from the at least one hardware unit so that each sample includes a timestamp and values gathered from the at least one hardware unit. (Xu [0071-0077] teaches a parameter change detection poller circuitry that may poll over an interval of time (see [0041]) for any changes from field devices, and upon detecting a change, it records the change and the timestamp associated with that change; in this case, the poller only records changes into the database, however each time polling occurs, a timestamp and data value would be available in the case of a data change, such that if configured, every polling query that occurs may be recorded if a change occurs within every poll)”.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to configure the DMA of KUNZ with the polling system taught by Xu to periodically poll and collect telemetry samples. A person having ordinary skill in the art would have been motivated to make this combination in order to reduce usage of network resources, not needing to receive multiple requests from a client device (Xu [0041]). Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
10. Claims 4-6, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over KUNZ and Xu as applied to claim 1 above, and in further view of CHIU Pub. No. US 2024/0202112 A1.
11. Regarding claim 4, the combination teaches “The system according to claim 1, wherein the microcontroller is … to provide the command to the hardware accelerator to perform the job including gathering the telemetry data from the at least one hardware unit and write the gathered telemetry data to the memory (KUNZ [0014] teaches the endpoint controller receiving the descriptor from the host, and then forwarding it to the DMA controller. Xu [0027] teaches the client sending a request to a parameter monitor circuitry, the request containing commands such as read/write/view, such that the descriptor of KUNZ should also contain a command in order to facilitate the data transfer by the DMA controller from a hardware unit(s) as taught in KUNZ [0060]).”
The combination does teach of IP routing firmware (KUNZ [0034]) however does not explicitly teach using the firmware to execute the commands.
CHIU teaches a microcontroller receiving commands from the host and using firmware to execute the host commands, instructing the DMA to move data such that it teaches the limitation “the microcontroller is to execute firmware to provide the command to the hardware accelerator to perform the job ([0023-0024] teaches a processing unit, the processing unit being implemented as a microcontroller that is programmed using firmware to execute host commands, the DMA controller receiving the instructions issued by the processing unit to carry out the job as specified by the command).”
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of CHIU to the combination of KUNZ and Xu to employ firmware executed by the endpoint controller to provide the command to the DMA. A person having ordinary skill in the art would have been motivated to make this combination in order to achieve faster sampling of telemetry data without continuous polling/requests from the host processor, offloading processor overhead. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
12. Regarding claim 5, wherein the combination, KUNZ teaches “The system according to claim 1, wherein the hardware accelerator is to gather the telemetry data from the at least one hardware unit and write the gathered data to a host memory of a host device connected to the network device via a data communication bus. ([0038] teaches a data bus used to transfer data from and to host memory wherein the DMA controller may utilize it to transfer data).”
13. Regarding claim 6, the combination teaches “The system according to claim 5, wherein the microcontroller is to receive a request from software executed by a central processing unit (CPU) of the host device to gather the telemetry data (KUNZ [0035] teaches host controllers implemented as a central processor, the host controller including a device driver, the device driver generating a descriptor and sending it to the endpoint controller, wherein the descriptor may contain instructions from a client request, to read device data as taught in Xu [0027]), and in response to receiving the request provide the command to the hardware accelerator to perform the job (CHIU [0024] teaches receiving the instructions issued by the processing unit, for carrying out the job of migrating the data as specified)”.
14. Regarding claim 8, the combination teaches “The system according to claim 1, further comprising a host device including: a host memory; and a CPU to execute software to provide a request to the microcontroller to gather the telemetry data and write the gathered telemetry data to the host memory (KUNZ [0035-0038] teaches a host system including host controllers that include a device driver implemented at the host controllers, the host controllers implemented as central processors. The device driver configures the host memory and network switch for transfer of data between the switch and the host memory. The device driver is also responsible for generating descriptors (requests) to the switch, received by an endpoint controller to carry out the descriptor task. It also teaches a host memory), wherein: the microcontroller is to, in response to receiving the request, provide the command to the hardware accelerator to perform the job; and the hardware accelerator is to gather the telemetry data from the at least one hardware unit and write the gathered telemetry data to the host memory (KUNZ [0005] teaches the endpoint controller receiving the descriptor and forwarding its address to the DMA controller; CHIU [0023-0024] teaches the DMA controller carrying out the instruction issued by the processing unit (which may be implemented as a microcontroller as described in CHIU [0023]) and begins migrating data from hardware units to a specific data buffer of the host)”.
15. Regarding claim 10, wherein the combination, KUNZ teaches “The system according to claim 1, wherein network device is a network switch ([0035]), and the hardware units include switching circuitry ([0047] teaches ethernet switch with TCAM controller and MAC transmitter).”
16. Regarding claim 11, wherein the combination, KUNZ teaches “The system according to claim 1, wherein the hardware accelerator includes a direct memory access (DMA) hardware accelerator ([0032] teaches of DMA controllers)”.
17. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over KUNZ and Xu as applied to claims 1 and 13 above, and in further view of SOOD et al. Pub. No. US 2023/0353508 A1 (hereafter SOOD).
18. Regarding claim 12, the combination does not explicitly teach a sampling rate of faster than 1 millisecond.
SOOD teaches a telemetry sampling at a rate on the order of a few microseconds such that it teaches the limitation “The system according to claim 1, wherein the hardware accelerator is to sample the telemetry data from the at least one hardware unit at a rate faster than every millisecond ([0036])”.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of SOOD to the combination of KUNZ, and Xu to configure the sampling rate to be faster than a millisecond. A person having ordinary skill in the art would have been motivated to make this combination in order manage bursts of received packet traffic (SOOD [0049-0052]). Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
19. Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over KUNZ and Xu as applied to claim 1 above, and in further view of Dong et al. Pub. No. US 2022/0114440 A1 (hereafter Dong).
20. Regarding claim 14, the combination does not explicitly teach of maintaining counter values of telemetry data.
Dong teaches of hardware performance counters such that it teaches the limitation “The system according to claim 1, wherein the gathered telemetry data includes any one or more of the following: counter values maintained by the at least one hardware unit; values from histograms; and temperature values ([0055] teaches of a hardware TPU performance recording a number of packets successfully received at each channel of a port of a TPU).”
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of Dong to the combination of KUNZ and Xu to collect performance counter data to memory. A person having ordinary skill in the art would have been motivated to make this combination in order to monitor performance and create historical telemetry data for future planning. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
21. Regarding claim 15, wherein the combination, Dong teaches “The system according to claim 14, wherein the counter values provide an indication of any one or more of the following: a number of packets transmitted and/or received; a number of bytes transmitted and/or received; buffer occupancy for a given one of the ports for a given one of the buffers or a priority on the given port; and a number of pause frames transmitted and/or received; and a number of inbound packets chosen to be discarded ([0055] teaches the counter recording the number of packets received at each port of a TPU)”.
22. Claims 7, 9, 16-19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over KUNZ, Xu and CHIU as applied to claims 6 and 8 above, and in further view of Wang et al. Pub. No. US 2024/0419617 A1 (hereafter Wang).
23. Regarding claim 7, the combination does not explicitly teach of providing an indication of completion upon completing a job.
Wang teaches the DMA generating a completion notification such that it teaches the limitation “The system according to claim 6, wherein: the hardware accelerator is to provide an indication to the microcontroller when the hardware accelerator completes the job gathering the telemetry data; and the microcontroller is to provide a notification to the software executed by the CPU that the job has been completed ([0046] teaches the DMA status source generating a moving completion notification after executing the descriptors/commands, and sends the notification to a status sink such that the control register knows the status, wherein a DMA descriptor controller may then update the target status table corresponding to a target descriptor, the descriptor containing address information such that it may be a host memory buffer address, implying completion to the host)”.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of Wang to the combination of KUNZ, Xu, and CHIU to implement a notification system upon completion of a job. A person having ordinary skill in the art would have been motivated to make this combination in order to determine the execution condition of each descriptor in order to carry out subsequent operations if required, allowing for the digital circuit to continuously read and write data, increasing efficiency (Wang [0035]). Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
24. Regarding claim 9, it is similar to claim 7 and is rejected for the same reasons.
25. Regarding claim 16, it is similar to claim 7 and is rejected for the same reasons.
26. Regarding claim 17, the combination teaches “The system according to claim 16, wherein the command for the job indicates the at least one hardware unit (KUNZ [0043] teaches the descriptor containing source addresses such that it identifies a hardware unit) and timing data including any one or more of the following: a duration of the job; a number of samples to be taken; a sampling frequency; or a time gap between each of the samples (Xu [0107-0111] teaches a time interval representing how often polling should occur as well as a delay value)”.
27. Regarding claim 18, it is similar to that of claim 17 and is rejected for the same reasons.
28. Regarding claim 19, the combination teaches “The system according to claim 18, wherein the job has a fixed duration defined by the timing data including a duration of the job or a number of samples to be taken (Xu [0107-0111] teaches a time interval such that it defines the window of polling)”.
29. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over KUNZ, Xu, CHIU, and Wang as applied to claim 18 above, and in further view of Niu et al. Pub. No. US 2022/0217098 A1 (hereafter Niu).
30. Regarding claim 20, the combination does not explicitly teach of using ring buffers.
Niu teaches writing to a ring buffer such that it teaches the limitation “The system according to claim 18, wherein the command for the job indicates that the telemetry data is to be written to a ring buffer in the memory ([0081] teaches a command issued from a device, the device including a ring buffer dedicated for storing a data stream to be transmitted; [0043-0044] teaches the command indicating the data to be written into the ring buffer)”.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of Niu to the combination of KUNZ, Xu, CHIU, and Wang to implement a ring buffer, and command telemetry data be written to the ring buffer. A person having ordinary skill in the art would have been motivated to make this combination in order to facilitate continuous data, reducing computing overhead and may support faster data transmission (Niu [0048]). Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
31. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over KUNZ, Xu, CHIU, and Wang as applied to claim 18 above, and in further view of MOYER et al. Pub. No. US 2016/0292027 A1 (hereafter Moyer).
32. Regarding claim 21, the combination does not explicitly teach issuing a terminate command from the host.
Moyer teaches of task termination logic such that it teaches the limitation “The system according to claim 18, wherein the microcontroller is to: receive a request from software executed by a CPU of a host device that the job should be terminated; and provide a command to the hardware accelerator to terminate the job ([0022] teaches a request from the CPU to terminate a task via a termination command)”.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of Moyer to the combination of KUNZ, Xu, CHIU, and Wang, to implement termination logic. A person having ordinary skill in the art would have been motivated to make this combination in order terminate a job once a condition is met, reducing unnecessary resource consumption. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
33. Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over KUNZ and Xu as applied to claim 1 above, and in further view of Narad Pub. No. US 2012/0059956 A1.
34. Regarding claim 22, the combination does not explicitly teach clearing the hardware unit upon gathering the telemetry data. Narad teaches zeroing counters after transferring statistics such that it teaches the limitation “The system according to claim 1, wherein the hardware accelerator is to clear the telemetry data from the at least one hardware unit upon gathering the telemetry data ([0022] teaches the interface configured to zero the counters after statistics are transferred to memory such that the hardware unit is cleared after gathering and writing to memory).”
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of Narad to the combination of KUNZ, and Xu, configure the accelerator to clear hardware counter after gathering data. A person having ordinary skill in the art would have been motivated to make this combination in order to accurately gather information during each polling interval and to prevent counter wrap-around (Narad [0022]). Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
Conclusion
35. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON A NGUYEN whose telephone number is (571)272-6074. The examiner can normally be reached Mon-Fri (10am-6pm).
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/BRANDON NGUYEN/Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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