DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-3, 7, 9, 11, and 17-19 are pending in this application. Claims 4-6, 8, are withdrawn
Election/Restrictions
Claims 4-6, 8, 12-16, and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species 2-8, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/29/26. Additionally, examiner withdraws claim 10 as being drawn to a nonelected Species 2-8 characterized in having a control and power stage 202 comprising a linear regulator power stage.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 09/09/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on 03/18/24. These drawings are not acceptable.
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, 9, 11, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (US 9768676 B1) hereinafter Shen and further in view of Gerritsen (US 20080315849 A1).
Regarding claim 1 and 17, Shen discloses a low-noise voltage regulator and method for controlling the low-noise voltage regulator (fig. 3, switching power regulator circuit including a current-mode controlled Boost converter 300; col 2 lines 8-9 “frequency noise can be filtered to allow for tight output voltage regulation”), comprising: an error amplifier (fig. 3, error amplifier 320) configured to generate an error signal that is proportional to a difference between a voltage at a ground node (fig 3. V.sub.ref; col 3 lines 32-34 “The reference voltage V.sub.Ref may be any suitable fixed value of the switching power regulator circuit 100”, examiner interprets that ground as a zero voltage reference point is a suitable reference and well known in the art to use ground as it serves as a zero voltage reference point when comparing difference in voltage measurements) and a voltage at a set node (fig 3, junction point between capacitor C.sub.ff and mid point between R.sub.f1 and R.sub.f2); a reference resistor (fig 3, feedback resistor values R.sub.f1) electrically coupled between an output power node (fig 3, output node 308) and the set node (fig 3, R.sub.f1 is coupled between junction point between capacitor C.sub.ff and mid point between R.sub.f1 and R.sub.f2 and output node 308); a reference current source (fig 3, current source 112); and a control and power stage electrically coupled between an input power node and the output power node (fig 3, current-mode controlled Boost power converter 302 is operatively intermediate an input node 306 and an output node 308), the control and power stage being configured to convert an input voltage to an output voltage in response to the error signal to minimize a magnitude of the error signal (implicit of a switching regulator shown in fig 3, designed to maintain a stable output voltage through a feedback control loop utilizing the error amplifier (320) to compare a portion of the output voltage (V_out) against a reference voltage (V_Ref or ground) to generate an error signal then the error signal is processed by the control circuitry (304) along with current sensing (322) and a clock signal (326) to modulate the switching pulse for the power stage (302) to respond by adjusting the duty cycle of the switch (360). This continuously adjusts the power delivery to minimize the error signal, effectively keeping the output voltage at the desired setpoint) the input voltage being a voltage at the input power node and the output voltage being a voltage at the output power node (fig 3, 306 V.sub.in and 308 V.sub.out).
Gerritsen discloses a power converter with feedback loop and has the concern of output voltage ripple with conventional design of using a voltage divider. Gerritsen instead utilizes a current reference source to pulled down the current through the resistor to a set node for a constant voltage drop identical to what is described in the instant application. Gerritsen discloses a reference current source (fig 8, Current reference source 528) electrically coupled to the set node (fig 8, internal node 523).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Shen and incorporate the use of a reference current source (in place of Shen’s R12) coupled to a node intended as a voltage drop for input to an error amplifier as taught by Gerritsen. The advantage of this design is to pull the current down through the resistor to ensure an accurate measurement of the output voltage without utilizing a fractional voltage divider.
Regarding claim 2 and 18, Shen and Gerritsen disclose the low-noise voltage regulator of claim 1 and method of filtering noise of claim 17, further comprising a reference capacitor electrically coupled in parallel with the reference resistor (Shen fig 3, feedforward capacitor C.sub.ff in parallel to R11) filtering noise across the reference resistor (Shen col 2 lines 8-9 “noise can be filtered to allow for tight output voltage regulation”).
Regarding claim 3, Shen and Gerritsen disclose the low-noise voltage regulator of claim 1, wherein: a first input port of the error amplifier is connected to the set node (Shen fig 3, node at the junction between – input to error amplifier 120 and C.sub.ff; Gerritsen fig 8, node 523 as first input to 222); and a second input port of the error amplifier is connected to the ground node (Shen fig 3. V.sub.ref is connected to + input of error amplifier 120; col 3 lines 32-34 “The reference voltage V.sub.Ref may be any suitable fixed value of the switching power regulator circuit 100”, examiner interprets that ground as a zero voltage reference point is a suitable reference and well known in the art to use ground as it serves as a zero voltage reference point when comparing difference in voltage measurements; Gerritsen fig 8, Vref 225 to second input of 222, it is a well-known and standard practice in electrical engineering to utilize Ground (or 0V reference) tied directly to one of the error amplifier inputs, particularly in single-supply control ICs, to create a fixed comparison point for a feedback voltage).
Regarding claim 7, Shen and Gerritsen disclose the low-noise voltage regulator of claim 1, wherein the reference current source is configured to generate a reference current signal that flows away from the set node, such that the output voltage is positive with respect to the ground node (Gerritsen fig 8, the arrow for current source 528 points downward, confirming that the reference current flows away from the sensing/set node 523 and into the ground rail 816. Because current is pulled down through resistor 527, node 817 is held at a higher potential than node 523, causing Vout to be strictly positive with respect to the ground rail 816).
Regarding claim 9, Shen and Gerritsen disclose the low-noise voltage regulator of claim 1, wherein the control and power stage comprises a switching power converter power stage (Gerritsen fig 8, par [0002] switched-mode power supply; Shen fig 3, 300 switching power regulator circuit including a current-mode controlled Boost converter).
Regarding claim 11, Shen and Gerritsen disclose low-noise voltage regulator of claim 1, wherein the low-noise voltage regulator has a boost topology (Gerritsen fig 8, par [0043] “so-called up-converter”; Shen fig 3, 300 switching power regulator circuit including a current-mode controlled Boost converter).
Regarding claim 18, Shen and Gerritsen disclose the method of claim 17, wherein establishing the voltage having the first magnitude across the reference resistor comprises applying a reference current signal to the reference resistor (Gerritsen fig 8, the arrow for current source 528 points downward, confirming that the reference current flows away from the sensing/set node 523 and into the ground rail 816 and current is pulled down through resistor 527).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hastings et al. (US 5600234 A) discloses capacitor 104 of fig 3 is is intended solely as a noise suppression component in the feedback circuit 78
Stanescu et al. (US 6518737 B1) A first frequency compensation capacitor 106 in FIG. 2 is placed in parallel with the upper resistor 30 of the voltage divider (R130 and R232). The capacitor 106 and the voltage divider (upper resistor 30 and lower resistor 32) in FIG. 2 provide a zero-pole pair, which enhances the phase margin (close to unity-loop-gain frequency) at a high load current
Mannama et al. (US 7919954 B1) LDO With Output Noise Filter capacitor CF
Stik et al. (US 8289009 B1) Low Dropout (LDO) Regulator With Ultra-low Quiescent Current
Joshi et al. (US 11782468 B2) Current-mode Feedforward Ripple Cancellation
Wang (US 20080169795 A1) LDO regulator with error amplifier with one input from ground and another from parallel RC
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren A Shaw whose telephone number is (571)272-3074. The examiner can normally be reached Mon-Fri 7-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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