DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This Action is in response to communications filed 12/23/2025.
Claims 1-2 and 10 have been amended.
Claims 1-20 are pending.
Claims 1-20 are rejected.
The Examiner notes the current action does not include prior art rejections over the current presentation of the claims. The cited relevant prior art references made of record below are considered as pertinent to the claims and disclosed details provided in the Specification.
The claims are subject to the rejections provided herein which must be addressed accordingly.
Response to Amendment
In the Remarks filed 12/23/2025, Applicant has amended:
The language of claim 1 to revert prior amendments of record and import the detail of the testing the memory cells through the storage of a proof of space plot and evaluation of the validity of response from claim 2. The Examiner therefore withdraws the 112(b) rejection made in the Office action dated 09/24/2025. Furthermore, in view of the amendments which revert the scope of the claims to the previously presented form as filed in the response filed 02/03/2025, the Examiner withdraws the 103 rejections made in the Office action dated 09/24/2025.
The language of claim 10 to remove the redundant language subject to the previous objection of record. The Examiner therefore withdraws the objection made in the Office action dated 09/24/2025.
Response to Arguments
In Remarks filed on 12/23/2025, Applicant substantially argues:
On Page 1, the Applicant acknowledges the double patenting rejections and requests the rejections as being held in abeyance until currently amended claims are indicated as allowable over the prior art of record. The Examiner has previously made of record and repeats herein that MPEP 804(I)(1) recites “[a]s filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only compliance with objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Replies with an omission should be treated as provided in MPEP § 714.03. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner.” For purposes of compact prosecution, the most recent filed response is considered. The following rejections herein are in response to Applicant’s amendments.
All arguments by the applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated December 23, 2025.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,941,254, hereinafter referred to as “Patent”. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are of a broader recitation of those in the US Patent as demonstrated by the comparison below. In this manner, it may be considered that the claims of the US Patent may anticipate the claims of the instant application as they are of narrower scope.
Instant Application
US Patent 11,941,254
A device, comprising: memory cells; and a circuit configured to test the memory cells through storing a proof of space plot in the memory cells and evaluating validity of responses.
A method, comprising: writing a proof of space plot into memory cells of a memory sub-system; generating a plurality of random challenges of proof of space; generating, using the proof of space plot stored in the memory cells, a plurality of responses to the plurality of random challenges respectively; and determining validity of the plurality of responses.
The device of claim 1, further comprising: a host interface operable to receive, from a host system, commands to read data from the memory cells and commands to write data to the memory cells.
The method of claim 1, further comprising: storing, in the memory sub-system, validation data, wherein the determining of the validity of the plurality of responses is performed by the memory sub-system using the validation data.
The device of claim 2, wherein the memory cells are configured on at least one integrated circuit die; and the circuit includes a processor configured via firmware to test the memory cells; and wherein the responses are generated used the proof of space plot stored in the memory cells, to proof of space challenges.
The method of claim 2, wherein the plurality of random challenges are generated within the memory sub-system.
The device of claim 3, wherein the firmware is configured to instruct the processor to: generate randomly the proof of space challenges; generate, using the proof of space plot stored in the memory cells, the responses; determine validity of the responses; and evaluate, based on the validity of the responses, health of the memory cells.
The method of claim 3, further comprising: identifying, by the memory sub-system, first memory cells being accessed during generation of the plurality of responses, wherein evaluating a health of the first memory cells is performed by the memory sub-system based at least in part on the identifying of the first memory cells.
The device of claim 4, wherein the firmware is configured to instruct the processor to: vary parameters used in reading the memory cells during generation of the responses; and identify parameters to read the memory cells based on the validity of the responses.
The method of claim 4, further comprising: varying parameters used in reading the first memory cells during generation of the plurality of responses; and identifying, from the parameters and based on the validity of the plurality of responses, parameters optimized to read the first memory cells.
The device of claim 4, wherein the firmware is configured to instruct the processor to: calibrate parameters used in reading the memory cells based on the validity of the responses.
The method of claim 5, further comprising: calibrating, periodically and prior to erasure of the proof of space plot to reclaim storage space occupied by the proof of space plot, read parameters of memory cells of the memory sub-system based on validating responses to random challenges of space occupied by the proof of space plot.
The device of claim 4, wherein the firmware is configured to instruct the processor to: read and write the memory cells according to computations for generation of the proof of space plot, while the device is disconnected from a host system.
The method of claim 4, further comprising: loading the memory sub-system on a production line in a manufacturing facility; connecting the memory sub-system to a host system on the production line; configuring, by the host system, the memory sub-system, to generate the random challenges and to determine the validity of the plurality of responses; and disconnecting the host system from the memory sub-system, wherein while being disconnected from the host system, the memory sub-system performs an autonomous self-test using the proof of space plot stored in the memory sub-system.
The device of claim 7, wherein the device is a solid-state drive; and the proof of space plot stored in the device as a by-product of testing the device on a production line.
The method of claim 7, further comprising: performing, while the memory sub-system on the production line, read and write operations according to computations for generation of the proof of space plot.
A method, comprising: storing, in memory cells of a device, a proof of space plot; and testing, via a circuit configured in the device, the memory cells.
The method of claim 7, further comprising: providing the memory sub-system as a product of the production line, with the proof of space plot stored in the memory sub-system as a by-product.
The method of claim 9, further comprising: receiving, via a host interface of the device and from a host system, commands to read data from the memory cells and commands to write data to the memory cells.
The method of claim 7, wherein the memory sub-system is a solid state drive having a host interface, memory cells formed on at least one integrated circuit, and a processing device configurable to function as an internal host to control the autonomous self-test.
The method of claim 10, wherein the memory cells are configured on at least one integrated circuit die; and the circuit includes a processor configured via firmware to test the memory cells; and wherein the responses are generated using the proof of space plot stored in the memory cells, to proof of space challenges.
A memory sub-system, comprising: a host interface operable to receive commands from a host system to read data from the memory sub-system and to write data to the memory sub-system; memory cells formed on at least one integrated circuit; and a processing device operable to control execution of the commands; wherein, after a proof of space plot is written into the memory cells, the memory sub-system is configured to: generate a plurality of random challenges of proof of space; generate, using the proof of space plot stored in the memory cells, a plurality of responses to the plurality of random challenges respectively; and determine validity of the plurality of responses.
The method of claim 11, further comprising: generating, randomly and via the processor running the firmware, the proof of space challenges; generating, using the proof of space plot stored in the memory cells, the responses; determining, validity of the responses; and evaluating, via the processor running the firmware and based on the validity of the responses, health of the memory cells.
The memory sub-system of claim 11, further configured to store validation data to determine the validity of the plurality of responses.
The method of claim 12, further comprising: varying parameters used in reading the memory cells during generation of the responses; and identifying parameters to read the memory cells based on the validity of the responses.
The memory sub-system of claim 12, further configured to identify first memory cells being accessed during generation of the plurality of responses, wherein a health of the first memory cells is evaluated based at least in part on identifications of the first memory cells.
The method of claim 12, further comprising: calibrating parameters used in reading the memory cells based on the validity of the responses.
The memory sub-system of claim 13, further configured to: vary parameters used in reading the first memory cells during generation of the plurality of responses; and identify, from the parameters and based on the validity of the plurality of responses, parameters optimized to read the first memory cells.
The method of claim 12, further comprising: reading and writing, while the device is disconnected from a host system, the memory cells according to computations for generation of the proof of space plot.
The memory sub-system of claim 14, further configured to calibrate, periodically and prior to erasure of the proof of space plot to reclaim storage space occupied by the proof of space plot, read parameters of memory cells of the memory sub-system based on validating responses to random challenges of space occupied by the proof of space plot.
A non-transitory computer storage medium storing instructions which, when executed in a device, cause the device to perform a method, comprising: testing, by a device having memory cells storing a proof of space plot, the memory cells through: generating using the proof of space plot stored in the memory cells responses to proof of space challenges.
The memory sub-system of claim 15, further configured to perform, while the memory sub-system is in a production line in a manufacturing facility but is disconnected from a host system on the production line, read and write operations according to computations for generation of the proof of space plot, while the memory sub-system is disconnected.
The non-transitory computer storage medium of claim 16, wherein the method further comprises: receiving, via a host interface of the device and from a host system, commands to read data from the memory cells and commands to write data to the memory cells.
The memory sub-system of claim 16, wherein the memory sub-system stores the proof of space plot as a by-product when the memory sub-system is provided as a product of the production line; the memory sub-system is a solid state drive; and the processing device is configurable to function as an internal host to control an autonomous self-test of health of memory sub-system using the proof of space plot.
The non-transitory computer storage medium of claim 17, further comprising: generating, randomly and via a processor of the device executing the instructions, the proof of space challenges; and evaluating, via the processor of the device executing the instructions and based on evaluating validity of the responses, health of the memory cells.
A non-transitory computer storage medium storing instructions which, when executed in a memory sub-system, cause the memory sub-system to perform a method, comprising: writing a proof of space plot into memory cells of the memory sub-system; generating a plurality of random challenges of proof of space; generating, using the proof of space plot stored in the memory cells, a plurality of responses to the plurality of random challenges respectively; and determining validity of the plurality of responses.
The non-transitory computer storage medium of claim 18, wherein the method further comprises: varying parameters used in reading the memory cells during generation of the responses; and identifying parameters to read the memory cells based on the validity of the responses.
The non-transitory computer storage medium of claim 18, wherein the method further comprises: varying parameters used in reading first memory cells during generation of the plurality of responses; and identifying, from the parameters and based on the validity of the plurality of responses, parameters optimized to read the first memory cells.
The non-transitory computer storage medium of claim 18, wherein the method further comprises: calibrating parameters used in reading the memory cells based on the validity of the responses.
The non-transitory computer storage medium of claim 19, wherein the method further comprises: calibrating, periodically and prior to erasure of the proof of space plot to reclaim storage space occupied by the proof of space plot, read parameters of memory cells of the memory sub-system based on validating responses to random challenges of space occupied by the proof of space plot.
Regarding claim 1, the claim of the instant application is substantially similar to that of Claim 11 of the Patent as noted by the unbolded portions of each claim in the table above. The bolded portions of claim 11 of the instant application and US Patent notes the differences and the US Patent thereby presenting a narrower scope establishes that the US Patent would otherwise anticipate the limitations of the instant application.
Regarding claim 2 of the instant application, the limitations are substantially identical to claim 11 of the Patent.
Regarding claim 3 of the instant application, the limitations are substantially identical to limitations of claim 11 of the Patent.
Regarding claim 4 of the instant application, the limitations are substantially identical to limitations of claim 11 and 13 of the Patent.
Regarding claim 5 of the instant application, the limitations are substantially identical to claim 14 of the Patent.
Regarding claim 6 of the instant application, the limitations are substantially identical to limitations of claim 15 of the Patent.
Regarding claim 7 of the instant application, the limitations are substantially identical to claim 16 of the Patent.
Regarding claim 8 of the instant application, the limitations are substantially identical to claim 17 of the Patent.
Regarding claim 9 of the instant application, the limitations are substantially identical to claim 1 of the Patent for similar as presented above for claim 1
Regarding claim 10 of the instant application, the limitations are substantially identical to limitations of claims 1 and 7 of the Patent.
Regarding claim 11 of the instant application, the limitations are substantially identical to limitations of claim 10 of the Patent
Regarding claim 12 of the instant application, the limitations are substantially identical to claims 1 through 4 of the Patent.
Regarding claim 13 of the instant application, the limitations are substantially identical to limitations of claim 5 of the Patent.
Regarding claim 14 of the instant application, the limitations are substantially identical to claim 6 of the Patent.
Regarding claim 15 of the instant application, the limitations are substantially identical to claim 8 of the Patent.
Regarding claim 16 of the instant application, the limitations are substantially identical to limitations of claim 18 of the Patent.
Regarding claim 17 of the instant application, the limitations are substantially identical to claim 7 of the Patent.
Regarding claim 18 of the instant application, the limitations are substantially identical to claim 4 of the Patent.
Regarding claim 19 of the instant application, the limitations are substantially identical to claim 19 of the Patent.
Regarding claim 20 of the instant application, the limitations are substantially identical to claim 20 of the Patent.
This is a nonstatutory double patenting rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Harms (US 2020/0265915) – Paragraph [0148] wherein testing a memory device is discussed.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER J YOON whose telephone number is (408)918-7629. The examiner can normally be reached on Monday-Friday 8am-3pm ET. The examiner’s email is alexander.yoon2@uspto.gov.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/ Supervisory Patent Examiner, Art Unit 2135