Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuzawa et al. (Pub NO. US 2011/0215959 A1; hereinafter Matsuzawa) in view of SUN et al. (Pub NO. US 2023/0160600 A1; hereinafter Sun).
Regarding claim 1, Matsuzawa teaches a speed signal converter circuit (Fig. 3-Fig. 4 and Fig. below) comprising:
an analog signal conditioning stage (20 in fig. 3 and Fig. below; See [0077]-[0083]) configured to determine a voltage of an input speed signal (output voltage of 20 is Vg1 and Vg2 determine speed of input signal speed signal Vi1 and Vi2 in fig. 3 and Fig. below; See [0077]-[0083]),
combine the voltage with an alternating current (AC) injection voltage signal (combine with AC injection CLK in fig, 3; See [0077]-[0083]) having a set frequency to generate a combined voltage signal (CLK has set frequency in Fig. 4), and
output a pulsed zero-crossing signal including a rising edge and a falling edge indicating a zero-crossing of the input speed signal based on the combined voltage signal (output of 20 is Vg1/Vg2 is zero crossing between +1 and -1 of combine signal vi1/vi2/CLK signal in fig. 4); and
a digital signal processing stage (10 in Fig. 3 ad Fig. below) in signal communication with the analog signal conditioning stage (10 is in communication with 20 in Fig. 3 and Fig. below),
the digital signal processing stage configured to determine a rising edge slope of the input speed signal and
a falling edge slope of the input signal based on a rising edge and a falling edge of the pulsed zero-crossing signal (output of 10 is Vo and Vo is based on rising edge slope and falling edge slope of Vg in Fig. 4; See [0090]-[0095]).
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Matsuzawa is silent about to determine an optimal edge among either the rising edge or the falling edge based on a comparison between the rising edge slope and the falling edge slope.
Sun teaches to determine an optimal edge among either the rising edge or the falling edge based on a comparison between the rising edge slope and the falling edge slope (satisfy slope comparison is optimal edge; See [0017], [0054], [0101]-[0103]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Matsuzawa by determine an optimal edge among either the rising edge or the falling edge based on a comparison between the rising edge slope and the falling edge slope, as taught by Sun in order to achieve screening voltage data (Sun; [0037]).
Regarding claim 2, Matsuzawa in view of Sun teaches the speed signal converter of claim 1. Sun further teaches wherein the digital signal processing stage determines whether the rising edge slope or the falling edge slope has a larger slope (ratio reflects the larger edge slope; See [0101]), and selects the rising edge or the falling edge associated with the larger slope as the optimal edge (edge can be selected by the ration; See [0101]).
Regarding claim 10, Matsuzawa teaches a method of processing an input speed signal (Fig. 3-Fig. 4 and Fig. below), the method comprising:
determining a voltage of an input speed signal (output voltage of 20 is Vg1 and Vg2 determine speed of input signal speed signal Vi1 and Vi2 in fig. 3 and Fig. below; See [0077]-[0083]);
combining the voltage with an alternating current (AC) injection voltage signal (combine with AC injection CLK in fig, 3; See [0077]-[0083]) having a set frequency to generate a combined voltage signal (CLK has set frequency in Fig. 4);
generating a pulsed zero-crossing signal including a rising edge and a falling edge that indicates a zero-crossing of the input speed signal based on the combined voltage signal (output of 20 is Vg1/Vg2 is zero crossing between +1 and -1 of combine signal vi1/vi2/CLK signal in fig. 4);
determining a rising edge slope of the input speed signal and a falling edge slope of the input signal based on a rising edge and a falling edge of the pulsed zero-crossing signal (output of 10 is Vo and Vo is based on rising edge slope and falling edge slope of Vg in Fig. 4; See [0090]-[0095]);
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Matsuzawa is silent about determining an optimal edge among either the rising edge or the falling edge based on a comparison between the rising edge slope and the falling edge slope.
Sun teaches to determine an optimal edge among either the rising edge or the falling edge based on a comparison between the rising edge slope and the falling edge slope (satisfy slope comparison is optimal edge; See [0017], [0054], [0101]-[0103]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Matsuzawa by determine an optimal edge among either the rising edge or the falling edge based on a comparison between the rising edge slope and the falling edge slope, as taught by Sun in order to achieve screening voltage data (Sun; [0037]).
Regarding claim 11, Matsuzawa in view of Sun teaches the method of claim 10, further comprising: determining whether the rising edge slope or the falling edge slope has a larger slope (ratio reflects the larger edge slope; See [0101]); and selecting the rising edge or the falling edge associated with the larger slope as the optimal edge (edge can be selected by the ration; See [0101]).
Allowable Subject Matter
Claims 3-9 and 12-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, none of the prior art fairly teaches or suggests the speed signal converter of claim 2, wherein the digital signal processing stage compares the optimal edge to an expected edge and detects a reverse wiring fault when the optimal edge does not match the expected edge.
Claims 4-9 depend on claim 3, therefore claims 4-9 also have allowable subject matter.
Regarding claim 12, none of the prior art fairly teaches or suggest the method of claim 11, further comprising: comparing the optimal edge to an expected edge; and detecting a reverse wiring fault when the optimal edge does not match the expected edge.
Claims 13-18 depend on claim 12, therefore claims 13-18 also have allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JIN et al. (Pub NO. US 2024/0015053 A1) discloses Decision Feedback Equalizer.
CAO et al. (Pub NO. US 2021/0376746 A1) discloses System and Method for Synchronous Rectification.
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/ZANNATUL FERDOUS/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858