Prosecution Insights
Last updated: August 16, 2026
Application No. 18/608,360

STACKED SURFACE ACOUSTIC WAVE DEVICE

Non-Final OA §103
Filed
Mar 18, 2024
Priority
Mar 28, 2023 — provisional 63/492,693
Examiner
TRA, ANH QUAN
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Skyworks Solutions Inc.
OA Round
3 (Non-Final)
73%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
78%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
818 granted / 1123 resolved
+4.8% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
38 currently pending
Career history
1158
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
58.8%
+18.8% vs TC avg
§102
24.0%
-16.0% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1123 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2, 4-6, 8, 10, 11 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Solal et al. (US 8610518) in view of Caron et al. (US 20210167752) and Branch et al. (US 12084708). As to claim 1, Solal et al.’s figures 1-3 show a surface acoustic wave device comprising: (a first bulk acoustic wave resonator comprising) a first interdigital transducer electrode (IDT 20) in electrical communication with a first piezoelectric layer (18), the first interdigital transducer electrode being an input interdigital transducer electrode (figure 3 shows IDT 20 receives input signal IN); and (a second bulk acoustic wave resonator comprising) a second interdigital transducer electrode (14) in electrical communication with a second piezoelectric layer (12), the second interdigital transducer electrode being an output interdigital transducer electrode (figure 3 shows IDT 14 outputs to IDT 14A), the first and second interdigital transducer electrodes positioned between at least a portion of the first piezoelectric layer and at least a portion of the second piezoelectric layer such that the second interdigital transducer electrode is configured to transduce a wave generated by the first interdigital transducer electrode. The figures fail to show that each of the first and second bulk acoustic wave resonators further comprises a support substrate, a functional layer and a trap rich layer arranged as claimed. However, Caron et al.’s figure 2A shows a bulk acoustic wave resonator comprises comprising a functional layer (20) between the support substrate (17) and piezoelectric layer (12), and a trap rich layer (22) between the support substrate and the functional layer. Therefore, it would have been obvious to one having ordinary skill in the art to further add a substrate, functional layer, and trap rich layer arranged as claimed for each of Solal et al.’s first and second bulk acoustic wave resonators for the purpose of reducing noise. Solal et al.’s figures further show a dielectric layer (24) between the first and second piezoelectric layers, a thickness of the dielectric layer being in a range of 0.1L to 0.5L ( Branch et al.’s figure 19D shows the period p for electrodes is about ½ wavelength or ½ L (col. 15, lines 21-25). Therefore, it would have been obvious to one having ordinary skill in the art to set Solal et al.’s “p” to be ½ wavelength or ½ L to achieve optimum performance. Solal et al.’s col. 3, lines 62-65. teaches that “a thickness dimension of the dielectric layer 24 ranges between h/2p=25% and h/2p=150%, and further is generally less than h/2p=80%”, where “p” represents a period for electrodes (col. 3, lines 41-43). Therefore, it is seen as an obvious design preference to set the thickness (h) of the dielectric layer (24) to be in a range of 0.1L to 0.5L to ensure optimum performance, MPEP 2144.05). As to claim 2, Solal et al.’s figures show a first pair of reflectors and a second pair of reflectors (see figure 2 or 3), wherein the first interdigital transducer electrode is positioned longitudinally between the first pair of reflectors, and the second interdigital transducer electrode is positioned longitudinally between the second pair of reflectors. As to claim 4, Solal et al.’s figures show that the dielectric layer is a silicon dioxide layer (col. 3, lines 57-65). As to claim 5, selecting the thickness as claimed is seen as an obvious design preference to ensure optimum performance, see Solal et al.’s col. 3, lines 62-65 and MPEP 2144.05. As to claim 6, Solal et al.’s figures show that a pitch of the first interdigital transducer electrode and a pitch of the second interdigital transducer electrode are the same. As to claim 8, Solal et al.’s figure 3 shows a first input/output terminal electrically coupled to the first interdigital transducer electrode, and a second input/output terminal electrically coupled to the second interdigital transducer electrode, the first and second input/output terminals exposed on a surface of the acoustic wave device. As to claim 10, the modified Solal et al.’s figures show that the first piezoelectric layer is disposed on the first support substrate (Caron et al.’s 17 in the first bulk acoustic resonator) and the second piezoelectric layer is disposed on a second support substrate (Caron et al.’s 17 in the second bulk acoustic resonator) such that the first and second piezoelectric layers are positioned between the first and second support substrates. As to claim 11, Solal et al.’s figures show that the first interdigital transducer electrode is disposed on, partially within, or embedded in the first piezoelectric layer. Claims 18-20 recite similar limitations in claims above. Therefore, they are rejected for the same reasons. Claim(s) 9, 12-13, 15-16 and 18-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Solal et al. (US 8610518) in view of Caron et al. (US 20210167752), Branch et al. (US 12084708) and Hamasaki et al. (US 20220140224). As to claim 9, the modified Solal et al.’s figures fail to show that first input/output terminal electrically to couple to the first interdigital transducer electrode by way of a first conductive via, and the second input/output terminal electrically to couple to the second interdigital transducer electrode by way of a second conductive via. However, Hamasaki et al.’s figure 1 shows a similar device that its IDTs (16 and 26) are coupled to external pads (41 and 44) by way of conductive vias (51-61 and 54). It would have been obvious to one having ordinary skill in the art to connect the first and second input/output terminals to external pads by way of conductive vias for the purpose of saving space and communicating with external devices. Note that the external pads is now considered as the first and second input/output terminals. Claims 12-13, 15-16 and 18 recite similar limitations in claims above. Therefore, they are rejected for the same reasons. As further regarding claim 12, the modified Solal et al.’s figures show a conductive via (i.e., Hamasaki et al.’s 51-61) extending at least through the dielectric layer (Solal’s 24, in order to connect the second IDS to external pad). As to claims 19 and 20, selecting the thickness as claimed is seen as an obvious design preference to ensure optimum performance, see MPEP 2144.05. As to claim 21, the modified Solal et al.’s figures show that one of the first conductive via or the second conductive via extends vertically through the dielectric layer (in order to connect the second IDS to external pad). As to claim 22, the modified Solal et al.’s figures show that the conductive via is laterally offset from and connected to the input interdigital transducer electrode through a lateral interconnect, and the conductive via further extends through the second support substrate, the second piezoelectric layer, the second functional layer, and second first trap rich layer. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Solal et al. (US 8610518) in view of Caron et al. (US 20210167752), Branch et al. (US 12084708), Hamasaki et al. (US 20220140224) and Hatakayama et al. (US 20220416757). As to claim 7, Solal et al.’s figures fail to show that a pitch of the first interdigital transducer electrode and a pitch of the second interdigital transducer electrode are different. However, Hatakeyama et al. (‘757)’s figure 1 shows a similar device that its transducers have different pitches. Therefore, it would have been obvious to one having ordinary skill in the art to select different pitches for Solal et al.’s transducers for the purpose of achieving desired filtering frequency. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH-QUAN TRA whose telephone number is (571)272-1755. The examiner can normally be reached Mon-Fri from 8:00 A.M.-5:00 P.M. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /QUAN TRA/ Primary Examiner Art Unit 2843
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Prosecution Timeline

Mar 18, 2024
Application Filed
Oct 15, 2025
Non-Final Rejection mailed — §103
Feb 16, 2026
Response Filed
Feb 26, 2026
Final Rejection mailed — §103
May 26, 2026
Request for Continued Examination
May 28, 2026
Response after Non-Final Action
Jun 17, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
73%
Grant Probability
78%
With Interview (+5.4%)
2y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1123 resolved cases by this examiner. Grant probability derived from career allowance rate.

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