DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-19 are currently pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/06/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 18 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim defines “computer-readable storage medium” which is related to software per se. However, the claim does not define a non-transitory computer-readable storage medium and is thus non-statutory for that reason (i.e., "When functional descriptive material is recorded on some non- transitory computer-readable medium it becomes structurally and functionally interrelated to the non-transitory medium and will be statutory in most cases since use of technology permits the function of the descriptive material to be realized"- Guidelines Annex IV).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, 5, 7, 9, 12, 13, 15, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, PENG et al. (Hereafter, “Zhang”) [CN 113542770 A].
In regards to claim 1, Zhang discloses a residual data writing method ([0005-0008] a DCT transformation method wherein residual block data is written into storage unit), comprising: determining a residual data reading mode ([0055] diagonal read/write rule) comprising a reading sequence of each piece of residual data ([0043] reading out a row of residual block data in parallel from each of the first storage units), and the quantity of residual data read simultaneously at each time ([0040] Since data belonging to different storage cells can be read in the same cycle, a row of data can be read in parallel from different storage cells in one cycle, thereby improving the circuit throughput. [0055] writing row-transformed data within one cycle while the column-transformed circuit reads out one column of row-transformed data in parallel within one cycle); determining the number of buffer groups and the number of buffers in each buffer group according to the residual data reading mode ([0040] In some embodiments, when inputting residual block data, the first memory can be divided into multiple first storage cells with a depth equal to the height of the residual block data. The number of first storage cells is equal to the width of the residual block data. [0044] determining the required storage area size based on the height and width of the residual block data, and then selecting multiple second storage units from the preset intermediate transposed storage structure based on the storage area size), wherein each buffer is provided with a unique buffer index ([0057-0058] bank is the number of the second storage unit), and each buffer comprises a plurality of buffer addresses ([0057-0058] depth is the depth value in the bank); acquiring a buffer index and a buffer address corresponding to to-be-written residual data ([0057] coef_tmp[bank'][depth] indicates that the position where the data should be written after the corner read and write rule); and writing the to-be-written residual data into a corresponding buffer according to the buffer index and the buffer address ([0043] write each data in the row-transformed data into different second storage units according to the preset diagonal read and write rules [0060] As shown in Figure 6, all data in each row is written to different second storage units, thus enabling simultaneous parallel writing. Furthermore, after row transformation, the data in the same column of the residual block is written to the same depth position in different second storage units.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the different embodiments, aspects, and/or examples of Zhang in order to improve the reading and writing of data [See Zhang].
In regards to claim 4, the limitations of claim 1 have been addressed. Zhang discloses wherein the acquiring the buffer index and the buffer address corresponding to the to-be-written residual data comprises: partitioning initial residual data acquired in a motion estimation target phase to obtain 16-bit to-be-written residual data ([0045-0046] bit width is defined according to the data after row transformation, 64x64 would have 64 storage units with a depth of 64 pre-set [0048] For example, as shown in Figure 4, the required storage area size for 4x8 residual block data is 8x8. Therefore, based on the 8x8 storage area, eight second storage units with a depth of 8 need to be selected from the preset intermediate transpose storage structure.); acquiring a vector coordinate corresponding to the to-be-written residual data according to a positional relationship between the to-be-written residual data and the initial residual data ([0057] coef_tmp[bank][depth] represents the original location where the data would have been written without the diagonal read/write rule); acquiring a search center point corresponding to the initial residual data ([0057] depth is the depth value and size represents the number of second storage units or the total depth, which is the maximum value of the width and height of the residual block data), and obtaining a vector offset coordinate of the to-be-written residual data according to an offset between the vector coordinate and the search center point ([0056] bank’ = (bank+depth)%size); and acquiring the buffer index and the buffer address corresponding to the to-be-written residual data according to the vector offset coordinate ([0056-0057] coef_tmp[bank’][depth]=coef_tmp[(bank+depth)%size][depth] represents the location where the data will be written after the diagonal read/write rule is adopted).
In regards to claim 5, the limitations of claim 4 have been addressed. Zhang discloses wherein the acquiring the buffer index corresponding to the to-be-written residual data according to the vector offset coordinate comprises: concatenating buffer lines of all buffers with the same buffer depth according to a buffer index of each buffer to obtain a concatenated buffer line ([0040] the first memory can be divided into multiple first storage cells with a depth equal to the height of the residual block data. The number of first storage cells is equal to the width of the residual block data); acquiring a concatenation width of the concatenated buffer line according to a width of a buffer line of each buffer ([0040] number of first storage cells is equal to the width of the residual block data); determining a first position mapping relationship between the to-be-written residual data and the concatenated buffer line according to the vector offset coordinate and the concatenation width ([0056] bank’ = (bank+depth)%size); and determining a buffer group and a buffer corresponding to the to-be-written residual data according to the first position mapping relationship, to determine the buffer index corresponding to the to-be-written residual data ([0056-0057] coef_tmp[bank’][depth]=coef_tmp[(bank+depth)%size][depth] represents the location where the data will be written after the diagonal read/write rule is adopted).
In regards to claim 7, the limitations of claim 4 have been addressed. Zhang discloses wherein the acquiring the buffer address corresponding to the to-be-written residual data according to the vector offset coordinate comprises: determining a second position mapping relationship between the to-be-written residual data and a buffer depth according to the vector offset coordinate and the search center point; and determining a buffer depth corresponding to the to-be-written residual data according to the second position mapping relationship, to determine the buffer address corresponding to the to-be-written residual data ([0058] For example, taking 4x8 data as an example, as shown in Figure 6, the row transformation circuit performs the row transformation for the first time to obtain the first row of transformed data. Using the diagonal read and write rule, the four data in the row of transformed data are written in parallel along the diagonal direction starting from the depth0 position of bank0: [bank0][depth0], [bank1][depth1], [bank2][depth2], and [bank3][depth3].).
Claim 9 lists all the same elements of claim 1, but in apparatus form rather than method form. Therefore, the supporting rationale of the rejection to claim 1 applies equally as well to claim 9.
Claim 12 lists all the same elements of claim 4, but in apparatus form rather than method form. Therefore, the supporting rationale of the rejection to claim 4 applies equally as well to claim 12.
Claim 13 lists all the same elements of claim 5, but in apparatus form rather than method form. Therefore, the supporting rationale of the rejection to claim 5 applies equally as well to claim 13.
Claim 15 lists all the same elements of claim 7, but in apparatus form rather than method form. Therefore, the supporting rationale of the rejection to claim 7 applies equally as well to claim 15.
Claim 17 lists all the same elements of claim 1, but in computer device form rather than method form. Therefore, the supporting rationale of the rejection to claim 1 applies equally as well to claim 17.
Claim 18 lists all the same elements of claim 1, but in computer-readable storage medium form rather than method form. Therefore, the supporting rationale of the rejection to claim 1 applies equally as well to claim 18.
Claim 19 lists all the same elements of claim 1, but in computer program product form rather than method form. Therefore, the supporting rationale of the rejection to claim 1 applies equally as well to claim 19.
Claim(s) 2, 3, 6, 10, 11, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of PARK et al. (Hereafter, “Park”) [US 2021/0211699 A1].
In regards to claim 2, the limitations of claim 1 have been addressed. Zhang discloses wherein the determining the residual data reading mode comprises: configuring a residual data reading circuit comprising two data interfaces which are configured to simultaneously read residual data corresponding to two adjacent motion vectors in each residual data reading process ([0010-0015] the DCT transformation circuit system comprises the row transformation circuit is used to read a row of residual block data from each first storage unit in parallel and the column transformation circuit is used to read a column of row-transformed data in parallel from each of the second storage units according to the diagonal read-write rules); and reading the residual data from the buffer at least once through the two data interfaces of the residual data reading circuit ([0016] During input, by storing the residual block data columnwise into different first storage units, since the data belonging to different first storage units can be read in parallel, the same row of data can be read simultaneously. Thus, a row of residual block data can be read in parallel from each first storage unit for row transformation calculation, which improves the efficiency of reading data.).
Park discloses residual data corresponding to two adjacent motion vectors ([0130] In the MVP mode, residual data from a motion vector of a current block may be encoded using a motion vector of an adjacent block as an MVP predictor.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Zhang with the residual data being related to a motion vector of the current block and an adjacent motion vector as taught by Park in order to effectively compress image content [See Park].
In regards to claim 3, the limitations of claim 1 have been addressed. Zhang discloses wherein the determining the number of buffer groups and the number of buffers in each buffer group according to the residual data reading mode comprises: determining residual data corresponding to two adjacent motion vectors read simultaneously in each residual data reading process according to the residual data reading mode, to configure two buffer groups; and configuring the same number of buffers in each buffer group ([0040] In some embodiments, when inputting residual block data, the first memory can be divided into multiple first storage cells with a depth equal to the height of the residual block data. The number of first storage cells is equal to the width of the residual block data. [0044] determining the required storage area size based on the height and width of the residual block data, and then selecting multiple second storage units from the preset intermediate transposed storage structure based on the storage area size).
Park discloses residual data corresponding to two adjacent motion vectors ([0130] In the MVP mode, residual data from a motion vector of a current block may be encoded using a motion vector of an adjacent block as an MVP predictor.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Zhang with the residual data being related to a motion vector of the current block and an adjacent motion vector as taught by Park in order to effectively compress image content [See Park].
In regards to claim 6, the limitations of claim 5 have been addressed. Zhang discloses wherein the to-be-written residual data comprises first residual data and second residual data which correspond to two adjacent motion vectors, and the determining the buffer group and the buffer corresponding to the to-be- written residual data according to the first position mapping relationship to determine the buffer index corresponding to the to-be-written residual data comprises: determining a plurality of target buffers having a corresponding relationship according to an arrangement sequence of buffers in each buffer group, wherein each of the target buffers belongs to a different buffer group, and the target buffers have the same arrangement sequence in respective corresponding buffer groups ([0058] For example, taking 4x8 data as an example, as shown in Figure 6, the row transformation circuit performs the row transformation for the first time to obtain the first row of transformed data. Using the diagonal read and write rule, the four data in the row of transformed data are written in parallel along the diagonal direction starting from the depth0 position of bank0: [bank0][depth0], [bank1][depth1], [bank2][depth2], and [bank3][depth3].); acquiring a difference parameter according to a buffer index of each target buffer ([0072] cyclic shift); determining a buffer group and a buffer corresponding to the first residual data ([0058] [bank0][depth0]), and a buffer group and a buffer corresponding to the second residual data respectively according to the first position mapping relationship ([0058] [bank1][depth1]), to determine a first buffer index corresponding to the first residual data and a second buffer index corresponding to the second residual data ([0057] depth is the depth value); when the first buffer index is the same as the second buffer index, correcting the second buffer index according to the difference parameter to obtain a third buffer index ([0060] As shown in Figure 6, all data in each row is written to different second storage units, thus enabling simultaneous parallel writing. Furthermore, after row transformation, the data in the same column of the residual block is written to the same depth position in different second storage units. [0072-0073] correcting incorrect storage with cyclic shift); and determining the first buffer index as a buffer index corresponding to the first residual data, and determining the third buffer index as a buffer index corresponding to the second residual data ([0058] For example, taking 4x8 data as an example, as shown in Figure 6, the row transformation circuit performs the row transformation for the first time to obtain the first row of transformed data. Using the diagonal read and write rule, the four data in the row of transformed data are written in parallel along the diagonal direction starting from the depth0 position of bank0: [bank0][depth0], [bank1][depth1], [bank2][depth2], and [bank3][depth3].).
Park discloses residual data corresponding to two adjacent motion vectors ([0130] In the MVP mode, residual data from a motion vector of a current block may be encoded using a motion vector of an adjacent block as an MVP predictor.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Zhang with the residual data being related to a motion vector of the current block and an adjacent motion vector as taught by Park in order to effectively compress image content [See Park].
Claim 10 lists all the same elements of claim 2, but in apparatus form rather than method form. Therefore, the supporting rationale of the rejection to claim 2 applies equally as well to claim 10.
Claim 11 lists all the same elements of claim 3, but in apparatus form rather than method form. Therefore, the supporting rationale of the rejection to claim 3 applies equally as well to claim 11.
Claim 14 lists all the same elements of claim 6, but in apparatus form rather than method form. Therefore, the supporting rationale of the rejection to claim 6 applies equally as well to claim 14.
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of CUI, Hai-liang et al. (Hereafter, “Cui”) [CN 111045600 A].
In regards to claim 8, the limitations of claim 1 have been addressed. Zhang fails to explicitly disclose wherein the writing the to-be-written residual data into the corresponding buffer according to the buffer index and the buffer address comprises: generating a mask corresponding to the buffer index and the buffer address; and writing the to-be-written residual data into the corresponding buffer according to the buffer index, the buffer address, and the mask.
Cui discloses wherein the writing the to-be-written residual data into the corresponding buffer according to the buffer index and the buffer address comprises: generating a mask corresponding to the buffer index and the buffer address ([0069] In practical applications, a MaskBuff can be added as a verification buffer to perform address mapping with the internal memory array, mapping the addresses in the memory array to the MaskBuff.); and writing the to-be-written residual data into the corresponding buffer according to the buffer index, the buffer address, and the mask ([0070] Based on the maskdata of each line in MaskBuff, the bits that need to be rewritten at the corresponding address in the memory array can be determined. For example, in Figure 2, if D0[1] is 1, then the bit1 of the address corresponding to address D0 in the memory array needs to be rewritten. Then the WD[1] bit of the write driver will write the target data (1 or 0) into the bit1 of the address matching D0 in the memory array.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Zhang with the known use of a mask to perform address mapping in a buffer as taught by Cui in order to improve the data writing efficiency [See Cui].
Claim 16 lists all the same elements of claim 8, but in apparatus form rather than method form. Therefore, the supporting rationale of the rejection to claim 8 applies equally as well to claim 16.
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/KAITLIN A RETALLICK/Primary Examiner, Art Unit 2482