DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-8 and 17-20 in the “Response To Restriction Requirement” filed on May 22, 2026 is acknowledged. Claims 9-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 18, 2024 has been considered by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 17, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9,991,352 B1 (Frougier).
Regarding claim 1, Frougier discloses, A semiconductor structure (semiconductor structure (100); FIG. 16; Col. 4, line 40), comprising:
a first nanosheet channel layer (first nanosheet channel layer (108A); FIG. 12; Col. 4, lines 63-64) having a first middle portion (annotated FIG. 12, below) and first outer portions (annotated FIG. 12, below);
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a second nanosheet channel layer (second nanosheet channel layer (108B); FIG. 12; Col. 4, lines 63-64) disposed over the first nanosheet channel layer (108A), the second nanosheet channel layer (108B) having a second middle portion (annotated FIG. 12, above) and second outer portions (annotated FIG. 12, above), wherein a first distance (annotated FIG. 12, above) between the first middle portion (annotated FIG. 12, above) and the second middle portion (annotated FIG. 12, above) defines a first region (annotated FIG. 12, above) and a second distance (annotated FIG. 12, above) between the first outer portions (annotated FIG. 12, above) and the second outer portions (annotated FIG. 12, above) defines a second region (annotated FIG. 12, above), wherein the second distance (annotated FIG. 12, above) is less than the first distance (annotated FIG. 12, above);
a gate dielectric layer (gate dielectric layer (134A); FIG. 16; Col. 12, line 60) disposed in the first region (annotated FIG. 12, above, and annotated FIG. 16, below) and the second region (annotated FIG. 12, above, and annotated FIG. 16, below), wherein the gate dielectric layer (134A) pinches off the second region (annotated FIG. 16, below); and
a conductive gate layer (conductive gate layer (134B); FIG. 16; Col. 12, line 66) disposed on the gate dielectric layer (134A) disposed in the first region (annotated FIG. 12, above, and annotated FIG. 16, below).
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Regarding claim 2, Frougier discloses, The semiconductor structure (100) according to claim 1, wherein the gate dielectric layer (134A) fills the second region (annotated FIGs. 12 and 16, above).
Regarding claim 3, Frougier discloses, The semiconductor structure (100) according to claim 1, wherein the gate dielectric layer (134A) is a continuous layer in the first region and the second region (annotated FIGs. 12 and 16, above).
Regarding claim 4, Frougier discloses, The semiconductor structure (100) according to claim 1, wherein the conductive gate layer (134B) fills the first region (annotated FIGs. 12 and 16, above).
Regarding claim 17, Frougier discloses, An integrated circuit (integrated circuit (100); FIG. FIG. 16; Col. 4, lines 30-31), comprising:
one or more semiconductor structures (one or more semiconductor structures (100); FIG. 16; Col. 4, line 40), wherein at least one of the one or more semiconductor structures (100) comprises:
a first nanosheet channel layer (first nanosheet channel layer (108A); FIG. 12; Col. 4, lines 63-64) having a first middle portion (annotated FIG. 12, above) and first outer portions (annotated FIG. 12, above);
a second nanosheet channel layer (second nanosheet channel layer (108B); FIG. 12; Col. 4, lines 63-64) disposed over the first nanosheet channel layer (108A), the second nanosheet channel layer (108B) having a second middle portion (annotated FIG. 12, above) and second outer portions (annotated FIG. 12, above), wherein a first distance (annotated FIG. 12, above) between the first middle portion (annotated FIG. 12, above) and the second middle portion (annotated FIG. 12, above) defines a first region (annotated FIG. 12, above) and a second distance (annotated FIG. 12, above) between the first outer portions (annotated FIG. 12, above) and the second outer portions (annotated FIG. 12, above) defines a second region (annotated FIG. 12, above), wherein the second distance is less than the first distance (annotated FIG. 12, above);
a gate dielectric layer (gate dielectric layer (134A); FIG. 16; Col. 12, line 60) disposed in the first region (annotated FIGs. 12 and 16, above) and the second region (annotated FIGs. 12 and 16, above), wherein the gate dielectric layer (134A) pinches off the second region (annotated FIG. 16, above); and
a conductive gate layer (conductive gate layer (134B); FIG. 16; Col. 12, line 66) disposed on the gate dielectric layer (134A) disposed in the first region (annotated FIGs. 12 and 16, above).
Regarding claim 18, Frougier discloses, The integrated circuit (100) according to claim 17, wherein the conductive gate layer (134B) fills the first region (annotated FIGs. 12 and 16, above), and wherein the gate dielectric layer fills (134A) the second region (annotated FIGs. 12 and 16, above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5-8, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier in view of US 2023/0197716 A1 (Bomberger).
Regarding claim 5, Frougier discloses, The semiconductor structure (100) according to claim 1, further comprising a source/drain liner layer (source/drain liner layer (116); FIGs. 12 and 16; Col. 8, line 51) disposed on sidewalls (annotated FIG. 16, above) of the gate dielectric layer (134A) disposed in the second region (annotated FIG. 16, above), and a source/drain region (source/drain region (118); FIG. 16; Col. 9, line 32) disposed on the source/drain liner layer (116).
But, Frougier does not appear to explicitly disclose, further comprising a source/drain liner layer disposed on sidewalls of the first nanosheet channel layer and the second nanosheet channel layer.
However, in analogous art, Bomberger discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that source/drain liner layers (source/drain liner layers (215); FIG. 2D; [0043]) provide low contact resistance which improves drive current ([0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Frougier and Bomberger before him/her to utilize a source/drain liner layer disposed on sidewalls of the first nanosheet channel layer (108A) and the second nanosheet channel layer (108B) of Frougier to provide low contact resistance and improve drive current for the semiconductor structure (100) of Frougier, as taught by Bomberger.
Regarding claim 6, Frougier in view of Bomberger discloses, The semiconductor structure (100) according to claim 5, wherein the source/drain region (118) is separated from the conductive gate layer (134B) by the source/drain liner layer (116 and/or 215) and the gate dielectric layer disposed (134A) in the second region (Frougier, annotated FIGs. 12 and 16, above).
Regarding claim 7, Frougier in view of Bomberger discloses, The semiconductor structure (100) according to claim 5, wherein the source/drain liner layer (116 and/or 215) comprises silicon (Bomberger, [0045]) and the source/drain region comprises SiGe (Frougier, Col. 9, lines, 35-39).
Regarding claim 8, Frougier in view of Bomberger discloses, The semiconductor structure (100) according to claim 7, wherein the source/drain liner layer (116 and/or 215) is a pFET source/drain liner layer (116 and/or 215) (Bomberger, [0043]—boron-doped liners (215)) and the source/drain region (118) is a pFET source/drain region (Bomberger, [0043]—PMOS transistor).
Regarding claim 19, Frougier discloses, The integrated circuit (100) according to claim 17, further comprising a source/drain liner layer (source/drain liner layer (116); FIGs. 12 and 16; Col. 8, line 51) disposed on sidewalls (annotated FIG. 16, above) of the gate dielectric layer (134A) disposed in the second region (annotated FIG. 16, above), and a source/drain region (source/drain region (118); FIG. 16; Col. 9, line 32) disposed on the source/drain liner layer (116).
But, Frougier does not appear to explicitly disclose, further comprising a source/drain liner layer disposed on sidewalls of the first nanosheet channel layer and the second nanosheet channel layer.
However, in analogous art, Bomberger discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that source/drain liner layers (source/drain liner layers (215); FIG. 2D; [0043]) provide low contact resistance which improves drive current ([0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Frougier and Bomberger before him/her to utilize a source/drain liner layer disposed on sidewalls of the first nanosheet channel layer (108A) and the second nanosheet channel layer (108B) of Frougier to provide low contact resistance and improve drive current for the semiconductor structure of the integrated circuit of Frougier, as taught by Bomberger.
Regarding claim 20, Frougier in view of Bomberger discloses, The integrated circuit (100) according to claim 19, wherein the source/drain liner layer (116 and/or 215) comprises silicon (Bomberger, [0045]) and the source/drain region comprises SiGe (Frougier, Col. 9, lines, 35-39).
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure.
US 2020/0105929 A1 (Zhang)—Discloses a semiconductor device (75; FIG. 2K) having a first nanosheet channel layer (21; FIG. 21) having first middle portion and first end portion (21A; FIG. 2I) and a second nanosheet channel layer (21; FIG. 21) disposed on first nanosheet channel layer (21) and having second middle portion and second end portion (21A; FIG. 2I) where a first distance between the first middle portion and second middle portion defines and first region and a second distance between first end portion and the second end portion defines a second region. Also discloses that the first and second distances are different. Additionally discloses, gate dielectric layer 30, conductive gate layer (32), and respective source and drain regions (56A and 56B).
US 2022/0310816 A1 (Wong)—Discloses a semiconductor device (50N and 50P; FIG. 14) that utilizes liner layers (91 and 93), where layer (93) exerts a tensile force or strain to counteract a compressive force or strain in layer (91). Also discloses, first and second nanosheet channels, a gate dielectric layer, a conductive gate layer, and source/drain regions.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights