DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 17, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9,991,352 B1 (Frougier).
Regarding amended claim 1, Frougier discloses, A semiconductor structure (semiconductor structure (100); FIG. 16; Col. 4, line 40), comprising:
a first nanosheet channel layer (first nanosheet channel layer (108A); FIG. 12; Col. 4, lines 63-64) having a first middle portion (annotated FIG. 12, below) and first outer portions (annotated FIG. 12, below);
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a second nanosheet channel layer (second nanosheet channel layer (108B); FIG. 12; Col. 4, lines 63-64) disposed over the first nanosheet channel layer (108A), the second nanosheet channel layer (108B) having a second middle portion (annotated FIG. 12, above) and second outer portions (annotated FIG. 12, above), wherein a first distance (annotated FIG. 12, above) between the first middle portion (annotated FIG. 12, above) and the second middle portion (annotated FIG. 12, above) defines a first region (annotated FIG. 12, above) and a second distance (annotated FIG. 12, above) between the first outer portions (annotated FIG. 12, above) and the second outer portions (annotated FIG. 12, above) defines a second region (annotated FIG. 12, above), wherein the second distance (annotated FIG. 12, above) is less than the first distance (annotated FIG. 12, above);
a gate dielectric layer (gate dielectric layer (134A); FIG. 16; Col. 12, line 60) disposed in the first region (annotated FIG. 12, above, and annotated FIG. 16, below) and the second region (annotated FIG. 12, above, and annotated FIG. 16, below), wherein the gate dielectric layer (134A) pinches off1 the second region (annotated FIG. 16, below) and extends (annotated FIG. 16, below; extends by virtue of at least its width) between source/drain regions (source/drain regions (118); FIG. 16; Col. 9, line 32) on opposing sides of the first nanosheet channel layer (108A) and the second nanosheet channel layer (108B); and
a conductive gate layer (conductive gate layer (134B); FIG. 16; Col. 12, line 66) disposed on the gate dielectric layer (134A) disposed in the first region (annotated FIG. 12, above, and annotated FIG. 16, below).
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Regarding claim 2, Frougier discloses, The semiconductor structure (100) according to claim 1, wherein the gate dielectric layer (134A) fills the second region (annotated FIGs. 12 and 16, above).
Regarding claim 3, Frougier discloses, The semiconductor structure (100) according to claim 1, wherein the gate dielectric layer (134A) is a continuous layer in the first region and the second region (annotated FIGs. 12 and 16, above).
Regarding claim 4, Frougier discloses, The semiconductor structure (100) according to claim 1, wherein the conductive gate layer (134B) fills the first region (annotated FIGs. 12 and 16, above).
Regarding amended claim 17, Frougier discloses, An integrated circuit (integrated circuit (100); FIG. 16; Col. 4, lines 30-31), comprising:
one or more semiconductor structures (one or more semiconductor structures (100); FIG. 16; Col. 4, line 40), wherein at least one of the one or more semiconductor structures (100) comprises:
a first nanosheet channel layer (first nanosheet channel layer (108A); FIG. 12; Col. 4, lines 63-64) having a first middle portion (annotated FIG. 12, above) and first outer portions (annotated FIG. 12, above);
a second nanosheet channel layer (second nanosheet channel layer (108B); FIG. 12; Col. 4, lines 63-64) disposed over the first nanosheet channel layer (108A), the second nanosheet channel layer (108B) having a second middle portion (annotated FIG. 12, above) and second outer portions (annotated FIG. 12, above), wherein a first distance (annotated FIG. 12, above) between the first middle portion (annotated FIG. 12, above) and the second middle portion (annotated FIG. 12, above) defines a first region (annotated FIG. 12, above) and a second distance (annotated FIG. 12, above) between the first outer portions (annotated FIG. 12, above) and the second outer portions (annotated FIG. 12, above) defines a second region (annotated FIG. 12, above), wherein the second distance is less than the first distance (annotated FIG. 12, above);
a gate dielectric layer (gate dielectric layer (134A); FIG. 16; Col. 12, line 60) disposed in the first region (annotated FIGs. 12 and 16, above) and the second region (annotated FIGs. 12 and 16, above), wherein the gate dielectric layer (134A) pinches off2 the second region (annotated FIG. 16, above) and extends (annotated FIG. 16, below; extends by virtue of at least its width) between source/drain regions (source/drain regions (118); FIG. 16; Col. 9, line 32) on opposing sides of the first nanosheet channel layer (108A) and the second nanosheet channel layer (108B); and
a conductive gate layer (conductive gate layer (134B); FIG. 16; Col. 12, line 66) disposed on the gate dielectric layer (134A) disposed in the first region (annotated FIGs. 12 and 16, above).
Regarding claim 18, Frougier discloses, The integrated circuit (100) according to claim 17, wherein the conductive gate layer (134B) fills the first region (annotated FIGs. 12 and 16, above), and wherein the gate dielectric layer fills (134A) the second region (annotated FIGs. 12 and 16, above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5-8, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier in view of US 2023/0197716 A1 (Bomberger).
Regarding amended claim 5, Frougier discloses, The semiconductor structure (100) according to claim 1, further comprising a source/drain liner layer (source/drain liner layer (116); FIGs. 12 and 16; Col. 8, line 51) disposed on sidewalls (annotated FIG. 16, above) of the gate dielectric layer (134A) disposed in the second region (annotated FIG. 16, above), and one source/drain region (118) of the source/drain regions (118) disposed on the source/drain liner layer (116).
But, Frougier does not appear to explicitly disclose, further comprising a source/drain liner layer disposed on sidewalls of the first nanosheet channel layer and the second nanosheet channel layer.
However, in analogous art, Bomberger discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that source/drain liner layers (source/drain liner layers (215); FIG. 2D; [0043]) provide low contact resistance which improves drive current ([0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Frougier and Bomberger before him/her to utilize a source/drain liner layer disposed on sidewalls of the first nanosheet channel layer (108A) and the second nanosheet channel layer (108B) of Frougier to provide low contact resistance and improve drive current for the semiconductor structure (100) of Frougier, as taught by Bomberger.
Regarding amended claim 6, Frougier in view of Bomberger discloses, The semiconductor structure (100) according to claim 5, wherein the one source/drain region (118) is separated from the conductive gate layer (134B) by the source/drain liner layer (116 and/or 215) and the gate dielectric layer disposed (134A) in the second region (Frougier, annotated FIGs. 12 and 16, above).
Regarding amended claim 7, Frougier in view of Bomberger discloses, The semiconductor structure (100) according to claim 5, wherein the source/drain liner layer (116 and/or 215) comprises silicon (Bomberger, [0045]) and the one source/drain region (118) comprises SiGe (Frougier, Col. 9, lines, 35-39).
Regarding amended claim 8, Frougier in view of Bomberger discloses, The semiconductor structure (100) according to claim 7, wherein the source/drain liner layer (116 and/or 215) is a pFET source/drain liner layer (116 and/or 215) (Bomberger, [0043]—boron-doped liners (215)) and the one source/drain region (118) is a pFET source/drain region (Bomberger, [0043]—PMOS transistor).
Regarding amended claim 19, Frougier discloses, The integrated circuit (100) according to claim 17, further comprising a source/drain liner layer (source/drain liner layer (116); FIGs. 12 and 16; Col. 8, line 51) disposed on sidewalls (annotated FIG. 16, above) of the gate dielectric layer (134A) disposed in the second region (annotated FIG. 16, above), and one source/drain region (118) of the source/drain regions (118) disposed on the source/drain liner layer (116).
But, Frougier does not appear to explicitly disclose, further comprising a source/drain liner layer disposed on sidewalls of the first nanosheet channel layer and the second nanosheet channel layer.
However, in analogous art, Bomberger discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that source/drain liner layers (source/drain liner layers (215); FIG. 2D; [0043]) provide low contact resistance which improves drive current ([0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Frougier and Bomberger before him/her to utilize a source/drain liner layer disposed on sidewalls of the first nanosheet channel layer (108A) and the second nanosheet channel layer (108B) of Frougier to provide low contact resistance and improve drive current for the semiconductor structure of the integrated circuit of Frougier, as taught by Bomberger.
Regarding amended claim 20, Frougier in view of Bomberger discloses, The integrated circuit (100) according to claim 19, wherein the source/drain liner layer (116 and/or 215) comprises silicon (Bomberger, [0045]) and the one source/drain region (118) comprises SiGe (Frougier, Col. 9, lines, 35-39).
Amended claims 1 and 17 are alternatively rejected under 35 U.S.C. 103 as being unpatentable over Frougier in view of US 2023/0018266 A1 (Fan).
Regarding amended claim 1, Frogier discloses, Regarding amended claim 1, Frougier discloses, A semiconductor structure (semiconductor structure (100); FIG. 16; Col. 4, line 40), comprising:
a first nanosheet channel layer (first nanosheet channel layer (108A); FIG. 12; Col. 4, lines 63-64) having a first middle portion (annotated FIG. 12, above) and first outer portions (annotated FIG. 12, above);
a second nanosheet channel layer (second nanosheet channel layer (108B); FIG. 12; Col. 4, lines 63-64) disposed over the first nanosheet channel layer (108A), the second nanosheet channel layer (108B) having a second middle portion (annotated FIG. 12, above) and second outer portions (annotated FIG. 12, above), wherein a first distance (annotated FIG. 12, above) between the first middle portion (annotated FIG. 12, above) and the second middle portion (annotated FIG. 12, above) defines a first region (annotated FIG. 12, above) and a second distance (annotated FIG. 12, above) between the first outer portions (annotated FIG. 12, above) and the second outer portions (annotated FIG. 12, above) defines a second region (annotated FIG. 12, above), wherein the second distance (annotated FIG. 12, above) is less than the first distance (annotated FIG. 12, above);
a gate dielectric layer (gate dielectric layer (134A); FIG. 16; Col. 12, line 60) disposed in the first region (annotated FIGs. 12 and 16, above) and the second region (annotated FIGs. 12 and 16, above), wherein the gate dielectric layer (134A) pinches off3 the second region (annotated FIG. 16, above); and
a conductive gate layer (conductive gate layer (134B); FIG. 16; Col. 12, line 66) disposed on the gate dielectric layer (134A) disposed in the first region (annotated FIGs. 12 and 16, above).
But, Applicant may argue that Frougier does not appear to explicitly disclose, wherein the gate dielectric layer extends between source/drain regions on opposing sides of the first nanosheet channel layer and the second nanosheet channel layer.
However, in analogous art, Fan discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor structure (200; FIG. 12; [0013]) may include inner spacers (inner spacers (232a-232c); FIG. 8; ([0028]) between channel layers (channel layers (208a-208c); FIG. 8; [0041]) to isolate conductive gate layers (conductive gate layers (242); FIG. 12; [0018]) from source/drain regions (source/drain regions (228); FIG. 8; [0026] ) ([0011]). Fan also discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that these inner spacer features (232a-232c) may include a dielectric material ([0011]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Frougier and Fan before him/her to extend the gate dielectric layer (134A) of Frougier between source/drain regions (118) on opposing sides of first nanosheet channel layer (108A) and second nanosheet channel layer (108B) to isolate conductive gate layer (134B) from source/drain regions (118) of Frogier, as taught by Fan, thereby enhancing manufacturing efficiency by eliminating the need to fabricate separate dielectric spacers which saves manufacturing time and expense. Please see, MPEP 2143(G)—The courts have made clear that the teaching, suggestion, or motivation test is flexible and an explicit suggestion to combine the prior art is not necessary. The motivation to combine may be implicit and may be found in the knowledge of one of ordinary skill in the art, or, in some cases, from the nature of the problem to be solved. "[A]n implicit motivation to combine exists not only when a suggestion may be gleaned from the prior art as a whole, but when the ‘improvement’ is technology-independent and the combination of references results in a product or process that is more desirable, for example because it is stronger, cheaper, cleaner, faster, lighter, smaller, more durable, or more efficient.”
Regarding amended claim 17, Frougier discloses, An integrated circuit (integrated circuit (100); FIG. 16; Col. 4, lines 30-31), comprising:
one or more semiconductor structures (one or more semiconductor structures (100); FIG. 16; Col. 4, line 40), wherein at least one of the one or more semiconductor structures (100) comprises:
a first nanosheet channel layer (first nanosheet channel layer (108A); FIG. 12; Col. 4, lines 63-64) having a first middle portion (annotated FIG. 12, above) and first outer portions (annotated FIG. 12, above);
a second nanosheet channel layer (second nanosheet channel layer (108B); FIG. 12; Col. 4, lines 63-64) disposed over the first nanosheet channel layer (108A), the second nanosheet channel layer (108B) having a second middle portion (annotated FIG. 12, above) and second outer portions (annotated FIG. 12, above), wherein a first distance (annotated FIG. 12, above) between the first middle portion (annotated FIG. 12, above) and the second middle portion (annotated FIG. 12, above) defines a first region (annotated FIG. 12, above) and a second distance (annotated FIG. 12, above) between the first outer portions (annotated FIG. 12, above) and the second outer portions (annotated FIG. 12, above) defines a second region (annotated FIG. 12, above), wherein the second distance is less than the first distance (annotated FIG. 12, above);
a gate dielectric layer (gate dielectric layer (134A); FIG. 16; Col. 12, line 60) disposed in the first region (annotated FIGs. 12 and 16, above) and the second region (annotated FIGs. 12 and 16, above), wherein the gate dielectric layer (134A) pinches off4 the second region (annotated FIG. 16, above); and
a conductive gate layer (conductive gate layer (134B); FIG. 16; Col. 12, line 66) disposed on the gate dielectric layer (134A) disposed in the first region (annotated FIGs. 12 and 16, above).
But, Applicant may argue that Frougier does not appear to explicitly disclose, wherein the gate dielectric layer extends between source/drain regions on opposing sides of the first nanosheet channel layer and the second nanosheet channel layer.
However, in analogous art, Fan discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor structure (200; FIG. 12; [0013]) may include inner spacers (inner spacers (232a-232c); FIG. 8; ([0028]) between channel layers (channel layers (208a-208c); FIG. 8; [0041]) to isolate conductive gate layers (conductive gate layers (242); FIG. 12; [0018]) from source/drain regions (source/drain regions (228); FIG. 8; [0026] ) ([0011]). Fan also discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that these inner spacer features (232a-232c) may include a dielectric material ([0011]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Frougier and Fan before him/her to extend the gate dielectric layer (134A) of Frougier between source/drain regions (118) on opposing sides of first nanosheet channel layer (108A) and second nanosheet channel layer (108B) to isolate conductive gate layer (134B) from source/drain regions (118) of Frogier, as taught by Fan, thereby enhancing manufacturing efficiency by eliminating the need to fabricate separate dielectric spacers which saves manufacturing time and expense. Please see, MPEP 2143(G), above.
Response to Amendments and Arguments
Applicant’s amendment of claims 1 and 17 and arguments on pages five (5)-six (6) of the “AMENDMENT AND RESPONSE TO OFFICE ACTION” filed on August 4, 2026 (hereinafter the “Response”) have been considered by the Examiner. However, they are unpersuasive for at least the following reasons.
As an example, page five (5) of the Response states:
With regard to the § 102 rejection, it is well established that "unless a reference discloses within the four corners of the document not only all of the limitations claimed but also all of the limitations arranged or combined in the same way as recited in the claim, it cannot be said to prove prior invention of the thing claimed and, thus, cannot anticipate under 35 U.S.C. §102." Net MoneyIN Inc. v. VeriSign Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008) (emphasis added). See also Crown Packaging Technology, Inc. v. Ball Metal Beverage Container Corporation, 635 F.3d 1373, 1383 (Fed. Cir. 2011) ("[D]isclosure of each element is not quite enough" because "[a]nticipation requires the presence in a single prior art disclosure of all elements of a claimed invention arranged as in the claim.") (emphasis in original, internal citations omitted). Applicant respectfully traverses the § 102 rejection on the ground that Frougier fails to expressly or inherently teach each and every limitation of claims 1 and 17 as originally presented.
For example, Frougier does not disclose a gate dielectric layer disposed in the first region and the second region, wherein the gate dielectric layer pinches off the second region. Frougier does not disclose gate dielectric material in the second region.
The Examiner respectfully submits that this argument is just a conclusory statement with no explanation provided as to why Applicant thinks that Frougier neither discloses (i) a gate dielectric layer disposed in the first region and the second region, wherein the gate dielectric layer pinches off the second region nor (ii) gate dielectric material in the second region. To advance prosecution, the Examiner respectfully requests that Applicant please explain in detail why the previous mapping of claims 1 and 17 in the Office Action dated June 16, 2026 failed to establish that Frogier discloses this recited structure.
As another example, pages five (5)-six (6) of the Response state:
Notwithstanding the foregoing traversal, Applicant has chosen to amend independent claim 1 without prejudice solely in order to further clarify the claimed subject matter so as to expedite prosecution of the present application. The amendments herein are not made for reasons relating to patentability over Frougier as the claims as originally filed are believed to recite patentable subject matter over this reference.
In particular, claim 1 has been amended to recite as follows:
A semiconductor device, comprising:
a first nanosheet channel layer having a first middle portion and first outer portions;
a second nanosheet channel layer disposed over the first nanosheet channel layer, the second nanosheet channel layer having a second middle portion and second outer portions, wherein a first distance between the first middle portion and the second middle portion defines a first region and a second distance between the first outer portions and the second outer portions defines a second region, wherein the second distance is less than the first distance;
a gate dielectric layer disposed in the first region and the second region, wherein the gate dielectric layer pinches off the second region and extends between source/drain regions on opposing sides of the first nanosheet channel layer and the second nanosheet channel layer; and
a conductive gate layer disposed on the gate dielectric layer disposed in the first region.
The Examiner respectfully submits, that this argument provides no explanation as to why Applicant thinks that Frougier fails to disclose the added recited limitation of “and extends between source/drain regions on opposing sides of the first nanosheet channel layer and the second nanosheet channel layer” which has been mapped in this Final Office Action. To advance prosecution, the Examiner respectfully requests that Applicant please explain in detail why this added limitation is not disclosed in the prior art of record, as detailed in this Final Office Action.
As an additional example, page six (6) of the Response states: “Moreover, one or more of the dependent claims are also believed to recite separately patentable subject matter.” The Examiner respectfully submits that this argument provides no explanation which dependent claim(s) Applicant thinks recite separately patentable subject matter and why Applicant has reached this conclusion.
Notwithstanding the above, to advance prosecution, the Examiner respectfully requests that Applicant please consider scheduling an interview with the Examiner to discuss its further proposed claim amendments and why they overcome the rejections in this Final Office Action prior to filing a written response to it. For example, perhaps Applicant could further amend claims 1 and 17 to recite that the gate dielectric layer directly contacts source/drain regions on opposing sides of the first nanosheet channel layer and the second nanosheet channel layer, and also distinguish such further amended claims from the combination of Frogier in view of Fan, as detailed in this Final Office Action. The Examiner would welcome a discussion of such further proposed claim amendments and is available at the number provided below.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this Final Office Action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this Final Office Action and the Advisory Action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the Advisory Action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the Advisory Action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this Final Office Action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 Second region (annotated FIG. 12, above, and annotated FIG. 16, below) is between adjacent outer portions of each of the nanosheet channel layers (108A and 108B), is fully filled with gate dielectric layer (134A), and has an absence of a conductive gate layer (134B). Please see, paragraph [0058] of Applicant’s application regarding the meaning of “pinch off”.
2 Second region (annotated FIGs. 12 and 16, above) is between adjacent outer portions of each of the nanosheet channel layers (108A and 108B), is fully filled with gate dielectric layer (134A), and has an absence of a conductive gate layer (134B).
3 Second region (annotated FIGs. 12 and 16, above) is between adjacent outer portions of each of the nanosheet channel layers (108A and 108B), is fully filled with gate dielectric layer (134A), and has an absence of a conductive gate layer (134B).
4 Second region (annotated FIGs. 12 and 16, above) is between adjacent outer portions of each of the nanosheet channel layers (108A and 108B), is fully filled with gate dielectric layer (134A), and has an absence of a conductive gate layer (134B).
Prosecution Insights