Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment August 25th, 2026 has been entered. Claims 1-10, 13-20, and 22-23 are pending in this application. Applicant amended independent claim 20 to remove the term “bits” from the previously recited “first copy of a codeword bits.” New claims 22 and 23 have been added. Claims 11 and 21 have been canceled.
Applicant’s amendments to the claims have been fully considered. The rejection of claim 20 under 35 USC § 103 is maintained for the reasons set forth below.
New claim 22 has been considered and is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
New claim 23 has been considered and is rejected under 35 USC § 103 as set forth below.
Response to Arguments
Applicant's arguments filed August 25th, 2026 have been fully considered but they are not persuasive.
Applicant argues that Freikorn et al. (US 10,496,484), hereinafter Freikorn, does not teach the claimed match bit because the comparison performed by comparator 156 is used internally to determine whether the data is valid, and that Selinger (US 2011/0041005) does not cure the deficiency because its status bit is based on error analysis rather than a comparison between first and second copies of a codeword. Applicant further argues that there would have been no motivation to communicate Freikorn’s internal comparison result to the host.
The rejection relies on the combined teachings of Freikorn and Selinger. Freikorn teaches comparing information associated with first and second copies and using the comparison to determine whether the data is valid or corrupted. Selinger teaches representing results of error analysis using status information, including a status bit, and communicating this status information to a host. Therefore, it would have been obvious to represent Freikorn’s match/non-match determination as a bit and communicate the resulting match/error status to the host, as taught by Selinger, to provide the host with information regarding the validity of the data. Also, the proposed combination does not require changing Freikorn’s internal recovery mechanism or requiring the host to retransmit the data. Instead, Selinger is relied upon for additionally communicating the resulting status information to the host. Therefore, Applicant’s arguments do not overcome the rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Freikorn, in view of Selinger.
Regarding claim 1, Freikorn teaches a method, comprising:
a first copy of a codeword (Freikorn, Fig. 1 teaches data 181 with parity 191 in volatile memory 144) and a second copy of the codeword (Freikorn, Fig. 1 teaches data copy 182 with parity copy 192 in volatile memory 144); and
comparing, based at least in part on reading the first copy of the codeword and the second copy of the codeword, a portion of the first copy of the codeword with a portion of the second copy of the codeword (Freikorn, col. 10, lines 20-23, “The comparator 156 may compare the generated parity 195 to the parity copy 192, to the parity 194, or both. If the comparator 156 detects a match, the data copy 182 may be considered valid”; Fig. 3, block 306 teaches an operation that includes “comparing first redundancy data corresponding to the first copy of the data to second redundancy data corresponding to the second copy of the data”).
Freikorn fails to teach reading, from memory; generating, based at least in part on the comparison, a match bit that indicates whether the portion of the first copy of the codeword matches the portion of the second copy of the codeword; and communicating, to a host device: the match bit, or an error status of the first copy of the codeword that is based at least in part on the match bit.
However, Selinger, in an analogous art, teaches reading from memory (Selinger, Fig. 6 teaches receiving a read command from host in step 610, then reading data and error correction code form the memory in step 620); generating, based at least in part on the comparison, a match bit that indicates whether the portion of the first copy of the codeword matches the portion of the second copy of the codeword (Selinger, Fig. 8A teaches a status bit 806; para. [0072], lines 14-19, “This status bit 806 may be a binary success or failure indication for use by the host 720. The status bit 806 would not necessarily differentiate between the type or extent of read error, but would provide a flag to the host 720 alerting it that some form of error had been encountered”); and communicating, to a host device: the match bit, or an error status of the first copy of the codeword that is based at least in part on the match bit (Selinger, Fig. 10; Abstract, lines 5-12, “a controller receives a command from a host, retrieves data from flash memory, analyzes the retrieved data for errors, and transmits status information to the host, wherein the status information comprises information based on a result of the error analysis, such as a read error. Alternatively, the controller stores the status information and transmits an error indicator to the host identifying that the status information regarding the error is available in memory”). Freikorn teaches generating a match determination/result based on a comparison of redundancy information, and when a match is detected during the comparison, the data copy is considered valid and if a match is not detected, the data copy may be determined to be corrupted. Selinger, however, teaches representing a binary result of an error analysis determination as a status bit, where the status bit may provide binary success/failure determination.
Freikorn and Selinger are both considered to be analogous to the claimed invention because both are in the same field of error detection and reliability within memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Freikorn’s data validity determination to incorporate the teachings of Selinger by including the functionality of the data validity determination being performed in connection with reading data from memory, the result of the match/non-match determination being represented as a bit, and communicating the resulting match/error status to the host.
The suggestion/motivation for doing so would be so that the host may identify an error condition and initiate the appropriate preventative operations, such as data relocation or read scrubbing (Selinger, para. [0071], lines 14-18).
Regarding claim 2, the combination of Freikorn in view of Selinger teaches the method of claim 1, further comprising: receiving, from the host device, a read command for a set of data, wherein a first set of data bits in the first copy of the codeword is representative of the set of data, and wherein a second set of data bits in the second copy of the codeword is representative of the set of data; and communicating, to the host device in response to the read command, the first set of data bits in the first copy of the codeword based at least in part on the error status of the first copy of the codeword (Freikorn, col. 2, lines 35-37, “FIG.1 depicts an illustrative example of a system 100 that includes a data storage device 102 and an access device 170 [e.g., a host device or another device]”; col. 4, lines 36-43, "The access device 170 may issue one or more commands to the data storage device 102, such as one or more requests to erase data, read data from, or write data to the memory device 103 of the data storage device 102. For example, the access device 170 may be configured to provide data, such as data 180, to be stored at the memory device 103 or to request data to be read from the memory device 103").
Regarding claim 3, the combination of Freikorn in view of Selinger teaches the method of claim 1, wherein the portion of the first copy of the codeword comprises first parity bits and the portion of the second copy of the codeword comprises second parity bits (Freikorn, Fig. 1, parity 191 & parity copy 192; col. 6, lines 26-31, "For example, prior to sending the data 180 to the data storage device 102, the access device 170 may process the data 180 to generate a parity 190. The parity 190 includes redundancy data [e.g., a checksum, one or more parity bits, a repetition code, or a hash value, as illustrative, non-limiting examples] that is based on the data 180").
Regarding claim 4, the combination of Freikorn in view of Selinger teaches the method of claim 1, wherein the portion of the first copy of the codeword comprises a first set of data bits and the portion of the second copy of the codeword comprises a second set of data bits (Freikorn, Fig. 1, data 181 & data copy 182).
Regarding claim 5, the combination of Freikorn in view of Selinger teaches the method of claim 1, further comprising: comparing, based at least in part on reading the first copy of the codeword and the second copy of the codeword, a second portion of the first copy of the codeword with a second portion of the second copy of the codeword (Freikorn, Fig. 3, block 306 teaches an operation that includes “comparing first redundancy data corresponding to the first copy of the data to second redundancy data corresponding to the second copy of the data”); and
generating, based at least in part on comparing the second portion of the first copy of the codeword with the second portion of the second copy of the codeword, a second match bit that indicates whether the second portion of the first copy of the codeword matches the second portion of the second copy of the codeword, wherein the error status of the first copy of the codeword is determined based at least in part on the second match bit (Freikorn, Fig. 2 teaches parity comparison to determine if the data and data copies are valid/non-valid). Freikorn does not explicitly teach generating a second match bit corresponding to a second comparison between second portions of the first and second copies of the codeword, however it would have been obvious to one of ordinary skill in the art to perform the comparison operations on additional portions of the stored data/codewords and generate a second match indicator for the additional comparison, as generating separate comparison indicators for portions of data is a known technique in redundancy validation within memory systems.
Regarding claim 6, the combination of Freikorn in view of Selinger teaches the method of claim 5, wherein the portion of the first copy of the codeword comprises a first set of data bits, the portion of the second copy of the codeword comprises a second set of data bits, the second portion of the first copy of the codeword comprises first parity bits, and the second portion of the second copy of the codeword comprises second parity bits (Freikorn, Fig. 1, parity 191 & parity copy 192; col. 6, lines 26-31, "For example, prior to sending the data 180 to the data storage device 102, the access device 170 may process the data 180 to generate a parity 190. The parity 190 includes redundancy data [e.g., a checksum, one or more parity bits, a repetition code, or a hash value, as illustrative, non-limiting examples] that is based on the data 180"). It would have been obvious to perform separate comparison operations on both the data bit and parity bit portions of the first and second copies of the codeword in order to improve the reliability of codeword verification.
Regarding claim 7, the combination of Freikorn in view of Selinger teaches the method of claim 1, further comprising: decoding the first copy of the codeword and the second copy of the codeword, wherein the portion of the first copy of the codeword is compared with the portion of the second copy of the codeword based at least in part on decoding the first copy of the codeword and the second copy of the codeword; and generating an error detection bit for the first copy of the codeword based at least in part on decoding the first copy of the codeword, wherein the error status of the first copy of the codeword is determined based at least in part on the error detection bit (Freikorn, col. 10, lines 17-20, "Validating the data copy 182 may include the encoder 154 (or the encoder 142) accessing the data copy 182 at the volatile memory 144 and processing the data copy 182 to generate the parity 195").
Regarding claim 8, the combination of Freikorn in view of Selinger teaches the method of claim 7, further comprising: correcting an error in the first copy of the codeword based at least in part on decoding the first copy of the codeword, wherein the portion of the first copy of the codeword is compared with the portion of the second copy of the codeword after correcting the error (Freikorn, col. 9, lines 19-23, "The ECC engine 158 may include one or more decoders configured to decode data read from the non-volatile memory 104 to detect and correct, up to an error correction capability of the ECC scheme, any bit errors that may be present in the data").
Regarding claim 9, the combination of Freikorn in view of Selinger teaches the method of claim 1, further comprising: decoding the first copy of the codeword and the second copy of the codeword (Freikorn, Fig. 1, bit error detector 152 performs error detection operations on the stored data copies; error detection operations include decoding) concurrently (Freikorn, Fig. 1 teaches the bit error detector 152 and comparator 156 integrated into the data path protection circuit 148; Freikorn does not explicitly teach “concurrently”, but the integrated bit error detector and comparator suggests parallel operations during the same verification flow) with comparing the portion of the first copy of the codeword with the portion of the second copy of the codeword (Freikorn, Fig. 3, block 306 teaches an operation that includes “comparing first redundancy data corresponding to the first copy of the data to second redundancy data corresponding to the second copy of the data”); and generating an error detection bit for the first copy of the codeword based at least in part on decoding the first copy of the codeword (Freikorn, Fig. 1, bit error detector 152; col. 8, lines 48-52, “the bit error detector 152 is configured to combine the data 184 and the parity 194 into a data word and to process the data word to generate a result [e.g., a syndrome] that indicates whether any bit errors were detected in the data word”), wherein the error status of the first copy of the codeword is determined based at least in part on the error detection bit (Freikorn, Fig. 2 teaches whether the data copy is valid/not valid based on error detection parity comparison bits).
Regarding claim 13, Freikorn teaches a method, comprising:
determining whether a first copy of the codeword matches a portion of a second copy of the codeword (Freikorn, col. 10, lines 20-23, “The comparator 156 may compare the generated parity 195 to the parity copy 192, to the parity 194, or both. If the comparator 156 detects a match, the data copy 182 may be considered valid”; Fig. 3, block 306 teaches an operation that includes “comparing first redundancy data corresponding to the first copy of the data to second redundancy data corresponding to the second copy of the data”); and
determining an error status of the first copy of the codeword based at least in part on the match bit (Freikorn, Fig. 2, blocks 208-212; col. 11, lines 51-65, “Error detection is performed to determine whether the data 184 includes any errors. The error detection may be performed by the data path protection circuit 148 of FIG. 1. For example, the encoder 154 may process the data 184 to generate parity P2 204, at 208. A determination of whether the parity P2 204 matches the parity P1 202 may be made, at 210. For example, the comparator 156 of FIG. 1 may compare the parity P2 204 to the parity P1 202. The parity P1 202 may correspond to the parity 194 of FIG. 1 that accompanies the data 184 through the data path 146. Alternatively, the parity P1 202 may correspond to the parity 191 transferred to the data path protection circuit 148 (e.g., bypassing the data path 146). When the parity P1 202 matches the parity P2 204, the data 184 may be considered valid, at 212”).
Freikorn fails to teach transmitting a read command for a set of data that is associated with a codeword and receiving, based at least in part on transmitting the read command, a match bit.
However, Selinger, in an analogous art, teaches transmitting a read command for a set of data that is associated with a codeword (Selinger, Fig. 6, step 610-620; Fig. 10, steps 1002-1006; para. [0065], lines 1-6, “Turning now in FIG. 6, flow chart 600 illustrates how the controller 400 is used in a read operation. As shown in FIG. 6, the controller 400 receives a read command from the host 420 [act 610]. The controller 400 then reads data and an error correction code associated with the data from the flash memory device(s) 430 [act 620]”); and
receiving, based at least in part on transmitting the read command, a match bit (Selinger, Fig. 8A teaches a status bit 806; para. [0072], lines 14-19, “This status bit 806 may be a binary success or failure indication for use by the host 720. The status bit 806 would not necessarily differentiate between the type or extent of read error, but would provide a flag to the host 720 alerting it that some form of error had been encountered”). Freikorn does not explicitly teach representing the match determination as a match bit or receiving that bit in response to a transmitted host read command. Freikorn teaches generating a match determination/result based on a comparison of redundancy information, and when a match is detected during the comparison, the data copy is considered valid and if a match is not detected, the data copy may be determined to be corrupted. Selinger, however, teaches representing a binary result of an error analysis determination as a status bit, where the status bit may provide binary success/failure determination.
Freikorn and Selinger are both considered to be analogous to the claimed invention because both are in the same field of error detection and reliability within memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Freikorn’s data validity determination to incorporate the teachings of Selinger by including the functionality of the comparison and data validity determination being performed in connection with a read command initiated by a host and the resulting match determination is represented as a bit and returned to the host.
The suggestion/motivation for doing so would be to provide the host with information that indicates the validity/integrity of the requested data and allowing the host to identify and respond to an error condition (Selinger, para. [0071], lines 14-18).
Regarding claim 14, the combination of Freikorn in view of Selinger teaches the method of claim 13, further comprising: receiving, based at least in part on transmitting the read command, a second match bit (Selinger, Fig. 6, steps 630 through 670; the result from the comparison at step 640 equates to a match bit) that indicates whether a second portion of the first copy of the codeword matches a second portion of the second copy of the codeword (Freikorn, Fig. 3, block 306 teaches an operation that includes “comparing first redundancy data corresponding to the first copy of the data to second redundancy data corresponding to the second copy of the data”; Fig. 2 teaches parity comparison to determine if the data and data copies are valid/non-valid). The references do not explicitly teach receiving a second match bit corresponding to a second comparison between second portions of the first and second copies of the codeword, however it would have been obvious to one of ordinary skill in the art to perform an additional comparison on an additional portion of data and generate a second comparison result for separate portions of the data.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Freikorn to incorporate the teachings of Selinger by including the functionality of the comparison and data validity determination being performed in connection with a read command initiated by a host and the resulting match determination is represented as a bit and returned to the host.
The suggestion/motivation for doing so would be to provide the host with information that indicates the validity/integrity of the requested data and allowing the host to identify and respond to an error condition (Selinger, para. [0071], lines 14-18).
Regarding claim 15, the combination of Freikorn in view of Selinger teaches the method of claim 14, wherein the portion of the first copy of the codeword comprises a first set of data bits, the portion of the second copy of the codeword comprises a second set of data bits, the second portion of the first copy of the codeword comprises a first set of parity bits, and the second portion of the second copy of the codeword comprises a second set of parity bits (Freikorn, Fig. 1, parity 191 & parity copy 192; col. 6, lines 26-31, "For example, prior to sending the data 180 to the data storage device 102, the access device 170 may process the data 180 to generate a parity 190. The parity 190 includes redundancy data [e.g., a checksum, one or more parity bits, a repetition code, or a hash value, as illustrative, non-limiting examples] that is based on the data 180").
Regarding claim 16, the combination of Freikorn in view of Selinger teaches the method of claim 13, further comprising: receiving, based at least in part on transmitting the read command (Selinger, Fig. 6, step 618), an error detection bit that indicates whether a memory device detected an error in the first copy of the codeword (Selinger, Fig. 6, step 620), wherein the error status is determined based at least in part on the error detection bit (Selinger, Fig. 6, steps 630 through 670).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Freikorn to incorporate the teachings of Selinger by including the functionality of the comparison and data validity determination being performed in connection with a read command initiated by a host and the resulting match determination is represented as an error correction bit.
The suggestion/motivation for doing so would be to provide the host with information that indicates the validity/integrity of the requested data and allowing the host to identify and respond to an error condition (Selinger, para. [0071], lines 14-18).
Regarding claim 17, the combination of Freikorn in view of Selinger teaches the method of claim 13, wherein the portion of the first copy of the codeword comprises a first set of data bits and the portion of the second copy of the codeword comprises a second set of data bits (Freikorn, Fig. 1, data 181 & data copy 182), the method further comprising: receiving, based at least in part on transmitting the read command (Selinger, Fig. 6, step 618), a second match bit (Selinger, Fig. 6, steps 630 through 670; the result from the comparison at step 640 equates to a match bit) that indicates whether a first set of parity bits in the first copy of the codeword matches a second set of parity bits in the second copy of the codeword (Freikorn, Fig. 1, parity 191 & parity copy 192 combined with Selinger’s teachings of match/non-match determination [Selinger, Fig. 6, steps 630 through 670]), wherein the error status of the first copy of the codeword is determined based at least in part on the second match bit (Selinger, para. [0065], lines 23-25, “If the correction does not succeed, a signal can be sent to the host 420 indicating that a storage error occurred”). The references do not explicitly teach receiving a second match bit corresponding to a second comparison between second portions of the first and second copies of the codeword, however it would have been obvious to one of ordinary skill in the art to perform an additional comparison on an additional portion of data and generate a second comparison result for separate portions of the data.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Freikorn to incorporate the teachings of Selinger by including the functionality of performing an additional comparison and generating corresponding comparison results.
The suggestion/motivation for doing so would be to allow for a more granular level of data verification.
Regarding claim 18, the combination of Freikorn in view of Selinger teaches the method of claim 13, wherein the portion of the first copy of the codeword comprises a first set of parity bits and the portion of the second copy of the codeword comprises a second set of parity bits (Freikorn, Fig. 1, parity 191 & parity copy 192), the method further comprising: receiving, based at least in part on transmitting the read command (Selinger, Fig. 6, step 618), a second match bit (Selinger, Fig. 6, steps 630 through 670; the result from the comparison at step 640 equates to a match bit) that indicates whether the first set of parity bits in the first copy of the codeword matches the second set of parity bits in the second copy of the codeword (Freikorn, Fig. 1, parity 191 & parity copy 192 combined with Selinger’s teachings of match/non-match determination [Selinger, Fig. 6, steps 630 through 670]), wherein the error status of the first copy of the codeword is determined based at least in part on the second match bit (Selinger, para. [0065], lines 23-25, “If the correction does not succeed, a signal can be sent to the host 420 indicating that a storage error occurred”). The references do not explicitly teach receiving a second match bit corresponding to a second comparison between second portions of the first and second copies of the codeword, however it would have been obvious to one of ordinary skill in the art to perform an additional comparison on an additional portion of data and generate a second comparison result for separate portions of the data.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Freikorn to incorporate the teachings of Selinger by including the functionality of performing an additional comparison and generating corresponding comparison results.
The suggestion/motivation for doing so would be to allow for a more granular level of data verification.
Regarding claim 19, the combination of Freikorn in view of Selinger teaches the method of claim 13, further comprising: receiving the set of data based at least in part on transmitting the read command (Selinger, Fig. 6, step 610 & 620); and determining that the set of data is error-free (Selinger, Fig. 6, step 640) based at least in part on the error status (Selinger, para. [0065], lines 23-25, “If the correction does not succeed, a signal can be sent to the host 420 indicating that a storage error occurred”) of the first copy of the codeword (Freikorn, Fig. 2 teaches parity comparison to determine if the data and data copies are valid/non-valid; the reference does not explicitly teach a “match bit”, however the parity comparison result inherently corresponds to some sort of match indication or status bit/flag).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Selinger’s teachings of a comparison result and error status determination to incorporate the teachings of Freikorn by including the functionality of redundant copy comparison.
The suggestion/motivation for doing so would improve the system’s ability to identify errors.
Claim 20 is a memory system with limitations similar to the method of claim 1, and is rejected under the same rationale.
Claims 10 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Freikorn in view of Selinger, as applied to claim 1 above, and further in view of Tian et al. (US 2015/0121132), hereinafter Tian.
Regarding claim 10, the combination of Freikorn in view of Selinger teaches the method of claim 1, but fails to teach further comprising: generating, based at least in part on reading the first copy of the codeword, a first error detection bit that indicates whether an error has been detected in the first copy of the codeword, wherein the error status of the first copy of the codeword is based at least in part on the first error detection bit; and generating, based at least in part on reading the second copy of the codeword, a second error detection bit that indicates whether an error has been detected in the second copy of the codeword, wherein an error status of the second copy of the codeword is based at least in part on the match bit and the second error detection bit.
However, Tian, in an analogous art, teaches further comprising: generating, based at least in part on reading the first copy of the codeword, a first error detection bit that indicates whether an error has been detected in the first copy of the codeword, wherein the error status of the first copy of the codeword is based at least in part on the first error detection bit; and generating, based at least in part on reading the second copy of the codeword, a second error detection bit that indicates whether an error has been detected in the second copy of the codeword, wherein an error status of the second copy of the codeword is based at least in part on the match bit and the second error detection bit (Tian, para. [0030], lines 1-4, "Respective parity values of the first and second copies of the data are generated (208). For example, parity computing circuits 120 and 122 (FIG. 1) determine the respective parity values of the first and second copies of the data").
Freikorn, Selinger, and Tian are considered to be analogous to the claimed invention because they are in the same field of error detection and correction in memory systems and/or devices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Freikorn in view of Selinger to incorporate the teachings of Tian by including the functionality of generating first and second error detection bits, with error statuses that are both based in part on match bits & error detection bits of the first and second copies of the codeword.
The suggestion/motivation for doing so would be to flag or identify whether an error is present in the data, which is a common practice in the field of error detection & correction.
Regarding claim 23, the combination of Freikorn in view of Selinger teaches the method of claim 1, but fails to teach wherein the first copy of the codeword is stored in a first section of a memory array of the memory and the second copy of the codeword is stored in a second section of the memory array.
However, Tian teaches wherein the first copy of the codeword is stored in a first section of a memory array of the memory and the second copy of the codeword is stored in a second section of the memory array (Tian, Fig. 1; para. [0015] & para. [0028] teaches storing a first copy of data in a first register element and storing a second copy of the data in a second register element).
Freikorn, Selinger, and Tian are considered to be analogous to the claimed invention because they are in the same field of error detection and correction in memory systems and/or devices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Freikorn in view of Selinger to incorporate the teachings of Tian by including the functionality of the first copy of the codeword is stored in a first section of memory and the second copy of the codeword is stored in a second section of the memory.
The suggestion/motivation for doing so would be provide separate storage for redundant copies of the data and allow for an uncorrupted copy of data to be used when one of the stored copies of data is corrupted.
Allowable Subject Matter
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kedem (US 6,195,761) teaches comparing corresponding data of redundant copies and determining validity based upon mismatching between the copies.
Kedem (US 6,233,696) teaches verification and repair of redundant stored data and determining whether redundant copies are consistent.
Tremblay et al. (US 6,728,898) teaches mirrored data storage and identifying divergence between redundant copies.
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/G.V.B./Examiner, Art Unit 2112
/ESAW T ABRAHAM/Primary Examiner, Art Unit 2112
