Prosecution Insights
Last updated: August 17, 2026
Application No. 18/608,463

PHYSICAL DOWNLINK CONTROL CHANNEL SOFT-COMBINING

Final Rejection §103
Filed
Mar 18, 2024
Examiner
JAIN, RAJ K
Art Unit
2411
Tech Center
2400 — Computer Networks
Assignee
Qualcomm Incorporated
OA Round
2 (Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
728 granted / 830 resolved
+29.7% vs TC avg
Moderate +8% lift
Without
With
+7.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
23 currently pending
Career history
869
Total Applications
across all art units

Statute-Specific Performance

§101
5.7%
-34.3% vs TC avg
§103
51.1%
+11.1% vs TC avg
§102
19.9%
-20.1% vs TC avg
§112
15.4%
-24.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 830 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1,3-13,15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over FAXÉR et al (US 20200382256 A1) hereinafter as FAXÉR in view of Huang et al (US 20220369352 A1) hereinafter as Huang. Regarding claim(s) 1,10,13, FAXÉR discloses an apparatus, comprising: one or more memories; and one or more processors being configured to, individually or collectively, based at least in part on information stored in the one or more memories ((See Fig(s). 5, host 24 with memory 46, processor 44), receive a plurality of physical downlink control channels (PDCCHs) corresponding to a plurality of physical downlink shared channels (PDSCHs), each of the plurality of PDCCHs conveying a respective downlink control information (DCI) scheduling a respective one of the plurality of PDSCHs, each of the plurality of PDSCHs associated with an actual redundancy version value of a set of redundancy version values, wherein the respective DCI (See Fig(s). 3, See ¶ 8,49, A wireless device first decodes a PDCCH and if a PDCCH is decoded successfully, it then decodes the corresponding PDSCH based on the decoded DCI in the PDCCH…. See ¶ 63,66, 185, the processing circuitry is further configured to set a redundancy version field to a predefined value as part of the indication, for CSI reporting, of the configuration of the PUSCH without the associated shared channel data.); omits an indication of the actual redundancy version value, and the one or more processors are further configured to obtain the actual redundancy version value based on a predetermined deterministic function (See ¶ 64, 70, 186, the indication, for CSI reporting, of the configuration of the PUSCH without the associated shared channel data is indicated in downlink control information, DCI, that is configured to omit an indication of a transport block size for the shared channel data.). Faxer further discloses the one or more processors are further configured to: store the plurality of PDCCHs corresponding to the plurality of PDSCHs corresponding to the set of redundancy version values in the one or more memories See Fig(s). 5, host 24 with memory 46, processor 44 for storage of redundancy versions). FAXÉR fails to disclose an indicated redundancy version value, and the one or more processors are further configured includes a redundancy version pattern indicator value, and the one or more processors are further configured to identify one of at least two sequences of the actual redundancy version value based on the redundancy version pattern indicator value, soft combine the stored plurality of PDCCHs to produce a soft combined PDCCH; and decode a soft combined DCI of the soft combined PDCCH. Huang discloses includes an indicated redundancy version value, and the one or more processors are further configured includes a redundancy version pattern indicator value, and the one or more processors are further configured to identify one of at least two sequences of the actual redundancy version value based on the redundancy version pattern indicator value (See ¶ 79, A UE determines a PDCCH monitoring occasion on an active DL BWP from the PDCCH monitoring periodicity, the PDCCH monitoring offset, and the PDCCH monitoring pattern within a slot. … See ¶ 290, In some aspects concurrent channels may be established based on pulse position or offsets. In some aspects concurrent channels may be established based on time hopping sequences. In some aspects concurrent channels may be established based on pulse repetition frequencies, pulse positions or offsets, and time hopping sequences.) ; soft combine the stored plurality of PDCCHs to produce a soft combined PDCCH; and decode a soft combined DCI of the soft combined PDCCH (See ¶ 217, 225-227, for a pair of PDCCH candidates comprising PDCCH1 and PDCCH2, UE may perform soft-combining for the pair of PDCCH candidates.). Soft combining of PDCCH allows for scheduling using same PDSCH with same DCI format and thus reducing overall bandwidth usage. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate the teachings of Huang within FAXÉR, so as to improve bandwidth efficiency. Claim(s) 2,14, is/are rejected under 35 U.S.C. 103 as being unpatentable over FAXÉR et al (US 20200382256 A1) hereinafter as FAXÉR in view of Huang et al (US 20220369352 A1) hereinafter as Huang, further in view of Reial et al (US 20210185683 A1 hereinafter as Reial. Regarding claim(s) 2,14, Reial discloses wherein in an instance where the respective DCI omits the indication of the actual redundancy version value, the one or more processors are further configured to recognize that all DCI scheduling the plurality of PDSCHs within a given remaining minimum system information (RMSI) transmission time interval (TTI) are identical (See Fig(s). 2, See ¶ 44. The PBCH also informs the UE about the RMSI numerology. FIG. 2 shows an example of a Synchronization Signal Block (SSB) and RMSI transmission. In this example, the UE receives at least one SS Block and at least one redundancy version (RV) of the NR-PDSCH every 20 ms, while the Transmission Time Interval (TTI) of the RMSI is, e.g., 80 ms.). RMSI maintains the critical system information with Synchronization Signal (SS) block. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate the teachings of Reial within FAXÉR, so RMSI maintains the critical system information with Synchronization Signal (SS) block between devices of interest to optimize device synchronization timing. Regarding claim(s) 3,15, FAXÉR discloses wherein the predetermined deterministic function yields the actual redundancy version value based on a location in time of the respective one of the plurality of PDSCHs (See ¶ 63, the processing circuitry is further configured to set a redundancy version field to a predefined value as part of the indication, for CSI reporting, of the configuration of the PUSCH without the associated shared channel data.). Regarding claim(s) 4,11,16, FAXÉR discloses wherein the predetermined deterministic function maps a system frame number to the actual redundancy version value (See ¶ 66). Regarding claim(s) 5,17, FAXÉR discloses wherein the predetermined deterministic function is a modulo operation that is a function of a system frame number and a quantity of all elements of the set of redundancy version values (See ¶ 189, According to one or more embodiments, the processing circuitry 68 is further configured to set a redundancy version field to a predefined value as part of the indication, for CSI reporting, of the configuration of the PUSCH without the associated shared channel data.). Regarding claim(s) 6,18, Huang discloses wherein the system frame number is a first system frame number of a given PDCCH or a second system frame number of a given PDSCH, and the first system frame number is different from the second system frame number (See ¶ 79). Reasons for combining same as claim 1. Regarding claim(s) 7,19, Huang discloses wherein in an instance where the respective DCI includes the indicated redundancy version value, the one or more processors are further configured to at least one of: utilize a cyclic function to map the indicated redundancy version value to the actual redundancy version value, or utilize a table that stores the indicated redundancy version value and a corresponding actual redundancy version value to map the indicated redundancy version value to the actual redundancy version value (See ¶ 56,Table 7.3.1.1). Reasons for combining same as claim 1. Regarding claim(s) 8,12,20, Huang discloses wherein in an instance where the respective DCI includes the redundancy version pattern indicator value, the redundancy version pattern indicator value indicates one of a predetermined plurality of redundancy version patterns for a corresponding plurality of use cases (See ¶ 79, A UE determines a PDCCH monitoring occasion on an active DL BWP from the PDCCH monitoring periodicity, the PDCCH monitoring offset, and the PDCCH monitoring pattern within a slot. . Reasons for combining same as claim 1. Regarding claim(s) 9, FAXÉR discloses wherein the one or more processors are further configured to: store the plurality of PDSCHs associated with the set of redundancy version values in the one or more memories See Fig(s). 5, host 24 with memory 46, processor 44),; Huang discloses soft combine the plurality of PDSCHs stored in the one or more memories, based on the actual redundancy version value respectively attributed to each of the plurality of PDSCHs stored in the one or more memories, to produce a soft combined PDSCH (See ¶ 217, 225-227, for a pair of PDCCH candidates comprising PDCCH1 and PDCCH2, UE may perform soft-combining for the pair of PDCCH candidates. For non-pair of PDCCH candidates, UE may not perform soft-combining for two PDCCH candidates.). and Reial discloses decode a soft combined remaining minimum system information (RMSI) and/or other system information (OSI) of the soft combined PDSCH (See Fig(s). 2, See ¶ 44. The PBCH also informs the UE about the RMSI numerology. FIG. 2 shows an example of a Synchronization Signal Block (SSB) and RMSI transmission. In this example, the UE receives at least one SS Block and at least one redundancy version (RV) of the NR-PDSCH every 20 ms, while the Transmission Time Interval (TTI) of the RMSI is, e.g., 80 ms.). Reasons for combining same as claim 2. Response to Arguments Applicant's arguments filed June 17, 2026 have been fully considered but they are not persuasive. With respect to 35 U.S.C. § 103 rejection of Claim(s) 1-20, Applicant contends inter alia “…The passages of Faxer cited by the Office concern different signaling, including CSI reporting and PUSCH configuration. The cited passages do not teach or suggest the signaling or the soft-combining architecture …” Examiner respectfully disagrees, First off Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. Second, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Examiner asserts Faxer clearly and explicitly recites DCI signaling through out the reference aside from PUSCH Faxer describes DCI within the PDCCH (See ¶ 7-8, NR supports “slot based” transmission. In each slot, the gNB transmits downlink control information (DCI) about which wireless device data is to be transmitted to and what resources in the current downlink subframe the data is transmitted on. The DCI is carried on the Physical Control Channel (PDCCH)..further See Fig(s). 4 network node 16 is configured with DCI 32 unit for indication of downlink control information See ¶ 160. The use of PDCCH is in control resource sets and one of skill in the art fully appreciates that COREsets is a configurable set of time–frequency resources where the PDCCH) can be transmitted. It defines the location and size of the area in the downlink resource grid where UEs look for Downlink Control Information (DCI).). With respect to soft combining, Huang discloses soft combining the stored plurality of PDCCHs to produce a soft combined PDCCH; and decode a soft combined DCI of the soft combined PDCCH (See ¶ 217, 225-227, for a pair of PDCCH candidates comprising PDCCH1 and PDCCH2, UE may perform soft-combining for the pair of PDCCH candidates.). Again, Soft combining of PDCCH allows for scheduling using same PDSCH with same DCI format and thus reducing overall bandwidth usage. Further, In response to applicant's argument that Faxer and Huang are unrelated disclosures, it should be noted the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Applicant further contends inter alai “..downlink control information (DCI) scheduling a respective one of the plurality of PDSCHs, and each of the plurality of PDSCHs is associated with an actual redundancy version value of a set of redundancy version values" where the redundancy version handling is accomplished by one of three alternative mechanisms: omission of an redundancy version indication with deterministic derivation, inclusion of an indicated redundancy version mapped via a predetermined sequence, or inclusion of an redundancy version pattern indicator selecting among multiple redundancy version sequences. The cited art does not teach or suggest this integrated framework…”. Examiner asserts the redundancy version to which applicant is eluding to only requires one of three mechanisms, with that stated Examiner points to Huang as teaching the redundancy version pattern indicator value (See ¶ 79, A UE determines a PDCCH monitoring occasion on an active DL BWP from the PDCCH monitoring periodicity, the PDCCH monitoring offset, and the PDCCH monitoring pattern within a slot. … See ¶ 290, In some aspects concurrent channels may be established based on pulse position or offsets. In some aspects concurrent channels may be established based on time hopping sequences. In some aspects concurrent channels may be established based on pulse repetition frequencies, pulse positions or offsets, and time hopping sequences.). Once again test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). While Examiner believes all of Applicant’s contentions have been appropriately addressed in this Office Action, however, failure to address a specific issue or comment, does not signify agreement with or concession of that issue or comment. Finally, the arguments made above are not intended to be exhaustive, and therefore nothing in this Action should be construed as an intent to concede with any issue with regard to any claim, except as specifically stated in this Office Action. Thus, based on the foregoing reasoning’s’ Examiner asserts the cited references either alone or in combination teach/suggest limitations of claims 1-20 and therefore the rejection to said claims is sustained. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAJ JAIN whose telephone number is (571)-272-3145. The examiner can normally be reached on M-Th 8-5. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Derrick Ferris can be reached 571-272-2123. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center for authorized users only. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form. /RAJ JAIN/ Primary Examiner, Art Unit 2411
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Prosecution Timeline

Mar 18, 2024
Application Filed
Mar 19, 2026
Non-Final Rejection mailed — §103
Jun 17, 2026
Response Filed
Aug 06, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
95%
With Interview (+7.6%)
2y 10m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 830 resolved cases by this examiner. Grant probability derived from career allowance rate.

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