Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
As per the instant application having Application No. 18/608,591, the amendment filed on 5/4/2026 is herein acknowledged. Claims 2, 6, 11, 17 and 20-22 have been amended and claims 24-26 have been added. Claims 1, 4, 13-16, 18 and 23 have been canceled. Claims 2-3, 5-12, 17, 19-22 and 24-26 are pending.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
TERMINAL DISCLAIMER
The terminal disclaimer filed on 9/12/2025 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US 11,947,841 has been reviewed and is accepted. The terminal disclaimer has been recorded.
OBJECTIONS
Claim Objections
Claim 21 is objected to because of the following informalities: As per claim 21, the limitations “a first set of bits that associated” (line 6) should be corrected to read “a first set of bits associated” or “a first set of bits that are associated”. Appropriate correction is required.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 6, 12, 21-22 and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Cheong et al. (US 5,533,189) in view of White et al. (US 5,696,937) and Loffer et al. (US 6,032,233).
2. (New) A method, comprising: decoding, by a decoder, an address of a memory array; [Cheong teaches “a directory of cache or memory (a memory directory is used in the shared global memory in multiprocessor systems) contains an array of entries that correspond one-to-one to data entries in the cache or the memory data array. “ (col. 1, lines 12-17) “A request is first decoded in the first stage while the directory is looked up by the index portion of the address. This is the directory access/request decode stage 31.” (col. 2, lines 38-42) “the address tag is in the input tag, and is available in stage 31” (Col. 5, lines 33-35) “A request is received by stage 31, decoded and passed to stage 32a” (col. 5, lines 50-51)]
reading a first set of bits associated with the address, wherein each bit of the first set of bits indicates access information for one or more respective addresses; [Cheong teaches “An updated directory entry requiring a new ECC most often only requires a portion of the entry updated. When an existing directory entry is modified, only the status bits are changed and the address tag read from directory 30 stay unchanged” (col. 5, lines 24-29) where “The status bits include a valid bit, value 1 of which indicates that the data entry is a valid one and value 0 otherwise. The status bits also may include a modified (dirty) bit which indicates whether the valid data entry contains a new value. When the bit has value 1, the entry has a new value which will be written back to the next lower level of memory hierarchy when the data entry is evicted to make room for a data entry of a new address. Status bits also may, depending on machine organization, include other bits such as "exclusive bit" or "inclusion bits" which are primarily used in multiple processor systems.” (col. 1, lines 25-35), the status bits are interpreted to correspond to the claimed first set of bits]
generating, by the decoder, a second set of bits that indicates updated information corresponding to whether the address has been accessed; [Cheong teaches “Tag will be 37 bits. Compared to normally 5 status bits (1 valid, 4 MESI) bits used in a typical multiprocessor coherence protocol), the number of address tag bits is much larger than the number of status bits. Thus, ECC generation can be distributed among the tag portion and the status portion of the directory entry” (col. 5, lines 36-49) “…From the response type from block 15 and the decode request types, block 17 decides which status bits need to be updated. For example, a request that triggers a load of a new data entry from the next lower level of memory will need to set the valid bit. Also, a castout request from the current level of memory will need to clear the valid bit; or, a write from the next higher level cache will set the modify bit. Depending on the complexity of the control logic, in a complex design block 17 may also take the status bits from the entry.sub.-- slct as input in order to generate new values of the status bits.” (col. 5, line 50 – col. 6, line 14) where the updated set of status bits from box 17 in fig. 1B correspond to the claimed second set of bits] but Cheong does not expressly disclose the generating by the decoder
combining the first set of bits with the second set of bits to update the first set of bits and to preserve the access information in one or more bits, of the first set of bits, not updated by the second set of bits; [Cheong teaches “… From the response type from block 15 and the decode request types, block 17 decides which status bits need to be updated (thus, suggesting at least one or more of the status bits may remain unchanged or preserved). For example, a request that triggers a load of a new data entry from the next lower level of memory will need to set the valid bit. Also, a castout request from the current level of memory will need to clear the valid bit; or, a write from the next higher level cache will set the modify bit. Depending on the complexity of the control logic, in a complex design block 17 may also take the status bits from the entry.sub.-- slct as input in order to generate new values of the status bits.” (col. 5, line 50 – col. 6, line 14). Thus, status bits from box 30 in fig. 1A is combined with new status bits generated in box 17 in fig. 1B. Thus combining a first set of status bits from 32A into updated entry at 33A which includes New status (0:j-1). See figs. 1A and 1B and related text. Note that status bits New status (0:j-1) in FIG. 1B corresponds to an updated first set of tag bits as it has updated the status bit portion of the from box 30] but Cheong does not expressly disclose combining the first set of bits with the second set of bits… to preserve the access information in one or more bits, of the first set of bits, not updated by the second set of bits
generating a codeword for the updated first set of bits; and storing the codeword in the memory array [Cheong teaches “ From block 17, the new status bits are inputted into block 18 so that an ECC is generated for the status portion with mxj ECC generation logic circuitry 18. Block 19, which performs an XOR, or sum operation, sums the ECC received from block 16 and the ECC received from block 18 to therefore output the new ECC for the directory entry.” (col. 6, lines 15-20) where the new ECC is stored in the directory (see col. 2, lines 38-67) (figs. 1-2 and related text) where “a directory of cache or memory (a memory directory is used in the shared global memory in multiprocessor systems) contains an array of entries that correspond one-to-one to data entries in the cache or the memory data array.” (col. 1, lines 12-17)]. Thus, a codeword is generated for status bits New status (0:j-1) which corresponds to an updated first set of bits as it has updated the directory array entry from box 30 into an entry having status bits New status (0:j-1). The codeword includes ECC for updated status bit portion from 18, which are used in 19 to generate NEW ECC [See figs. 1A and 1B and related text].
Regarding the generating by the decoder, White teaches [“The tag/status array-decoder block provides a number of functions which: (a) stores the tag address and stores the status and parity information for that address; (b) compares an incoming tag address with the stored address at that index to determine a "HIT"; (c) qualifies a "HIT" as valid by error checking and examining the status bits; (d) provides the bank address when there is a "HIT" and selects the bank for replacement when there is a "miss"; (e) provides new values for the valid bits and the status/tag parity for a status update; (which corresponds to the generating) (f) generates an odd parity for the tag address and status bits which will be stored in the tag/status array.” (col. 8, lines 8-18)].
Cheong and White are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Cheong to have the generating by the decoder as taught by White since doing so would at least provide the benefits of flexibility of design and “in order to provide a rapid invalidation of addresses in a tag/status array-decoder unit” (col. 3, lines 24-40).
The combination of Cheong and White does not expressly disclose combining the first set of bits with the second set of bits… to preserve the access information in one or more bits, of the first set of bits, not updated by the second set of bits; however, regarding these limitations, Loffer teaches [“ In case the entry in column V.sub.a is accessed, the new entry written to column V.sub.a is the entry that has been most recently used, because the latest access to the cache was directed towards column V.sub.a. Therefore, V.sub.a is more recently used than V.sub.b, V.sub.c, and V.sub.d, and therefore, the MRU/LRU status bits X1, X2, and X3 have to be changed accordingly. This implies that X1 has to be set to "EVEN" (800), X2 has to be set to "EVEN" (801), and X3 has to be set to "EVEN" (802) as well. The status bits X4, X5 and X6 do not relate to V.sub.a. Instead, they refer to the relative order of V.sub.b, V.sub.c, and V.sub.d, which is not changed by an access of column V.sub.a. Therefore, the status bits X4, X5 and X6 remain as they are (803, 804, 805), and no changes are made to these status bits.” (col. 10, lines 35-47)].
Cheong, White and Loffer are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong and While to have the combining the first set of bits with the second set of bits to… the access information in one or more bits, of the first set of bits, not updated by the second set of bits as taught by Loffer since doing so would provide the benefits of [“a storage device for keeping status information which is to be updated by multiple access paths which may perform their update simultaneously.” (col. 2, lines 53-57)].
Therefore, it would have been obvious to combine Cheong and White with Loffer for the benefit of creating a storage system/method to obtain the invention as specified in claim 2.
6. The method of claim 2, wherein generating the second set of bits comprises: selecting a value for a bit corresponding to the address, wherein the second set of bits includes the bit [Cheong teaches “… In general, the decoded request type from the decode operation in stage 31 is acted on by block 15… From the response type from block 15 and the decode request types, block 17 decides which status bits need to be updated. For example, a request that triggers a load of a new data entry from the next lower level of memory will need to set the valid bit. Also, a castout request from the current level of memory will need to clear the valid bit; or, a write from the next higher level cache will set the modify bit. Depending on the complexity of the control logic, in a complex design block 17 may also take the status bits from the entry.sub.-- slct as input in order to generate new values of the status bits.” (col. 5, line 50 – col. 6, line 14). New status generation would update status bit values from the entry which is input into fig. 1B].
12. The method of claim 2, further comprising: receiving a read command for the codeword; and communicating a portion of the codeword in response to the read command for the codeword, the portion of the codeword indicating the access information for the set of addresses [Cheong teaches “The director entry (Entry.sub.-- slct) read out from directory array 30 by a request and inputted into stage 32 is illustrated with n (=k +j) bits of information (a k bit tag and a j bit status) and m ECC check bits.” (col. 3, lines 1-4) ““The decoded request type is received by logic circuitry within block 15, which is utilized to select within multiplexer 14 between the tag inputted with the request and the tag received from directory array 30. The selected tag is then passed on and inserted into block 16 in order to generate the tag portion of the ECC with mkx ECC logic circuitry 16… In general, the decoded request type from the decode operation in stage 31 is acted on by block 15… From the response type from block 15 and the decode request types, block 17 decides which status bits need to be updated.” (col. 5, line 50-col. 6, line 14)].
21. An apparatus, comprising: a memory array; and one or more controllers coupled with the memory array, the one or more controllers configured to cause the apparatus to: decode, by a decoder, an address of the memory array; read a first set of bits that associated with the address, wherein each bit of the first set of bits indicates access information for one or more respective addresses; generate, by the decoder, a second set of bits that indicates updated information corresponding to whether the address has been accessed; combining the first set of bits with the second set of bits to update the first set of bits and to preserve the access information in one or more bits, of the first set of bits, not updated by the second set of bits; generate a codeword for the updated first set of bits; and store the codeword in the memory array [The rationale in the rejection of claim 2 is herein incorporated].
22. The method of claim 2, wherein combining the first set of bits with the second set of bits maintains error correction code (ECC) protection for the first set of bits based on avoiding overwriting the first set of bits [Cheong teaches combining of a first of bits and a second set of bits as “… In general, the decoded request type from the decode operation in stage 31 is acted on by block 15… From the response type from block 15 and the decode request types, block 17 decides which status bits need to be updated (thus, suggesting at least some bits may not be updated or overwritten). For example, a request that triggers a load of a new data entry from the next lower level of memory will need to set the valid bit. Also, a castout request from the current level of memory will need to clear the valid bit; or, a write from the next higher level cache will set the modify bit. Depending on the complexity of the control logic, in a complex design block 17 may also take the status bits from the entry.sub.-- slct as input in order to generate new values of the status bits.” (col. 5, line 50 – col. 6, line 14). “…the ECC generation for the status portion (block 18) takes a very small portion of the cycle time to complete. Therefore, block 18 can be moved into stage 33. The key is that the time to finish status bit generation (block 17), plus the time to finish ECC generation for the status bits (block 18), plus the time of ECC sum (block 19) do not exceed the cycle time, and that they can fit in one stage of the pipeline.” (col. 6, lines 15-29)]. Additionally, Loffer teaches [“ In case the entry in column V.sub.a is accessed, the new entry written to column V.sub.a is the entry that has been most recently used, because the latest access to the cache was directed towards column V.sub.a. Therefore, V.sub.a is more recently used than V.sub.b, V.sub.c, and V.sub.d, and therefore, the MRU/LRU status bits X1, X2, and X3 have to be changed accordingly. This implies that X1 has to be set to "EVEN" (800), X2 has to be set to "EVEN" (801), and X3 has to be set to "EVEN" (802) as well. The status bits X4, X5 and X6 do not relate to V.sub.a. Instead, they refer to the relative order of V.sub.b, V.sub.c, and V.sub.d, which is not changed by an access of column V.sub.a. Therefore, the status bits X4, X5 and X6 remain as they are (803, 804, 805), and no changes are made to these status bits.” (col. 10, lines 35-47). Thus, updating status bits based on avoiding overwriting some of the bits].
24. (New) The method of claim 2, wherein each bit, of the first set of bits, corresponds to a different column or different row of the memory array [Loffer teaches memory arrays rows (fig. 7 and related text). “The order of the four cache entries of one row is indicated by the MRU/LRU status bits X1, X2, . . . X6.” (col. 10, lines 11-12)].
25. (New) The method of claim 2, wherein a quantity of the first set of bits is the same as a quantity of the updated first set of bits [Cheong teaches “From the response type from block 15 and the decode request types, block 17 decides which status bits need to be updated (thus, suggesting at least one or more of the status bits may remain unchanged or preserved). For example, a request that triggers a load of a new data entry from the next lower level of memory will need to set the valid bit. Also, a castout request from the current level of memory will need to clear the valid bit; or, a write from the next higher level cache will set the modify bit. Depending on the complexity of the control logic, in a complex design block 17 may also take the status bits from the entry.sub.-- slct as input in order to generate new values of the status bits.” (col. 5, line 50 – col. 6, line 14). Note updating the values of status bits does not necessarily change the number of status bits. Loffer teaches [“ In case the entry in column V.sub.a is accessed, the new entry written to column V.sub.a is the entry that has been most recently used, because the latest access to the cache was directed towards column V.sub.a. Therefore, V.sub.a is more recently used than V.sub.b, V.sub.c, and V.sub.d, and therefore, the MRU/LRU status bits X1, X2, and X3 have to be changed accordingly. This implies that X1 has to be set to "EVEN" (800), X2 has to be set to "EVEN" (801), and X3 has to be set to "EVEN" (802) as well. The status bits X4, X5 and X6 do not relate to V.sub.a. Instead, they refer to the relative order of V.sub.b, V.sub.c, and V.sub.d, which is not changed by an access of column V.sub.a. Therefore, the status bits X4, X5 and X6 remain as they are (803, 804, 805), and no changes are made to these status bits.”].
26. (New) The method of claim 2, wherein combining the second set of bits and the first set of bits comprises using the second set of bits to modify the first set of bits Cheong teaches “From the response type from block 15 and the decode request types, block 17 decides which status bits need to be updated. For example, a request that triggers a load of a new data entry from the next lower level of memory will need to set the valid bit. Also, a castout request from the current level of memory will need to clear the valid bit; or, a write from the next higher level cache will set the modify bit. Depending on the complexity of the control logic, in a complex design block 17 may also take the status bits from the entry.sub.-- slct as input in order to generate new values of the status bits.” (col. 5, line 50 – col. 6, line 14). Thus, using the updated bits to generate new status bits].
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cheong et al. (US 5,533,189) in view of White et al. (US 5,696,937) and Loffer et al. (US 6,032,233) as applied in the rejection of claim 3 above, and further in view of Seshadri et al. (US 2012/0324314).
3. The combination of Cheong, White and Loffer teaches The method of claim 2, but does not expressly disclose further comprising: determining whether error correction code (ECC) decoding is enabled for tag bits at a memory device comprising the memory array in response to an activated operational mode of the memory device; however, regarding these limitations, Seshadri teaches [“[0041] According to embodiments of this invention, ECC encoder/decoder 44 is enabled upon entry into and exit from retention mode for a given retention domain 40q, to allow for the correction of data retention errors caused by power supply voltage V.sub.dda being applied by bias control circuit 42 being below the worst case DRV (i.e., the DRV for the poorest cells 22) for that retention domain 40q.” “[0044]… During process 50, retention control signals RET_CTRL applied to retention control logic 45 will indicate the normal operating mode for retention domain 40q; in response, retention control logic 45 will disable ECC encoder/decoder 44 for accesses to retention domain 40q, by way of enable signal ECC_EN. As such, read and write accesses from and to retention domain 40q during process 50 are performed without error correction decoding (on data read) or encoding (on data write). Maximum performance of RAM 18 for these accesses is therefore available”].
Cheong, White, Loffer and Sheshadri are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong, White and Loffer to include determining whether ECC decoding is enabled for tag bits at a memory device comprising the memory array based at least in part on an activated operational mode of the memory device as taught by Seshadri since doing so would provide the benefits of being able to enable/disable ECC; thus, achieving maximum performance for reads and writes (par. 0044).
Therefore, it would have been obvious to combine Cheong, White and Loffer with Seshardri for the benefit of creating a storage system/method to obtain the invention as specified in claim 3.
Claim 5 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Cheong et al. (US 5,533,189) in view of White et al. (US 5,696,937) and Loffer et al. (US 6,032,233) as applied in the rejection of claim 3 above, and further in view of Benisty et al. (US 2018/0069658).
5. The combination of Cheong, White and Loffer teaches The method of claim 2, wherein generating the codeword comprises: performing error correction code (ECC) encoding on the updated first set of bits, wherein the codeword comprises the updated first set of bits [Cheong teaches “ From block 17, the new status bits are inputted into block 18 so that an ECC is generated for the status portion with mxj ECC generation logic circuitry 18. Block 19, which performs an XOR, or sum operation, sums the ECC received from block 16 and the ECC received from block 18 to therefore output the new ECC for the directory entry.” (col. 6, lines 15-20). White teaches “The tag/status array-decoder block provides a number of functions which: (a) stores the tag address and stores the status and parity information for that address; (b) compares an incoming tag address with the stored address at that index to determine a "HIT"; (c) qualifies a "HIT" as valid by error checking and examining the status bits; (d) provides the bank address when there is a "HIT" and selects the bank for replacement when there is a "miss"; (e) provides new values for the valid bits and the status/tag parity for a status update; (f) generates an odd parity for the tag address and status bits which will be stored in the tag/status array.” (col. 8, lines 8-18)] but the combination does not expressly disclose the codeword comprises a set of parity bits that is for the updated first set of bits; however, regarding these limitations, Benitsy teaches [“the codeword may contain 192 (i.e., 3*64) information bits, 12 tag data bits, and 20 parity bits.” (par. 0082)].
Cheong, White, Loffer and Benitsty are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong, White and Loffer to have the codeword comprises a set of parity bits that is for the updated first set of bits as taught by Benisty since doing so would provide the benefits of facilitating verification of the integrity of the data stored in the memory (par. 0116).
Therefore, it would have been obvious to combine Cheong, White and Loffer with Benisty for the benefit of creating a storage system/method to obtain the invention as specified in claim 5.
9. The combination of Cheong, White and Loffer teaches The method of claim 2, further comprising: performing error correction code (ECC) decoding on the first set of bits…, wherein the codeword is generated after performing the ECC decoding [Cheong teaches “From block 17, the new status bits are inputted into block 18 so that an ECC is generated for the status portion with mxj ECC generation logic circuitry 18. Block 19, which performs an XOR, or sum operation, sums the ECC received from block 16 and the ECC received from block 18 to therefore output the new ECC for the directory entry.” (col. 6, lines 15-20). White teaches “The tag/status array-decoder block provides a number of functions which: (a) stores the tag address and stores the status and parity information for that address; (b) compares an incoming tag address with the stored address at that index to determine a "HIT"; (c) qualifies a "HIT" as valid by error checking and examining the status bits; (d) provides the bank address when there is a "HIT" and selects the bank for replacement when there is a "miss"; (e) provides new values for the valid bits and the status/tag parity for a status update; (f) generates an odd parity for the tag address and status bits which will be stored in the tag/status array.” (col. 8, lines 8-18) “ From block 17, the new status bits are inputted into block 18 so that an ECC is generated for the status portion with mxj ECC generation logic circuitry 18. Block 19, which performs an XOR, or sum operation, sums the ECC received from block 16 and the ECC received from block 18 to therefore output the new ECC for the directory entry.” (col. 6, lines 15-20) where the new ECC is stored in the directory (see col. 2, lines 38-67) (figs. 1-2 and related text), where Cheong further teaches “A request is received by stage 31, decoded and passed to stage 32a, which performs a checking of the ECC within ECC check logic 12 and a determination if there is a hit or a miss within hit/miss detect logic 13, which are both well-known circuits in the art.” (col. 5, lines 50-54); which would correspond to ECC decoding/checking the input to stage 32a, which includes the first set of tag bits corresponding to the tag bits and status bits input from 30 and 31 (fig. 1A), thus performing ECC checking/decoding before generating new ECC at 19 in fig. 1B, but Cheong does not expressly refer to this operation as ECC decoding such as generating the codeword after performing the ECC decoding. White teaches “The tag/status array-decoder block provides a number of functions which: (a) stores the tag address and stores the status and parity information for that address; (b) compares an incoming tag address with the stored address at that index to determine a "HIT"; (c) qualifies a "HIT" as valid by error checking and examining the status bits; (d) provides the bank address when there is a "HIT" and selects the bank for replacement when there is a "miss"; (e) provides new values for the valid bits and the status/tag parity for a status update; (f) generates an odd parity for the tag address and status bits which will be stored in the tag/status array.” (col. 8, lines 8-18)] but the combination of Cheong, White and Loffer does not expressly disclose and a set of parity bits for the first set of bits nor generating the codeword at 19 in fig. 1B after performing the ECC decoding since Cheong refers to the operation as ECC checking; however, regarding these limitations; Benisty teaches [“The ECC engine 166 may also be configured to receive data and to process the received data in accordance with one or more ECC decoding schemes. For example, the ECC engine 166 may include an ECC decoder, such as a Reed Solomon decoder, a BCH decoder, an LDPC decoder, a Turbo Code decoder, a decoder configured to decode received data in accordance with one or more other ECC encoding schemes, or any combination thereof. The ECC engine 166 may be configured to decode data read from the memory 104 to detect and correct, up to an error correction capability of the ECC scheme, any bit errors that may be present in the data. In some implementations, the ECC engine 166 may be configured to perform single error correct, multiple error detect decoding based on a cyclic code, such as a BCH code. For example, the ECC engine 166 may be configured to detect up to ten errors and to correct up to one error based on the cyclic code, as further described herein. “ (par. 0048) “the method 1000 includes concurrently encoding a first portion of an error correction code (ECC) codeword and tag parity data (e.g., residual parity data) that corresponds to a second portion of the ECC codeword, combining the encoded first portion of the ECC codeword and the encoded first portion of tag parity data to generate an encoded ECC codeword, and decoding a received codeword based on the encoded ECC codeword. For example, the first portion of the ECC codeword may be encoded by the main encoder 504 of FIG. 5, and the tag parity data may be generated and encoded by the residual parity generator 506 of FIG. 5.” (par. 0115), thus, also performing ECC decoding/checking on bits to be processed before generated an encoded ECC codeword].
Cheong, White, Loffer and Benitsty are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong, White and Loffer to have the accessing the bits as decoding and include a set of parity bits for the first set of bits as well as generating of the codeword after performing ECC decoding as taught by Benisty since doing so would provide the benefits of facilitating verification of the integrity of the data stored in the memory (par. 0116).
Therefore, it would have been obvious to combine Cheong, White and Loffer with Benisty for the benefit of creating a storage system/method to obtain the invention as specified in claim 9.
10. The combination of Cheong, White and Loffer teaches The method of claim 2, wherein the first set of bits … are read from a set of memory cells, and wherein storing the codeword comprises: writing the codeword to the set of memory cells [Cheong teaches “a directory of cache or memory (a memory directory is used in the shared global memory in multiprocessor systems) contains an array of entries that correspond one-to-one to data entries in the cache or the memory data array.” (col. 1, lines 12-17) “The directory entry (Entry.sub.-- slct) read out from directory array 30 by a request and inputted into stage 32 is illustrated with n (=k +j) bits of information (a k bit tag and a j bit status) and m ECC check bits. “ (col. 3, lines 1-4) “From block 17, the new status bits are inputted into block 18 so that an ECC is generated for the status portion with mxj ECC generation logic circuitry 18. Block 19, which performs an XOR, or sum operation, sums the ECC received from block 16 and the ECC received from block 18 to therefore output the new ECC for the directory entry.” (col. 6, lines 15-20) where the new ECC is stored in the directory (see col. 2, lines 38-67) (figs. 1-2 and related text)] but the combination does not expressly disclose and parity bits for the first set of bits; however, regarding these limitations, Benitsty teaches [“the codeword may contain 192 (i.e., 3*64) information bits, 12 tag data bits, and 20 parity bits.” (par. 0082) “the method 1000 includes concurrently encoding a first portion of an error correction code (ECC) codeword and tag parity data (e.g., residual parity data) that corresponds to a second portion of the ECC codeword, combining the encoded first portion of the ECC codeword and the encoded first portion of tag parity data to generate an encoded ECC codeword, and decoding a received codeword based on the encoded ECC codeword. For example, the first portion of the ECC codeword may be encoded by the main encoder 504 of FIG. 5, and the tag parity data may be generated and encoded by the residual parity generator 506 of FIG. 5.” (par. 0115)].
Cheong, White, Loffer and Benitsty are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong, White and Loffer to have the accessing of the bits as decoding and include a set of parity bits for the first set of bits as taught by Benisty since doing so would provide the benefits of facilitating verification of the integrity of the data stored in the memory (par. 0116).
Therefore, it would have been obvious to combine Cheong, White and Loffer with Benisty for the benefit of creating a storage system/method to obtain the invention as specified in claim 10.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Cheong et al. (US 5,533,189) in view of White et al. (US 5,696,937) and Loffer et al. (US 6,032,233) and Kajigaya (US 2015/0074493).
7. The combination of Cheong, White and Loffer teaches The method of claim 2, but does not expressly disclose further comprising: receiving a pre-charge command after receiving a command that includes the address, wherein the codeword is stored in the memory array in response to receiving the pre-charge command; however, regarding these limitations, Kajigaya teaches [“ When a precharge command is received to activate a write pulse signal /WP, a write operation is performed to memory cells corresponding to information of the register circuits RDGi and RDCj as necessary, and the page is closed (S24). In this S24, when an error correction by the ECC control block 15 has been performed on a data bit (an inverted control signal INVi is generated), the data bit is written to a memory cell corresponding to the register circuit RGDi for which an error correction has been performed. Rewriting of check bits is also performed.” (par. 0087)].
Cheong, White, Loffer and Kajigaya are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong, White and Loffer to include receiving a pre-charge command after the command, wherein the codeword is stored in the memory array in response to receiving the pre-charge command as taught by Kajigaya since doing so would provide the benefits of [facilitating the performance of the write operation by the precharge signal activating the write pulse signal (par. 0084)].
Therefore, it would have been obvious to combine Cheong, White and Loffer with Kayigaya for the benefit of creating a storage system/method to obtain the invention as specified in claim 7.
8. The combination of Cheong, White and Loffer teaches The method of claim 2, but does not expressly disclose further comprising: latching the codeword in a set of latching components before storing the codeword in the memory array; however, regarding these limitations [Kayigaya teaches “The read write units (for data bits) 31 includes a sense amplifier SADi, a register circuit RGDi, and a write driver WD. The read write units (for check bits) 32 includes a sense amplifier SACj, a register circuit RGCj, and a write driver WDC.” (par. 0036; fig. 2 and related text) “In FIG. 5, the write driver WD includes a write control circuit 85 and a GBL driver 82 in detail, and details of the respective circuits are shown. In FIG. 5, sense latch circuit 84 has a portion including the sense amplifier SADi and the data register circuit RGDi.” (par. 0061; fig. 5 and related text)].
Cheong, White, Loffer and Kajigaya are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong, White and Loffer to include a structure latching as taught by Kajigaya since doing so would provide the benefits of [facilitating error correction in a semiconductor memory (par. 0023)].
Therefore, it would have been obvious to combine Cheong, White and Loffer with Kayigaya for the benefit of creating a storage system/method to obtain the invention as specified in claim 8.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
Ruby (US 5,471,605) teaches “Typically, LRU status bits in the LRU array are updated during both cache read and write cycles. In a multi-way set associative cache memory, updating the LRU status bits during a read cycle is timing-critical since the new LRU status bit values depend on the MATCH signals originated in each way of the cache. On a read miss cycle, the old LRU status bit value in the array is preserved. Two ways to preserve the old LRU status bit are disabling any write to the data or reading the data and subsequently writing the same data back into the array. On a read hit cycle, the LRU status bit value is read, updated according to the values of the MATCH signals for each way, and then written into the LRU status bit array. The LRU array status bits are typically updated using combinational logic to directly implement the logic equations that define the updated LRU array status bits.” (col. 1, lines 45-60).
ACKNOWLEDGEMENT OF ISSUES RAISED BY APPLICANT
Response to Amendment
Applicant's arguments filed on 5/4/2026 have been fully considered but they are moot in view of new grounds of rejection.
CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 2-3, 5-10, 12, 21-22 and 24-26 have received an action on the merits and are subject to a final rejection.
a(2) CLAIMS NO LONGER UNDER CONSIDERATION
Claims 1, 4, 13-16, 18 and 23 have been canceled.
a(3) ALLOWABLE SUBJECT MATTER
Per the instant office action, claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In particular, while Cheong teaches ECC generation of new status bits, neither Cheong by itself or in combination with the prior art of record, teaches or renders obvious the recited combination as set forth in claim 11, including “communicating the first set of tag bits and the second set of bits to a first error correction code (ECC) engine, wherein the first set of bits and second set of bits are combined after the communicating.” Since in Cheong, the new status bits are generated and then they are communicated to the ECC generation.
Claims 17 and 19-20 are allowed.
The reasons for allowance of claim 17 are the following: In interpreting the pending claim(s), in light of the Specification, the Examiner finds the claimed invention to be patentably distinct from the prior art of record. The prior art of record, including the references noted above; neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “amplifier components configured to sense a first set of bits associated with the address, wherein each bit of the first set of bits indicates access information for one or more respective addresses; a decoder configured to decode the address and configured to generate a second set of bits that indicates updated information corresponding to whether the address has been accessed; a first error correction code (ECC) engine configured to combine the first set of bits and the second set of bits to update the first set of bits and to preserve the access information in one or more bits, of the first set of bits, not updated by the second set of bits, wherein the first ECC engine is further configured to generate a codeword for the updated first set of bits; and latching components configured to latch the codeword for storage at the memory array.”
More specifically, while Cheong teaches ECC generation of new status bits, neither Cheong by itself or in combination with the prior art of record, teaches or renders obvious the recited combination as set forth in claim 17, including “a first error correction code (ECC) engine configured to combine the first set of bits and the second set of bits to update the first set of bits and to preserve the access information in one or more bits, of the first set of bits, not updated by the second set of bits, wherein the first ECC engine is further configured to generate a codeword for the updated first set of bits” since in Cheong, the new status bits are generated and then sent to the ECC engine.
Dependent claims 19-20 are allowed for the reasons indicated with respect to claim 17.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIMA RIGOL whose telephone number is (571)272-1232. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached on (571) 272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
May 14, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135
Prosecution Insights