Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/18/2025 has been entered.
As per the instant application having Application No. 18/608,591, the amendment filed on 12/1/2025 with request for continued examination (RCE) filed on 12/18/2025 is herein acknowledged. Claims 2, 5-6, 9, 11, 17 and19-21 have been amended and claims 22-23 have been added. Claims 1, 4, 15-16 and 18 have been canceled. Claims 2-3, 5-14, 17 and 19-23 are pending.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
TERMINAL DISCLAIMER
The terminal disclaimer filed on 9/12/2025 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US 11,947,841 has been reviewed and is accepted. The terminal disclaimer has been recorded.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 6, 11-12 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Cheong et al. (US 5,533,189) in view of White et al. (US 5,696,937).
2. (New) A method, comprising: decoding, by a decoder, an address of a memory array; [Cheong teaches “a directory of cache or memory (a memory directory is used in the shared global memory in multiprocessor systems) contains an array of entries that correspond one-to-one to data entries in the cache or the memory data array. “ (col. 1, lines 12-17) “A request is first decoded in the first stage while the directory is looked up by the index portion of the address. This is the directory access/request decode stage 31.” (col. 2, lines 38-42) “the address tag is in the input tag, and is available in stage 31” (Col. 5, lines 33-35) “A request is received by stage 31, decoded and passed to stage 32a” (col. 5, lines 50-51)]
reading a first set of bits that indicates whether the decoded address has been accessed; [Cheong teaches “the address tag is in the input tag, and is available in stage 31” (Col. 5, lines 33-35) “An updated directory entry requiring a new ECC most often only requires a portion of the entry updated. When an existing directory entry is modified, only the status bits are changed and the address tag read from directory 30 stay unchanged” (col. 5, lines 24-29), where the first set of bits thus corresponds to the combination of address tag and status bits read from directory array 30 in fig. 1A before any modifications are made (see figs. 1A and 1B and related text). Note that since the claim requires the first set of bits indicate whether the address has been accessed, the combination of address tag and status bits in Cheong corresponds to these bits since it includes status bits which include access information]
generating, by the decoder, a second set of bits that indicates updated information corresponding to whether the decoded address has been accessed; [Cheong teaches “Tag will be 37 bits. Compared to normally 5 status bits (1 valid, 4 MESI) bits used in a typical multiprocessor coherence protocol), the number of address tag bits is much larger than the number of status bits. Thus, ECC generation can be distributed among the tag portion and the status portion of the directory entry” (col. 5, lines 36-49) “The decoded request type is received by logic circuitry within block 15, which is utilized to select within multiplexer 14 between the tag inputted with the request and the tag received from directory array 30. The selected tag is then passed on and inserted into block 16 in order to generate the tag portion of the ECC with mkx ECC logic circuitry 16… In general, the decoded request type from the decode operation in stage 31 is acted on by block 15… From the response type from block 15 and the decode request types, block 17 decides which status bits need to be updated. For example, a request that triggers a load of a new data entry from the next lower level of memory will need to set the valid bit. Also, a castout request from the current level of memory will need to clear the valid bit; or, a write from the next higher level cache will set the modify bit. Depending on the complexity of the control logic, in a complex design block 17 may also take the status bits from the entry.sub.-- slct as input in order to generate new values of the status bits.” (col. 5, line 50 – col. 6, line 14) where the updated set of status bits from box 17 in fig. 1B correspond to the claimed second set of bits] but Cheong does not expressly disclose the generating by the decoder
combining the first set of bits with the generated second set of bits to update the first set of bits; [Cheong teaches “The decoded request type is received by logic circuitry within block 15, which is utilized to select within multiplexer 14 between the tag inputted with the request and the tag received from directory array 30. The selected tag is then passed on and inserted into block 16 in order to generate the tag portion of the ECC with mkx ECC logic circuitry 16… In general, the decoded request type from the decode operation in stage 31 is acted on by block 15… From the response type from block 15 and the decode request types, block 17 decides which status bits need to be updated. For example, a request that triggers a load of a new data entry from the next lower level of memory will need to set the valid bit. Also, a castout request from the current level of memory will need to clear the valid bit; or, a write from the next higher level cache will set the modify bit. Depending on the complexity of the control logic, in a complex design block 17 may also take the status bits from the entry.sub.-- slct as input in order to generate new values of the status bits.” (col. 5, line 50 – col. 6, line 14). Thus, the directory entry comprising address tag and status bits from box 30 in fig. 1A is combined with new status bits generated in box 17 in fig. 1B by taking address tag portion from the entry in 30 and combining it with New status bits generated in box 17; thus combining a first set of bits including address bits and status bits from 32A into updated entry at 33A which includes address tag TAG(0:k-1) and New status (0:j-1). See figs. 1A and 1B and related text. Note that the combination of TAG(0:k-1) and status bits New status (0:j-1) in FIG. 1B corresponds to an updated first set of tag bits as it has updated the status bit portion of the from box 30]
generating a codeword for the updated first set of bits; and storing the codeword in the memory array [Cheong teaches “ From block 17, the new status bits are inputted into block 18 so that an ECC is generated for the status portion with mxj ECC generation logic circuitry 18. Block 19, which performs an XOR, or sum operation, sums the ECC received from block 16 and the ECC received from block 18 to therefore output the new ECC for the directory entry.” (col. 6, lines 15-20) where the new ECC is stored in the directory (see col. 2, lines 38-67) (figs. 1-2 and related text) where “a directory of cache or memory (a memory directory is used in the shared global memory in multiprocessor systems) contains an array of entries that correspond one-to-one to data entries in the cache or the memory data array.” (col. 1, lines 12-17)]. Thus, a codeword is generated for the updated set of tag TAG(0:k-1) and status bits New status (0:j-1) which corresponds to an updated first set of bits as it has updated the directory array entry from box 30 into an entry having TAG(0:k-1) and status bits New status (0:j-1). The codeword includes ECC for address tag portion from 16 and ECC from updated status bit portion from 18, which are used in 19 to generate NEW ECC [See figs. 1A and 1B and related text].
Regarding the generating by the decoder, White teaches [“The tag/status array-decoder block provides a number of functions which: (a) stores the tag address and stores the status and parity information for that address; (b) compares an incoming tag address with the stored address at that index to determine a "HIT"; (c) qualifies a "HIT" as valid by error checking and examining the status bits; (d) provides the bank address when there is a "HIT" and selects the bank for replacement when there is a "miss"; (e) provides new values for the valid bits and the status/tag parity for a status update; (which corresponds to the generating) (f) generates an odd parity for the tag address and status bits which will be stored in the tag/status array.” (col. 8, lines 8-18)].
Cheong and White are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Cheong to have the generating by the decoder as taught by White since doing so would at least provide the benefits of flexibility of design and “in order to provide a rapid invalidation of addresses in a tag/status array-decoder unit” (col. 3, lines 24-40).
Therefore, it would have been obvious to combine Cheong and White for the benefit of creating a storage system/method to obtain the invention as specified in claim 2.
6. The method of claim 2, wherein generating the second set of bits comprises: selecting a value for a bit corresponding to the decoded address, wherein the generated second set of bits includes the bit [Cheong teaches “The decoded request type is received by logic circuitry within block 15, which is utilized to select within multiplexer 14 between the tag inputted with the request and the tag received from directory array 30. The selected tag is then passed on and inserted into block 16 in order to generate the tag portion of the ECC with mkx ECC logic circuitry 16… In general, the decoded request type from the decode operation in stage 31 is acted on by block 15… From the response type from block 15 and the decode request types, block 17 decides which status bits need to be updated. For example, a request that triggers a load of a new data entry from the next lower level of memory will need to set the valid bit. Also, a castout request from the current level of memory will need to clear the valid bit; or, a write from the next higher level cache will set the modify bit. Depending on the complexity of the control logic, in a complex design block 17 may also take the status bits from the entry.sub.-- slct as input in order to generate new values of the status bits.” (col. 5, line 50 – col. 6, line 14). New status generation would update status bit values from the entry which is input into fig. 1B].
11. The method of claim 2, further comprising: communicating the first set of tag bits and the generated second set of bits to a first error correction code (ECC) engine, wherein the first set of bits and generated second set of bits are combined after the communicating [Cheong teaches “ Thus, it is an objective of the present invention to generate an ECC for each request received within a memory device controller in a manner that does not require an extra cycle in order to generate the ECC.” (col. 3, lines 45-48) where “The ECC generation logic 20 operates on the n information bit of the entry to generate a new m-bit ECC.” (col. 3, lies 23-25) see ECC generation logic in (figs. 1 and 1B and related text) “ From block 17, the new status bits are inputted into block 18 so that an ECC is generated for the status portion with mxj ECC generation logic circuitry 18. Block 19, which performs an XOR, or sum operation, sums the ECC received from block 16 and the ECC received from block 18 to therefore output the new ECC for the directory entry.” (col. 6, lines 15-20) where the new ECC is stored in the directory (see col. 2, lines 38-67) (figs. 1, 1b, 2 and related text). Thus, the directory entry comprising address tag and status bits from box 30 in fig. 1A is combined with new status bits generated in box 17 in fig. 1B by taking address tag portion from the entry in 30 and combining it with New status bits generated in box 17; thus combining a first set of tag bits including address bits and status bits from 32A into updated entry at 33A which includes address tag TAG(0:k-1) and New status (0:j-1). See figs. 1A and 1B and related text. Note that the combination of TAG(0:k-1) and status bits New status (0:j-1) in FIG. 1B corresponds to an updated first set of tag bits as it has updated the status bit portion of the from box 30. The entry before modification shown in box 30 of fig. 1A is input into ECC engine including ECC tag 16, ECC status 18 and box 19. The first set of tag bits including tag bits and status bits from 30, 31 in fig. 1A are communicated to ECCs in 32a, 33a in fig. 1B and after this communicating, the bits in 30, 31 are combined to replace status bits by updated status bits and generate new entry including new status and tag which are further combined in 19 to generate NEW ECC (0:m-1) in fig. 1B].
12. The method of claim 2, further comprising: receiving a read command for the codeword; and communicating a portion of the codeword in response to the read command for the codeword, the portion of the codeword indicating the access information for the set of addresses [Cheong teaches “The director entry (Entry.sub.-- slct) read out from directory array 30 by a request and inputted into stage 32 is illustrated with n (=k +j) bits of information (a k bit tag and a j bit status) and m ECC check bits.” (col. 3, lines 1-4) ““The decoded request type is received by logic circuitry within block 15, which is utilized to select within multiplexer 14 between the tag inputted with the request and the tag received from directory array 30. The selected tag is then passed on and inserted into block 16 in order to generate the tag portion of the ECC with mkx ECC logic circuitry 16… In general, the decoded request type from the decode operation in stage 31 is acted on by block 15… From the response type from block 15 and the decode request types, block 17 decides which status bits need to be updated.” (col. 5, line 50-col. 6, line 14)].
21. An apparatus, comprising: a memory array; and one or more controllers coupled with the memory array, the one or more controllers configured to cause the apparatus to: decode, by a decoder, an address of the memory array; read a first set of bits that indicates whether the decoded address has been accessed; generate, by the decoder, a second set of bits that indicates updated information corresponding to whether the decoded address has been accessed; combining the first set of bits with the generated second set of bits to update the first set of bits; generate a codeword for the updated first set of bits; and store the codeword in the memory array [The rationale in the rejection of claim 2 is herein incorporated].
22. (New) The method of claim 2, wherein combining the first set of bits with the generated second set of bits to update the first set of bits maintains error correction code (ECC) protection for the first set of bits based on avoiding overwriting the first set of bits [Cheong teaches combining of a first of bits and a second set of bits as “The decoded request type is received by logic circuitry within block 15, which is utilized to select within multiplexer 14 between the tag inputted with the request and the tag received from directory array 30. The selected tag is then passed on and inserted into block 16 in order to generate the tag portion of the ECC with mkx ECC logic circuitry 16… In general, the decoded request type from the decode operation in stage 31 is acted on by block 15… From the response type from block 15 and the decode request types, block 17 decides which status bits need to be updated. For example, a request that triggers a load of a new data entry from the next lower level of memory will need to set the valid bit. Also, a castout request from the current level of memory will need to clear the valid bit; or, a write from the next higher level cache will set the modify bit. Depending on the complexity of the control logic, in a complex design block 17 may also take the status bits from the entry.sub.-- slct as input in order to generate new values of the status bits.” (col. 5, line 50 – col. 6, line 14). Thus, the directory entry comprising address tag and status bits from box 30 in fig. 1A is combined with new status bits generated in box 17 in fig. 1B by taking address tag portion from the entry in 30 and combining it with New status bits generated in box 17; thus combining a first set of bits including address bits and status bits from 32A into updated entry at 33A which includes address tag TAG(0:k-1) and New status (0:j-1). See figs. 1A and 1B and related text. Note that the combination of TAG(0:k-1) and status bits New status (0:j-1) in FIG. 1B corresponds to an updated first set of tag bits as it has updated the status bit portion of the from box 30.
And explains “From block 17, the new status bits are inputted into block 18 so that an ECC is generated for the status portion with mxj ECC generation logic circuitry 18. Block 19, which performs an XOR, or sum operation, sums the ECC received from block 16 and the ECC received from block 18 to therefore output the new ECC for the directory entry… Because the tag in the update entry has many more bits than the status bit portion (37 bits versus 5 bits in the above description), the ECC generation for the status portion (block 18) takes a very small portion of the cycle time to complete. Therefore, block 18 can be moved into stage 33. The key is that the time to finish status bit generation (block 17), plus the time to finish ECC generation for the status bits (block 18), plus the time of ECC sum (block 19) do not exceed the cycle time, and that they can fit in one stage of the pipeline.” (col. 6, lines 15-29)]. Thus, according to Cheong ECC for the first set of bits (including address portion and status bits) is maintained by taking ECC from box 16 which includes the unchanged portion of the first set of bits and combining it with ECC from box 18 which includes the updated portion from box 17 or second set of bits to generate an updated version the first set of bits rather than overwriting the first set of bits with the second set of bits and taking ECC of just the second set of bits. Thus, avoiding overwriting of the first set of bits with the updated or generated bits from box 17, since the unchanged portion of the first set of bits is maintained as well as ECC for the first set of bits (before updating and after updating). Note the Specification also explains “Combining the stored tag bits and the generated tag bits (rather than generating a new codeword based solely on the generated tag bits) may allow the device to preserve the stored tag bits that are not updated by the generated tag bits.” (par. 0066 of US 2024/0302998, corresponding to the Instant Application), which is equivalent to the updating taught by Cheong since Cheong does not completely replace the first set of bits by the second set of bits but rather combines the first set of bits (including a portion that changes and one that does not) with the second set of bits (updated bits).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cheong et al. (US 5,533,189) in view of White et al. (US 5,696,937) as applied in the rejection of claim 3 above, and further in view of Seshadri et al. (US 2012/0324314).
3. The combination of Cheong and White teaches The method of claim 2, but does not expressly disclose further comprising: determining whether error correction code (ECC) decoding is enabled for tag bits at a memory device comprising the memory array in response to an activated operational mode of the memory device; however, regarding these limitations, Seshadri teaches [“[0041] According to embodiments of this invention, ECC encoder/decoder 44 is enabled upon entry into and exit from retention mode for a given retention domain 40q, to allow for the correction of data retention errors caused by power supply voltage V.sub.dda being applied by bias control circuit 42 being below the worst case DRV (i.e., the DRV for the poorest cells 22) for that retention domain 40q.” “[0044]… During process 50, retention control signals RET_CTRL applied to retention control logic 45 will indicate the normal operating mode for retention domain 40q; in response, retention control logic 45 will disable ECC encoder/decoder 44 for accesses to retention domain 40q, by way of enable signal ECC_EN. As such, read and write accesses from and to retention domain 40q during process 50 are performed without error correction decoding (on data read) or encoding (on data write). Maximum performance of RAM 18 for these accesses is therefore available”].
Cheong, White and Sheshadri are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong and White to include determining whether ECC decoding is enabled for tag bits at a memory device comprising the memory array based at least in part on an activated operational mode of the memory device as taught by Seshadri since doing so would provide the benefits of being able to enable/disable ECC; thus, achieving maximum performance for reads and writes (par. 0044).
Therefore, it would have been obvious to combine Cheong and White with Seshardri for the benefit of creating a storage system/method to obtain the invention as specified in claim 3.
Claim 5 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Cheong et al. (US 5,533,189) in view of White et al. (US 5,696,937) as applied in the rejection of claim 3 above, and further in view of Benisty et al. (US 2018/0069658).
5. The method of claim 2, wherein generating the codeword comprises: performing error correction code (ECC) encoding on the updated first set of bits, wherein the codeword comprises the updated first set of bits [Cheong teaches “ From block 17, the new status bits are inputted into block 18 so that an ECC is generated for the status portion with mxj ECC generation logic circuitry 18. Block 19, which performs an XOR, or sum operation, sums the ECC received from block 16 and the ECC received from block 18 to therefore output the new ECC for the directory entry.” (col. 6, lines 15-20). White teaches “The tag/status array-decoder block provides a number of functions which: (a) stores the tag address and stores the status and parity information for that address; (b) compares an incoming tag address with the stored address at that index to determine a "HIT"; (c) qualifies a "HIT" as valid by error checking and examining the status bits; (d) provides the bank address when there is a "HIT" and selects the bank for replacement when there is a "miss"; (e) provides new values for the valid bits and the status/tag parity for a status update; (f) generates an odd parity for the tag address and status bits which will be stored in the tag/status array.” (col. 8, lines 8-18)] but the combination does not expressly disclose the codeword comprises a set of parity bits that is for the updated first set of bits; however, regarding these limitations, Benitsy teaches [“the codeword may contain 192 (i.e., 3*64) information bits, 12 tag data bits, and 20 parity bits.” (par. 0082)].
Cheong, White and Benitsty are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong and White to have the codeword comprises a set of parity bits that is for the updated first set of bits as taught by Benisty since doing so would provide the benefits of facilitating verification of the integrity of the data stored in the memory (par. 0116).
Therefore, it would have been obvious to combine Cheong and White with Benisty for the benefit of creating a storage system/method to obtain the invention as specified in claim 5.
9. The method of claim 2, further comprising: performing error correction code (ECC) decoding on the first set of bits…, wherein the codeword is generated after performing the ECC decoding [Cheong teaches “From block 17, the new status bits are inputted into block 18 so that an ECC is generated for the status portion with mxj ECC generation logic circuitry 18. Block 19, which performs an XOR, or sum operation, sums the ECC received from block 16 and the ECC received from block 18 to therefore output the new ECC for the directory entry.” (col. 6, lines 15-20). White teaches “The tag/status array-decoder block provides a number of functions which: (a) stores the tag address and stores the status and parity information for that address; (b) compares an incoming tag address with the stored address at that index to determine a "HIT"; (c) qualifies a "HIT" as valid by error checking and examining the status bits; (d) provides the bank address when there is a "HIT" and selects the bank for replacement when there is a "miss"; (e) provides new values for the valid bits and the status/tag parity for a status update; (f) generates an odd parity for the tag address and status bits which will be stored in the tag/status array.” (col. 8, lines 8-18) “ From block 17, the new status bits are inputted into block 18 so that an ECC is generated for the status portion with mxj ECC generation logic circuitry 18. Block 19, which performs an XOR, or sum operation, sums the ECC received from block 16 and the ECC received from block 18 to therefore output the new ECC for the directory entry.” (col. 6, lines 15-20) where the new ECC is stored in the directory (see col. 2, lines 38-67) (figs. 1-2 and related text), where Cheong further teaches “A request is received by stage 31, decoded and passed to stage 32a, which performs a checking of the ECC within ECC check logic 12 and a determination if there is a hit or a miss within hit/miss detect logic 13, which are both well-known circuits in the art.” (col. 5, lines 50-54); which would correspond to ECC decoding/checking the input to stage 32a, which includes the first set of tag bits corresponding to the tag bits and status bits input from 30 and 31 (fig. 1A), thus performing ECC checking/decoding before generating new ECC at 19 in fig. 1B, but Cheong does not expressly refer to this operation as ECC decoding such as generating the codeword after performing the ECC decoding. White teaches “The tag/status array-decoder block provides a number of functions which: (a) stores the tag address and stores the status and parity information for that address; (b) compares an incoming tag address with the stored address at that index to determine a "HIT"; (c) qualifies a "HIT" as valid by error checking and examining the status bits; (d) provides the bank address when there is a "HIT" and selects the bank for replacement when there is a "miss"; (e) provides new values for the valid bits and the status/tag parity for a status update; (f) generates an odd parity for the tag address and status bits which will be stored in the tag/status array.” (col. 8, lines 8-18)] but the combination of Cheong and White does not expressly disclose and a set of parity bits for the first set of bits nor generating the codeword at 19 in fig. 1B after performing the ECC decoding since Cheong refers to the operation as ECC cheking; however, regarding these limitations; however, regarding these limitations, Benisty teaches [“The ECC engine 166 may also be configured to receive data and to process the received data in accordance with one or more ECC decoding schemes. For example, the ECC engine 166 may include an ECC decoder, such as a Reed Solomon decoder, a BCH decoder, an LDPC decoder, a Turbo Code decoder, a decoder configured to decode received data in accordance with one or more other ECC encoding schemes, or any combination thereof. The ECC engine 166 may be configured to decode data read from the memory 104 to detect and correct, up to an error correction capability of the ECC scheme, any bit errors that may be present in the data. In some implementations, the ECC engine 166 may be configured to perform single error correct, multiple error detect decoding based on a cyclic code, such as a BCH code. For example, the ECC engine 166 may be configured to detect up to ten errors and to correct up to one error based on the cyclic code, as further described herein. “ (par. 0048) “the method 1000 includes concurrently encoding a first portion of an error correction code (ECC) codeword and tag parity data (e.g., residual parity data) that corresponds to a second portion of the ECC codeword, combining the encoded first portion of the ECC codeword and the encoded first portion of tag parity data to generate an encoded ECC codeword, and decoding a received codeword based on the encoded ECC codeword. For example, the first portion of the ECC codeword may be encoded by the main encoder 504 of FIG. 5, and the tag parity data may be generated and encoded by the residual parity generator 506 of FIG. 5.” (par. 0115), thus, also performing ECC decoding/checking on bits to be processed before generated an encoded ECC codeword].
Cheong, White and Benitsty are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong and White to have the accessing the bits as decoding and include a set of parity bits for the first set of bits as well as generating of the codeword after performing ECC decoding as taught by Benisty since doing so would provide the benefits of facilitating verification of the integrity of the data stored in the memory (par. 0116).
Therefore, it would have been obvious to combine Cheong and White with Benisty for the benefit of creating a storage system/method to obtain the invention as specified in claim 9.
10. The method of claim 2, wherein the first set of bits … are read from a set of memory cells, and wherein storing the codeword comprises: writing the codeword to the set of memory cells [Cheong teaches “a directory of cache or memory (a memory directory is used in the shared global memory in multiprocessor systems) contains an array of entries that correspond one-to-one to data entries in the cache or the memory data array.” (col. 1, lines 12-17) “The directory entry (Entry.sub.-- slct) read out from directory array 30 by a request and inputted into stage 32 is illustrated with n (=k +j) bits of information (a k bit tag and a j bit status) and m ECC check bits. “ (col. 3, lines 1-4) “From block 17, the new status bits are inputted into block 18 so that an ECC is generated for the status portion with mxj ECC generation logic circuitry 18. Block 19, which performs an XOR, or sum operation, sums the ECC received from block 16 and the ECC received from block 18 to therefore output the new ECC for the directory entry.” (col. 6, lines 15-20) where the new ECC is stored in the directory (see col. 2, lines 38-67) (figs. 1-2 and related text)] but the combination of Cheong and White does not expressly disclose and parity bits for the first set of bits; however, regarding these limitations, Benitsty teaches [“the codeword may contain 192 (i.e., 3*64) information bits, 12 tag data bits, and 20 parity bits.” (par. 0082) “the method 1000 includes concurrently encoding a first portion of an error correction code (ECC) codeword and tag parity data (e.g., residual parity data) that corresponds to a second portion of the ECC codeword, combining the encoded first portion of the ECC codeword and the encoded first portion of tag parity data to generate an encoded ECC codeword, and decoding a received codeword based on the encoded ECC codeword. For example, the first portion of the ECC codeword may be encoded by the main encoder 504 of FIG. 5, and the tag parity data may be generated and encoded by the residual parity generator 506 of FIG. 5.” (par. 0115)].
Cheong, White and Benitsty are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong and White to have the accessing f the bits as decoding and include a set of parity bits for the first set of bits as taught by Benisty since doing so would provide the benefits of facilitating verification of the integrity of the data stored in the memory (par. 0116).
Therefore, it would have been obvious to combine Cheong and White with Benisty for the benefit of creating a storage system/method to obtain the invention as specified in claim 10.
Claims 7-8, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheong et al. (US 5,533,189) in view of White et al. (US 5,696,937) and Kajigaya (US 2015/0074493).
7. The combination of Cheong and White teaches The method of claim 2, but does not expressly disclose further comprising: receiving a pre-charge command after receiving a command that includes the address, wherein the codeword is stored in the memory array in response to receiving the pre-charge command; however, regarding these limitations, Kajigaya teaches [“ When a precharge command is received to activate a write pulse signal /WP, a write operation is performed to memory cells corresponding to information of the register circuits RDGi and RDCj as necessary, and the page is closed (S24). In this S24, when an error correction by the ECC control block 15 has been performed on a data bit (an inverted control signal INVi is generated), the data bit is written to a memory cell corresponding to the register circuit RGDi for which an error correction has been performed. Rewriting of check bits is also performed.” (par. 0087)].
Cheong, White and Kajigaya are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong and White to include receiving a pre-charge command after the command, wherein the codeword is stored in the memory array in response to receiving the pre-charge command as taught by Kajigaya since doing so would provide the benefits of [facilitating the performance of the write operation by the precharge signal activating the write pulse signal (par. 0084)].
Therefore, it would have been obvious to combine Cheong and White with Kayigaya for the benefit of creating a storage system/method to obtain the invention as specified in claim 7.
8. The combination of Cheong and White teaches The method of claim 2, but does not expressly disclose further comprising: latching the codeword in a set of latching components before storing the codeword in the memory array; however, regarding these limitations [Kayigaya teaches “The read write units (for data bits) 31 includes a sense amplifier SADi, a register circuit RGDi, and a write driver WD. The read write units (for check bits) 32 includes a sense amplifier SACj, a register circuit RGCj, and a write driver WDC.” (par. 0036; fig. 2 and related text) “In FIG. 5, the write driver WD includes a write control circuit 85 and a GBL driver 82 in detail, and details of the respective circuits are shown. In FIG. 5, sense latch circuit 84 has a portion including the sense amplifier SADi and the data register circuit RGDi.” (par. 0061; fig. 5 and related text)].
Cheong, White and Kajigaya are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong and White to include a structure latching as taught by Kajigaya since doing so would provide the benefits of [facilitating error correction in a semiconductor memory (par. 0023)].
Therefore, it would have been obvious to combine Cheong and White with Kayigaya for the benefit of creating a storage system/method to obtain the invention as specified in claim 8.
17. An apparatus, comprising: …a first set of bits that indicates whether an address of the memory array has been accessed … a decoder configured to decode the address and configured to generate a second set of bits that indicates updated information corresponding to whether the decoded address has been accessed; a first error correction code (ECC) engine configured to combine the first set of bits and the generated second set of bits to update the first set of bits, wherein the first ECC engine is further configured to generate a codeword for the updated first set of bits; and… the codeword for storage at the memory array [The rationale in the rejection of claim 2 is herein incorporated where Cheong teaches “ Thus, it is an objective of the present invention to generate an ECC for each request received within a memory device controller in a manner that does not require an extra cycle in order to generate the ECC.” (col. 3, lines 45-48) where “The ECC generation logic 20 operates on the n information bit of the entry to generate a new m-bit ECC.” (col. 3, lies 23-25) see ECC generation logic in (figs. 1 and 1B and related text)].
The combination of Cheong and White does not expressly disclose amplifier components configured to sense a first set of bits that indicates whether an address of the memory array has been accessed… latching components configured to latch; however, regarding these limitations Kajigawa teaches [“The read write units (for data bits) 31 includes a sense amplifier SADi, a register circuit RGDi, and a write driver WD. The read write units (for check bits) 32 includes a sense amplifier SACj, a register circuit RGCj, and a write driver WDC.” (par. 0036; fig. 2 and related text) where “a syndrome decoder using the syndrome to identify whether or not the first and second memory cells have an error and which one of the first and second memory cells has an error when the error exists; and an error correction unit that outputs an inverted control signal (INVi in FIG. 5;” (par. 0024) “the syndrome is decoded by a syndrome decoder possessed by the ECC control block 15, and the location of data where an error has occurred is identified (S15). Inverted control signals (INVi and INVj) are outputted to the register circuits (RGDi and RGCj) corresponding to the identified location, and the error is corrected by inverting data held by the register circuits (S16).” (par. 0086) and also teaches row decoder 16 where “A row decoder 16 is arranged adjacent to the memory cell array 20, and the row decoder 16 decodes a row address included in an address signal received from the address input terminals 5, and selects and activates one of the word lines (WL0 to WLm-1 in FIG. 3).” (par. 0033) “ In FIG. 5, the write driver WD includes a write control circuit 85 and a GBL driver 82 in detail, and details of the respective circuits are shown. In FIG. 5, sense latch circuit 84 has a portion including the sense amplifier SADi and the data register circuit RGDi.” (par. 0061; fig. 5 and related text)].
Cheong, White and Kajigaya are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong and White to include a structure including amplifier… decoder and latching as taught by Kajigaya since doing so would provide the benefits of [facilitating error correction in a semiconductor memory (par. 0023)].
Therefore, it would have been obvious to combine Cheong and White with Kayigaya for the benefit of creating a storage system/method to obtain the invention as specified in claim 17.
20. The apparatus of claim 17, wherein the decoder is configured to generate the second set of bits by being configured to: select a value for a bit corresponding to the decoded address, wherein the generated second set of bits includes the bit [The rationale in the rejection of claim 6 is herein incorporated].
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Cheong et al. (US 5,533,189) in view of White et al. (US 5,696,937) as applied in the rejection of claim 12 above, and further in view of Sharma (US 2004/0210722).
13. The method of claim 12, further comprising: receiving a read command for data associated with the codeword; and communicating the data in response to the read command for the data, [Cheong teaches “ Thus, minimizing ECC circuitry is very important in high frequency cache designs, because the ECC logic is often located on a critical path during the performance of read/write operations. Therefore, while ECC has become a must in high-reliability systems, to accommodate ECC without sacrifice and performance is a critical issue.” (col. 2, lines 21-26) “The director entry (Entry.sub.-- slct) read out from directory array 30 by a request and inputted into stage 32 is illustrated with n (=k +j) bits of information (a k bit tag and a j bit status) and m ECC check bits. One request processing operation determines whether to construct a new entry for directory 30 or to simply modify an existing directory entry. For the former, the tag accompanying the request will be used as the tag for the new directory entry. For the latter, the tag read out and selected (e.g., in the set associative cache) will be used. If a request finds the addressed entry, and the purpose of the request is to access (read or write) the data entry, then the same address tag should remain in the directory entry.” (col. 3, lines 1-18)] but the combination does not expressly disclose wherein communication of the data and communication of the portion of the codeword at least partially overlap in time; however, regarding these limitations, Sharma teaches [“memory controller 42 reads during cycles 5-8 the 1,024 data bits and the 128 ECC/tag directory bits of the first requested cache line via data bus 122 and first information bus 126 as indicated at 146 and 148, respectively. After reading the first cache line, memory controller 42 computes the ECC based on the modified tag directory bits associated with the first cache line.” (par. 0029) where a time overlap for the reads is shown in 146 and 148 (fig. 5 and related text)].
Cheong, White and Sharma are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong and White to expressly have the communication of the data and communication of the portion of the codeword at least partially overlap in time as taught by Sharma since doing so would facilitate accesses to the cache memory data and “reduce memory bandwidth losses” (par. 0034).
Therefore, it would have been obvious to combine Cheong, White and Sharma for the benefit of creating a storage system/method to obtain the invention as specified in claim 13.
14. The method of claim 13, wherein the portion of the codeword is communicated via one or more metadata pins and the data is communicated via one or more data busses [Cheong teaches “Referring to FIG. 2, there is illustrated a multiprocessor system for embodying the present invention. Note that the present invention may also be implemented within a uniprocessor system. Processors 202, 204 and 206 include caches and are coupled via control, address and data bus 208 to memory controller 210, which is coupled to system memory 212, high performance input/output ("I/O") device 220, and I/O channel controllers 214, 216 and 218. I/O channel controller 214 is coupled to system I/O and native I/O 260. I/O channel controllers 214, 216 and 218 are also coupled to I/O busses within a microchannel bus. Note, the aforementioned devices are also coupled to system controller 230… The directory control logic of the present invention may be implemented along with any one of the caches within processors 202, 204 and 206 or within memory controller 210.” (col. 4, lines 51-67; fig. 2 and related text) where ECCs are communicated via metadata pins (see figs. 1A-1B and 2 and related text). Sharma teaches “memory controller 42 reads during cycles 5-8 the 1,024 data bits and the 128 ECC/tag directory bits of the first requested cache line via data bus 122 and first information bus 126 as indicated at 146 and 148, respectively. After reading the first cache line, memory controller 42 computes the ECC based on the modified tag directory bits associated with the first cache line.” (par. 0029) where information is read via information bus 126 which corresponds to metadata pins].
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Cheong et al. (US 5,533,189) in view of White et al. (US 5,696,937) and Kajigaya (US 2015/0074493), and further in view of Benisty et al. (US 2018/0069658).
19. The apparatus of claim 17, wherein the first ECC engine is configured to generate the codeword by being configured to: perform ECC encoding on the updated first set of tag bits, wherein the codeword comprises the updated first set of tag bits and a set of parity bits that is for the updated first set of tag bits [The rationale in the rejection of claim 5 is herein incorporated but the combination of Cheong, White, Kajigaya and Benisty applied to claim 19 instead of the combination of Cheong, White and Benisty].
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Cheong et al. (US 5,533,189) in view of White et al. (US 5,696,937) as applied in the rejection of claim 2 above, and further in view of McFarling (US 2005/0172079).
23. (New) The combination of Cheong and White teaches The method of claim 2, wherein combining the first set of bits with the generated second set of bits comprises: [see combining as applied above with respect to claim 2] but does not expressly disclose combining the first set of bits with the generated second set of bits using one or more logic OR operations; however, regarding these limitations, [McFarling teaches “ When an entry is loaded and replaced multiple times, the usage bits may be logically combined (e.g., a logical OR operation) with the previous usage bits for this section of memory. The usage bits may be stored in table according to the tag that corresponds to the data related to the usage bits. By storing the usage bits according to the corresponding tags, the resulting table maintains the organization of the data in the cache. Once the usage bit is stored, processing proceeds to decision block 414.” (par. 0031)].
Cheong, White and McFarling are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Cheong and White to combine a first set of bit with a second set of bits by performing one or more logic OR operations as taught by McFarling, since doing so would provide the benefits of identifying changes in the bits, for future reference (see par. 0031.
Therefore, it would have been obvious to combine Cheong, White and McFarling for the benefit of creating a storage system/method to obtain the invention as specified in claim 23.
ACKNOWLEDGEMENT OF ISSUES RAISED BY APPLICANT
Response to Amendment
Applicant's arguments filed on 12/1/2025 with respect to the 35 USC 103 rejections have been fully considered but they are not deemed persuasive.
As required by M.P.E.P. § 707.07(f), a response to these arguments appears below.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Claims must be given the broadest reasonable interpretation during examination and limitations appearing in the specification but not recited in the claim are not read into the claim (See M.P.E.P. 2111 [R-1]).
With respect to claims 2 and 21, Applicant argues “the Office Action admits that the “address tag bits” of Cheong do not include access information and instead relies on the “status bits” of Cheong as allegedly including “access information”… at least the address tag bits of Cheong are not applicable to “a first set of bits that indicates whether the decoded address has been accessed” “a second set of bits that indicates updated information corresponding to whether the decoded address has been accessed” or “combining the first set of bits with the generated second set of bits to update the first set of bits”… According to Cheong, the status bits “include a valid bit” and “also may include a modified (dirty) bit which indicates whether the valid data entry contains a new value.”… Cheong describes updating the status bits, which may include “setting the valid bit,” “clearing the valid bit,” “setting the modify bit,” or “generating new values of the status bits.”… the Office Action appears to allege that “combining the first set of tag bits with the generated second set of tag bits to update the first set of tag bits,” as recited in previously presented claim 2, is disclosed by combining an address tag portion of an entry with new status bits… However… the address tag bits of Cheong do not indicate “whether the decoded address has been accessed,” as recited with respect to both the first set of bits and the second set of bits in claim 2. Therefore the address tag bits of Cheong are not applicable to either the claimed “first set of bits” or “second set of bits.”… the address tag bits of Cheong – alone or in combination with the status bits of Cheong – do not disclose “combining the first set of bits with the generated second set of bits to update the first set of bits,”… Cheong does not disclose combining the status bits with any other bits, and therefore Cheong does not disclose “combining the first set of bits with the generated second set of bits to update the first set of bits….”.
In response, these arguments have been fully considered but are not deemed persuasive.
First, note that pending claims 2 and 21 do not contain any requirement or limitation dictating how the claimed combining occurs; thus, the claimed combining has been interpreted according to the broadest reasonable interpretation. The claims also do not define the first set of bits or second set of bits other than by stating that they indicate whether the address has been accessed, and a set of bits including additional information which still includes bits that indicate whether the address has been accessed is not precluded from reading on the first set of bits or second set of bits. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Note that the combination of the address tag and status bits read from directory array 30 in fig. 1A before any modifications are made in Cheong may be interpreted to correspond to the first set of bits [Note that since the claim requires the first set of bits to include access information, the combination of address tag and status bits in Cheong corresponds to these bits since it includes status bits which include access information. The combination of address tag and status bits read from directory array 30 in fig. 1A before any modifications are made. “the address tag is in the input tag, and is available in stage 31” (Col. 5, lines 33-35) “An updated directory entry requiring a new ECC most often only requires a portion of the entry updated. When an existing directory entry is modified, only the status bits are changed and the address tag read from directory 30 stay unchanged” (col. 5, lines 24-29).]. The second set of bits may be interpreted as the updated set of status bits are generated in box 17 in fig. 1B and related text. [Cheong explains “The decoded request type is received by logic circuitry within block 15, which is utilized to select within multiplexer 14 between the tag inputted with the request and the tag received from directory array 30. The selected tag is then passed on and inserted into block 16 in order to generate the tag portion of the ECC with mkx ECC logic circuitry 16… In general, the decoded request type from the decode operation in stage 31 is acted on by block 15… From the response type from block 15 and the decode request types, block 17 decides which status bits need to be updated. For example, a request that triggers a load of a new data entry from the next lower level of memory will need to set the valid bit. Also, a castout request from the current level of memory will need to clear the valid bit; or, a write from the next higher level cache will set the modify bit. Depending on the complexity of the control logic, in a complex design block 17 may also take the status bits from the entry.sub.-- slct as input in order to generate new values of the status bits.” (col. 5, line 50 – col. 6, line 14)].
Applicant’s arguments appear to misconstrue the interpretation of the combining by stating that “by combining an address tag portion of an entry with new status bits… However… the address tag bits of Cheong do not indicate “whether the decoded address has been accessed,”” since this is not how the claimed combining has been interpreted since the combination of old address and status bits (first set of bits) of Cheong is combined with second set of bits (updated status bits) such as to update the status bits portion into a new set of bits or updated first bits (including address portion and updated status bits). Note that [According to Cheong, the directory entry comprising address tag and status bits from box 30 in fig. 1A is combined with new status bits generated in box 17 in fig. 1B by taking address tag portion from the entry in 30 and combining it with New status bits generated in box 17; thus combining a first set of tag bits including address bits and status bits from 32A into updated entry at 33A which includes address tag TAG(0:k-1) and New status (0:j-1). See figs. 1A and 1B and related text. Note that the combination of TAG(0:k-1) and status bits New status (0:j-1) in FIG. 1B corresponds to an updated first set of tag bits as it has updated the status bit portion of the from box 30. Note that the claimed combining has not been defined in such a way such as to preclude this interpretation].
Regarding all other Claims not specifically traversed above and whose rejections were upheld, the Applicant contends that the listed claims are allowable by virtue of their dependence on other allowable claims. As this dependence is the sole rationale put forth for the allowability of said dependent claims, the Applicant is directed to the Examiner's remarks above. Additionally, any other arguments the Applicant made that were not specifically addressed in this Office Action appeared to directly rely on an argument presented elsewhere in the Applicant’s response that was traversed, rendered moot or found persuasive above.
All arguments by the applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated 12/1/2025.
CLOSING COMMENTS
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 2-3, 5-14, 17 and 19-23 have received an action on the merits and are subject to a final rejection.
a(2) CLAIMS NO LONGER UNDER CONSIDERATION
Claims 1, 4, 15-16 and 18 have been canceled.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIMA RIGOL whose telephone number is (571)272-1232. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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January 30, 2025
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135