DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant's request for reconsideration of the rejection of the last Office action is persuasive and, therefore, the 102 rejection of that action is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-9, 15, 20-21 and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Neoh (US 2020/0125335 A1) in view of Dulong et al. (US 5,815,421, hereinafter Dulong).
Regarding claim 1, Neoh discloses an apparatus as shown in figure 3 comprising: a Data Mover and Transformer (DMT) configured to transform a first data array retrieved from a first memory into a second data array to be stored in a second memory as shown in figure 1, the DMT comprising: a Row to Column (R2C) transformer configured to transform a data sub-array into a transformed data sub-array by transforming one or more rows of the data sub-array into one or more respective columns of the transformed data sub-array ([0014], first local X-Y transpose operation transposes the rows of the matrices 101 in the first FFT dimension, in the X-dimension, to columns of the matrices 102 in the second FFT dimension, in the Y-dimension). Neoh differs from the claimed invention in not specifically teaching a memory reader to populate the data sub-array with data retrieved from the first memory according to a memory read pattern, wherein the memory read pattern is based on a predefined transformation from the first data array to the second data array; and a memory writer to write data from the transformed data sub-array to the second memory according to a memory write pattern, wherein the memory write pattern is based on the predefined transformation from the first data array to the second data array. However, Dulong teaches a method of transposing an array comprising an unpack operation to perform an unpack of the low-order data elements (read as memory read pattern) of Source 201, within register 204, and Source 200, within register 203, to generate Result 202, within register 205 (figure 2 and col. 6 lines 13-28, read on to populate the data sub-array with data retrieved from the first memory according to a memory read pattern, wherein the memory read pattern is based on a predefined transformation from the first data array to the second data array), and data element a(1) of Source 201, which resides in the lowest-order location within register 204, is stored in the second lowest-order location of result register 205, data element b(0) of Source 200, which resides in the second lowest-order location within register 203, is stored in the third lowest-order location of result register 205, and so forth, such that interleaving of Source 201 and Source 200 continues in this manner until register 205 is filled (col. 6 lines 18-34, read as to write data from the transformed data sub-array to the second memory according to a memory write pattern, wherein the memory write pattern is based on the predefined transformation from the first data array to the second data array) in order to easily manipulate data in memory array. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Neoh in having a memory reader to populate the data sub-array with data retrieved from the first memory according to a memory read pattern, wherein the memory read pattern is based on a predefined transformation from the first data array to the second data array; and a memory writer to write data from the transformed data sub-array to the second memory according to a memory write pattern, wherein the memory write pattern is based on the predefined transformation from the first data array to the second data array, as per teaching of Dulong, in order to easily manipulate data in memory array.
Regarding claim 2, Neoh teaches that two transpose engines may, for example, generate the memory access patterns to write/read to/from memory block 410 in order to provide a transposed matrix that feeds into 2 FFT engines that implement the functions of a multi-dimensional fast Fourier transform ([0025]), as well as Dulong teaches that unpack operation manipulates data elements by interleaving data from a first source with data from a second source to generate a result, i.e., the first source, second source, and result are given distinct address locations within the computer system memory; or each operation is performed by a corresponding instruction (col. 5 line 58 through col. 6 line 2) such that the unpack operation obviously includes an address pattern input to input read pattern information and write pattern information, wherein the memory reader is configured to determine the memory read pattern based on the read pattern information, wherein the memory writer is configured to determine the memory write pattern based on the write pattern information in order to easily manipulate data in memory array.
Regarding claim 8, Neoh teaches that the DMT is configured to transform the first data array into the second data array by performing a sequence of read/write cycles, a read/write cycle of the sequence of read/write cycles comprising: populating the one or more rows of the data sub-array by one or more respective memory entries retrieved by the memory reader from the first memory according to the memory read pattern; transforming the one or more rows of the data sub-array into the one or more respective columns of the transformed data sub-array; and writing data from one or more rows of the transformed data sub-array to one or more respective memory entries of the second memory according to the memory write pattern ([0014] and [0025], the first local X-Y transpose operation transposes the rows of the matrices 101 in the first FFT dimension to columns of the matrices 102 in the second FFT dimension, and two transpose engines may, for example, generate the memory access patterns to write/read to/from memory block 410 in order to provide a transposed matrix that feeds into 2 FFT engines that implement the functions of a multi-dimensional fast Fourier transform).
Regarding claim 9, Neoh teaches that the DMT is configured to configure at least one of a count of the rows in the data sub-array or a count of the columns in the data sub-array based on input R2C configuration information ([0018], matrix 200 can be transposed by writing the columns of the matrix in columns of a memory block, and then reading rows of matrix 200 from rows of the memory block).
Regarding claim 15, Neoh discloses that each of the first data array and the second data array comprises two or more dimensions (figure 1).
Regarding claim 20, the limitations are rejected as the same reasons as set forth in claim 1.
Regarding claim 21, the limitations are rejected as the same reasons as set forth in claim 2.
Regarding claim 23, the limitations are rejected as the same reasons as set forth in claim 8.
Regarding claim 24, the limitations are rejected as the same reasons as set forth in claim 1.
Regarding claim 25, the limitations are rejected as the same reasons as set forth in claim 8.
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Neoh (US 2020/0125335 A1) in view of Dulong et al. (US 5,815,421, hereinafter Dulong) as applied in claim 1 above and further in view of Mansell (WO 2021/229229 A1).
Regarding claims 10-14, the combination of Neoh and Dulong differs from the claimed invention in not specifically teaching that a count of the rows in the data sub-array and a count of the columns in the data sub-array are based on an element size of a data element in the first data array, wherein a count of the rows in the data sub-array is based on a memory entry size of the first memory, wherein a count of the rows in the data sub-array is based on a count of data elements of the first data array per memory entry of the first memory, wherein a count of the columns in the data sub-array is based on a memory entry size of the second memory, and wherein a count of the columns in the data sub-array is based on a count of data elements of the second data array per memory entry of the second memory. However, Mansell discloses that a count of the rows in the data sub-array and a count of the columns in the data sub-array are based on an element size of a data element in the first data array, wherein a count of the rows in the data sub-array is based on a memory entry size of the first memory, wherein a count of the rows in the data sub-array is based on a count of data elements of the first data array per memory entry of the first memory, wherein a count of the columns in the data sub-array is based on a memory entry size of the second memory, and wherein a count of the columns in the data sub-array is based on a count of data elements of the second data array per memory entry of the second memory (page 12 line 34 through page 13 line 13, provides sub-portion selection information to select which sub-portion of the portion of the matrix data structure in memory identified based on the addressing information is to be loaded to the operand storage circuitry when loading a given target row or column, and the sub-portion selection information can be used to narrow down which sub-portion of a row or column should be processed for a given operation as the layout of matrix data in memory may include rows or columns of a greater size than the block of matrix data to be operated on by a given set of matrix processing instructions). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Neoh and Dulong, in having that a count of the rows in the data sub-array and a count of the columns in the data sub-array are based on an element size of a data element in the first data array, wherein a count of the rows in the data sub-array is based on a memory entry size of the first memory, wherein a count of the rows in the data sub-array is based on a count of data elements of the first data array per memory entry of the first memory, wherein a count of the columns in the data sub-array is based on a memory entry size of the second memory, and wherein a count of the columns in the data sub-array is based on a count of data elements of the second data array per memory entry of the second memory, as per teaching of Mansell, in order to support more efficient 2D convolution operations.
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Neoh (US 2020/0125335 A1) in view of Dulong et al. (US 5,815,421, hereinafter Dulong) as applied in claim 1 above and further in view of Yi et al. (CN 103048644A as recited in Applicant’s IDS).
Regarding claims 16-19, the combination of Neoh and Dulong differs from the claimed invention in not specifically teaching a processor configured to generate radar information based on the second data array in the second memory, wherein the first data array in the first memory comprises first processed radar data arranged in the first data array according to a first radar-processing dimension, wherein the second data array is arranged according to a second radar-processing dimension to be processed by the processor, wherein the processor is configured to generate second processed radar data by processing data from the second data array according to the second radar-processing dimension, to store the second processed radar data in a third data array in the first memory, and to configure the DMT to transform the third data array from the first memory into a fourth data array to be stored in the second memory, the fourth data array is arranged according to a third radar-processing dimension to be processed by the processor, and wherein the second radar-processing dimension is different from the first radar-processing dimension, and the third radar-processing dimension is different from the second radar-processing dimension. However, Yi teaches a synthetic matrix transposition method of the synthetic aperture radar imaging system comprising synthetic aperture radar echo input matrix data, echo data matrix division and generation of read-write address, the echo matrix data in SDRAM, echo matrix transpose output of output cache unit and echo matrix data to configure the size of the sub matrix block, and perform optimal segmentation according to input echo raw data matrix of size in the transposition process ([0006]-[0013]) in order to improve the requirement of the data capacity of a memory and matrix transposition efficiency. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Neoh and Dulong in having a processor configured to generate radar information based on the second data array in the second memory, wherein the first data array in the first memory comprises first processed radar data arranged in the first data array according to a first radar-processing dimension, wherein the second data array is arranged according to a second radar-processing dimension to be processed by the processor, wherein the processor is configured to generate second processed radar data by processing data from the second data array according to the second radar-processing dimension, to store the second processed radar data in a third data array in the first memory, and to configure the DMT to transform the third data array from the first memory into a fourth data array to be stored in the second memory, the fourth data array is arranged according to a third radar-processing dimension to be processed by the processor, and wherein the second radar-processing dimension is different from the first radar-processing dimension, and the third radar-processing dimension is different from the second radar-processing dimension, as per teaching of Yi, in order to improve the requirement of the data capacity of a memory and matrix transposition efficiency.
Allowable Subject Matter
Claims 3-7 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach nor suggest “wherein the read pattern information comprises read sub-address information to define a plurality of read sub-address sequences, the memory read pattern is based on a combination of the plurality of read sub-address sequences, wherein the write pattern information comprises write sub-address information to define a plurality of write sub-address sequences, the memory write pattern is based on a combination of the plurality of write sub-address sequences” as recited in claim 3; and “wherein the read pattern information comprises read sub-address information to define a plurality of read sub-address sequences, the memory read pattern is based on a combination of the plurality of read sub-address sequences, wherein the write pattern information comprises write sub-address information to define a plurality of write sub-address sequences, the memory write pattern is based on a combination of the plurality of write sub-address sequences” as recited in claim 22.
Claims 4-7, are also objected because of depending on claim 3, containing the same allowable subject matter.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ZHUO H LI/Primary Examiner, Art Unit 2133