DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
The objections to claims 5 and 12 have been withdrawn in light of Applicant’s amendments.
Response to Arguments
Applicant's arguments filed 8/31/2026 have been fully considered but they are not persuasive. On pages 10 and 11 of Applicant’s remarks, Applicant argues that Appelt does not anticipate claim 1 because it does not disclose a connector having a thickness matching the separation of the dies. However, since the term “connector” is relatively broad, the wiring layer and the bumps can be collectively regarded as a connector. When viewed in this manner, the connector of Appelt would still meet all of the limitations, as amended.
On pages 11 and 12 of Applicant’s remarks, Applicant argues that Chung does anticipate the newly amended features from claims 8 and 15 of the inner and outer surfaces and the connection sites, and further that one would not be motivated to modify Chung to include this feature. While Chung does not explicitly recite this feature, this feature is obvious over Appelt, similarly to how it was applied to the originally filed claim 12. Since Applicant hasn’t given any specific arguments against this combination beyond the generic “Nor would a person skilled in the art be motivated to modify Chung to include this feature”, claims 8 and 15 are unpatentable over Chung in view of Appelt (see 103 rejections below for details).
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
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Claims 1, 3-4, and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Appelt et al. (US 20180145060 A1), hereinafter referred to as "Appelt".
Regarding claim 1, Appelt discloses a semiconductor package, comprising: a substrate (622 in figure 5); a first die attached over the substrate (22 in figure 5); a second die stacked on a top surface of the first die (12 in figure 5), wherein the second die and the top surface of the first die are separated by a vertical separation (up and down separation between 12 and 22 in figure 5); a connector positioned at least partially between the first and second dies (16 and 28 on the right side of figure 5. They collectively connect, and can thus be considered a connector), the connector having a thickness matching the vertical separation (the part of the connector that includes both 16 and 28 spans all the way from first die 22 to second die 12, and thus that thickness matches the vertical separation between those dies) and including a distal end portion located away from the first and second dies (end portion in line with edge of 24); and a mold material over the substrate and the first and second dies (14, 24, 34, 44, and 54 in figure 5).
Regarding claim 3, Appelt discloses all of the limitations of claim 1. Appelt further discloses that the mold material at least partially exposes the distal end portion (figure 5, right end of 16 is not covered by encapsulant mold).
Regarding claim 4, Appelt discloses all of the limitations of claim 1. Appelt further discloses that the connector is a first laterally extending connector extending past a first peripheral edge of the first die (16 extends past the right peripheral edge of the first die 22), the semiconductor package further comprising: a second laterally extending connector extending past a second peripheral edge of the first die (16 and 28 on the left side of figure 5, which extends past the left peripheral edge), wherein the vertical separation is greater than a second thickness of the second laterally extending connector (the part of the connector that does not have the part 28 has a thickness less than that of the separation of the dies).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
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Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Appelt in view of Vadhavkar et al. (US 20160343687 A1), hereinafter referred to as "Vadhavkar".
Regarding claim 2, Appelt discloses all of the limitations of claim 1. Appelt does not teach that the first die has a Through Silicon Via (TSV).
In the same field of endeavor of stacked semiconductor die packages, Vadhavkar teaches the first die has a Through Silicon Via (140 in Vadhavkar figure 1). Vadhavkar also teaches that these are utilized to electrically interconnect the dies vertically, which allows for vertical stacking of semiconductor die, which reduces the footprint of the device (Vadhavkar paragraph 0003).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the through-silicon vias from Vadhavkar to the device of Appelt in order to electrically interconnect the dies and reduce the footprint.
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Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Appelt.
Regarding claim 6, Appelt discloses all of the limitations of claim 1. Appelt further discloses that the connector is a first connector, and the distal end portion of the connector is a first distal end portion, the connector extending laterally past peripheral edges of the first and second dies (first connector extends past right peripheral edges of the dies);
In this embodiment Appelt does not disclose a third die over the second die.
In a separate embodiment, Appelt teaches a configuration that has a third die stacked on a top surface of the second die (92 in figure 23); a second connector positioned at least partially between the second and third dies and extending laterally past peripheral edges of the second and third dies (56a and attached bump in figure 23, which is between 12 and 92), the second connector including a second distal end portion located away from the second and third dies (end of 56 extended away from the dies); and a connector interconnect extending at least partially vertically and directly connecting the first and second distal end portions (53 and 13 in figure 23), wherein the connector is encapsulated within the mold material (encapsulated in mold 14, 24, 34, and 94 in figure 23).
This allows more dies to be stacked as a part of the structure. Appelt teaches that these packages can form a full system (Appelt paragraph 0053), and different full systems might require a different number of dies. Thus, one would want to add additional dies to create a full system within the package. Furthermore, the connector interconnect electrically couples these extra dies.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the third die and interconnects from the other embodiment of Appelt in order to stack additional dies as part of the package.
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Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Appelt in view of Chung Qwan Ho (KR 100743649 B1), hereinafter referred to as "Chung".
Regarding claim 7, Appelt discloses all of the limitations of claim 1.
In the same field of endeavor of stacked semiconductor die packages, Chung teaches the substrate is a first substrate and includes a first mounting surface extending along a first direction (200 in Chung figure 2), the package further comprising: a second substrate arranged along a second direction orthogonal to the first direction (CF in Chung figure 2), wherein the second substrate has a second mounting surface arranged orthogonal to the first mounting surface (side of CF); an additional substrate having a corresponding surface, wherein the corresponding surface of the additional substrate is orthogonal to a surface of the first substrate (additional CF on left side of Chung figure 2, [not labeled]). Chung also teaches that these are used to electrically connect the stacked dies to electrodes on the substrate (Chung page 4, lines 3-12).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the orthogonal substrates of Chung to the device of Appelt in order to electrically connect the dies to circuitry on the substrate.
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Claims 8-10, and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Appelt.
Regarding claim 8, Chung discloses a semiconductor package, comprising: a first substrate having a first surface with a pair of opposing peripheral edges (200 in Chung figure 2); a second substrate having a second inner surface opposite a second outer surface with both second inner and outer surfaces extending generally orthogonal to the first surface (CF in figure 2. It has inner surface facing the die stack and outer surface opposite that, and both are perpendicular to the first surface), wherein: the second substrate is attached to the first substrate, and the first and second substrates are non-integral (200 and CF are attached, and separate pieces, and so are non-integral); at least one die over the first surface (21, 220, 230, and 240 in figure 2), wherein at least one die includes a third surface generally orthogonal to the second inner and outer surfaces (tops of the dies are parallel with 200 and perpendicular to the left and right surfaces of CF); and at least one wire directly coupling contact points on the second inner surface and the third surface (wires 260a/260b/260c/260d).
Chung does not disclose a connection site on the second side.
Appelt teaches that the second substrate includes a connection site having a conductive material on the second outer surface configured to be electrically coupled to an external circuit (89 in Appelt figure 19), the conductive material extending along a vertical direction across the second outer surface (each connection 89 extends along the vertical direction in figure 19). Appelt teaches that this connects it to a side package (Appelt paragraph 0102), and that these external connections can be used for connecting to other semiconductor dice or passive devices or adjacent packages (Appelt paragraph 0056), which is good because it allows more compact design since the connections are closer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the connection site of Appelt to the device of Chung in order to have compact connections between adjacent packages or passive devices.
Regarding claim 9, Chung in view of Appelt discloses all of the limitations of claim 8. Chung further discloses a third die separated from the first surface of the first substrate by a first distance (230 in figure 2), wherein the second substrate includes an edge separated from the first surface of the first substrate by a second distance greater than or equal to the first distance (top edge of CF is above top surface of 230).
Regarding claim 10, Chung in view of Appelt discloses all of the limitations of claim 8. Chung further discloses that the at least one wire extends from the second inner surface of the second substrate to at least one of (a) the first surface of the first substrate, or (b) an outermost portion of the at least one die (wires 260a/260b/260c/260d extend to an outermost portion of the dies 210/220/230/240).
Regarding claim 12, Chung in view of Appelt discloses all of the limitations of claim 8. The combined device shows that the at least one wire is electrically coupled to the conductive material (wires 260a/260b/260c/260d are electrically coupled to the conductive patterns on CF, see Chung translation page 4 lines 3-12, which is also where the connection sites of Appelt would need to connect to in order to connect to other packages. Thus, these would be coupled together).
Regarding claim 13, Chung in view of Appelt teaches all of the limitations of claim 8.
Appelt further teaches that the conductive material corresponds to an array of contacts (array of 5 contacts 89 in Appelt figure 19).
Regarding claim 14, Chung in view of Appelt discloses all of the limitations of claim 8. Chung further discloses a mold material at least partially covering the at least one die, the first surface, the second inner surface, or a combination thereof (Chung translation page 5, lines 6-11).
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Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Appelt as applied to claim 8 above, and further in view of Lin (US 20140084445 A1), hereinafter referred to as “Lin”.
Regarding claim 11, Chung in view of Appelt discloses all of the limitations of claim 8. Chung does not teach that the second substrate is attached to the first substrate via a uniform bonding material over the first surface.
In the same field of endeavor of stacked semiconductor die packages, Lin teaches the second substrate is attached to the first substrate via a uniform bonding material over the first surface (174 in Lin figure 6A). Lin also teaches that this bonding material is used because it has a high thermal conductivity, which allows for increased heat transfer out of the dies and through the substrates (Lin paragraph 0031).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the second substrate using the bonding material of Lin in order to facilitate faster thermal conduction away from the dies.
Claims 15-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Appelt.
Regarding claim 15, Chung discloses a first substrate having a first surface (200 in figure 2); a second substrate having a second inner surface opposite a second outer surface with both second inner and outer surfaces extending generally orthogonal to the first surface (CF in figure 2. It has inner surface facing the die stack and outer surface opposite that, and both are perpendicular to the first surface), wherein the first and second substrates are non-integral (200 and CF are separate pieces, and so are non-integral); and at least one die over the first surface (210, 220, 230, and 240 in figure 2), wherein the at least one die includes a third surface generally orthogonal to the second inner surface (top surface of any of the dies is perpendicular to side surface of CF); wherein components on the first, second, and/or third surfaces are electrically coupled to each other (CF has several conductive patterns that connect the dies to electrodes on the circuit board 200 through the wire bonds. Page 4, lines 3-12 of machine translation); a plurality of wirebonds extending from the second inner surface of the second substrate to at least one of (a) the first surface of the first substrate, or (b) an outermost portion of the at least one die (wires 260a/260b/260c/260d).
Chung does not disclose a connection site on the second side.
Appelt teaches that the second substrate includes a connection site having a conductive material on the second outer surface configured to be electrically coupled to an external circuit (89 in Appelt figure 19), the conductive material extending along a vertical direction across the second outer surface (each connection 89 extends along the vertical direction in figure 19). Appelt teaches that this connects it to a side package (Appelt paragraph 0102), and that these external connections can be used for connecting to other semiconductor dice or passive devices or adjacent packages (Appelt paragraph 0056), which is good because it allows more compact design since the connections are closer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the connection site of Appelt to the device of Chung in order to have compact connections between adjacent packages or passive devices.
Regarding claim 16, Chung in view of Appelt discloses all of the limitations of claim 15. Chung further discloses that the first substrate is a base substrate (200 is at the base of the package) and the second substrate is a side substrate attached to the base substrate (CF is attached to the side of 200) and extending vertically away from the base substrate (CF extends vertically above 200).
Regarding claim 19, Chung in view of Appelt discloses all of the limitations of claim 15. Chung further discloses a mold material encapsulating the at least one die and at least partially covering the first surface, the second inner surface, or both (Chung page 5, lines 6-11).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Appelt as applied to claim 15 above, and further in view of Lin.
Regarding claim 17, Chung in view of Appelt discloses all of the limitations of claim 8. Chung in view of Appelt does not teach that the second substrate is attached to the first substrate via a uniform bonding material.
Lin teaches the first substrate and the second substrate are attached to one another via a bonding material extending vertically along each of the first substrate and the second substrate (174 in Lin figure 6A). Lin also teaches that this bonding material is used because it has a high thermal conductivity, which allows for increased heat transfer out of the dies and through the substrates (Lin paragraph 0031).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the second substrate using the bonding material of Lin in order to facilitate faster thermal conduction away from the dies.
Regarding claim 18, Chung discloses all of the limitations of claim 15. Chung in view of Appelt does not disclose a plurality of additional substrates.
Lin teaches a plurality of additional substrates surrounding the at least one dies (76 in Lin figure 6A. paragraph 0032). Furthermore, Lin teaches that multiple heat spreading paths improves heat efficiency (paragraph 0034).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the multiple additional substrates of Lin in order to improve the heat efficiency of the semiconductor package.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3-4, and 6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. US 10453820 B2 in view of Appelt.
Claim
Current Application
US 10453820 B2 claim 1
1
A semiconductor package, comprising:
a substrate; [1]
a first die attached over the substrate; [5]
a second die stacked on a top surface of the first die; [5]
wherein the second die and the top surface of the first die are separated by a vertical separation [26]
a connector positioned at least partially between the first and second dies, [15]
the connector having a thickness matching the vertical separation [27]
and including a distal end portion located away from the first and second dies; [16]
and a mold material over the substrate and the first and second dies. [14]
A semiconductor package, comprising:
a first substrate having a first surface; [1]
a second substrate having an outermost edge and a second surface generally orthogonal to the first surface; [2]
one or more dies over the first surface, [5]
wherein an outermost die of the one or more dies includes a third surface generally orthogonal to the second surface; [6]
a plurality of wirebonds extending from the second surface of the second substrate to at least one of (a) the first surface of the first substrate, or (b) the third surface of the outermost die; and further comprising: [7]
a mold material disposed over the first substrate and at least partially covering the one or more dies and the wirebonds, [14]
wherein the mold material includes a fourth surface generally co-planar with the outermost edge of the second substrate.
3
The semiconductor package of claim 1, [1, 5, 14-16]
wherein the mold material at least partially exposes the distal end portion [17]
4
The semiconductor package of claim 1, [1, 5, 14-16]
further comprising: die interconnects disposed between and electrically coupling the first and second dies, [18]
wherein the connectors provide a vertical separation between the first and second dies, [19]
and wherein the vertical separation is greater than a thickness of the connector. [20]
In regards to claim 1, ‘820 claim 7 has all of the limitations, except [15], [16], [26], and [27]. Appelt teaches a stacked die structure wherein the second die and the top surface of the first die are separated by a vertical separation (up and down separation between 92 and 52 in figure 23); a connector positioned at least partially between the first and second dies (56a and connected bump on the right side of figure 23. They collectively connect, and can thus be considered a connector), the connector having a thickness matching the vertical separation (the part of the connector that includes both 56a and the bump spans all the way from first die 92 to second die 52, and thus that thickness matches the vertical separation between those dies) and including a distal end portion located away from the first and second dies (end portion in line with edge of 94); Appelt uses the connector, circuit, to electrically connect the die to other layers, and the edge of the package to be connected to other neighboring packages or devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the connector of Appelt to arrive at the claimed invention in order to connect the dies to outside packages or devices.
In regards to claim 3, the limitations of claim 1 are discussed above. The limitation added by claim 3 is further taught by Appelt: the mold material at least partially exposes the distal end portion (figure 23, right end of 56 is not covered by encapsulant mold).
In regards to claim 4, the limitations of claim 1 are discussed above. The limitation added in claim 4 is taught by Appelt: the connector is a first laterally extending connector extending past a first peripheral edge of the first die (56a extends past the right peripheral edge of the first die 92), the semiconductor package further comprising: a second laterally extending connector extending past a second peripheral edge of the first die (56a and connected bump on the left side of figure 23, which extends past the left peripheral edge), wherein the vertical separation is greater than a second thickness of the second laterally extending connector (the part of the connector that does not have the bump has a thickness less than that of the separation of the dies). This feature is the same as the connector described above and is thus obvious for the same reasons given there.
In regards to claim 6, the limitations of claim 1 are discussed above. The additional limitations added in claim 6 are taught by Appelt: the connector is a first connector and the distal end portion of the connector is a first distal end portion, the connector extending laterally past peripheral edges of the first and second dies (first connector 56a extends past edges of the dies); further comprising: a third die stacked on a top surface of the second die (22 in figure 23); a second connector positioned at least partially between the second and third dies and extending laterally past peripheral edges of the second and third dies (16 in figure 23), the second connector including a second distal end portion located away from the second and third dies (end of 16 extended away from the dies); and a connector interconnect extending at least partially vertically and directly connecting the first and second distal end portions (13 and 53 in figure 23), wherein the connector is encapsulated within the mold material (encapsulated in mold 14, 24, 34, 54, and 94 in figure 23). Appelt also teaches that these are to electrically connect the semiconductor dice. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the connector interconnect of Appelt to arrive at the claimed invention in order to electrically connect the semiconductor dies.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. US 10453820 B2 in view of Appelt and further in view of Vadhavkar.
In regards to claim 2, the limitations of claim 1 are discussed above. The limitation added in claim 2 is taught by Vadhavkar: the first die has a Through Silicon Via (140 in Vadhavkar figure 1). Vadhavkar also teaches that are utilized to electrically interconnect the dies vertically, which allows for vertical stacking of semiconductor die, which reduces the footprint of the device (Vadhavkar paragraph 0003). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the through-silicon vias from Vadhavkar to arrive at the claimed invention in order to electrically interconnect the dies and reduce the footprint.
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 8, respectively of U.S. Patent No. US 10453820 B2 in view of Appelt.
Claim
Current Application
Claim
US 10453820 B2 claim 1
7
The semiconductor package of claim 1, [1, 5, 14-16, 26-27]
wherein the substrate is a first substrate
and includes a first mounting surface extending along a first direction, [1]
the package further comprising: a second substrate arranged along a second direction orthogonal to the first direction, [2]
wherein the second substrate has a second mounting surface arranged orthogonal to the first mounting surface; [2]
an additional substrate having a corresponding surface, [24]
wherein the corresponding surface of the additional substrate is orthogonal to a surface of the first substrate. [25]
8
A semiconductor package, comprising:
a first substrate having a first surface; [1]
a second substrate having a second surface generally orthogonal to the first surface; [2]
one or more dies over the first surface, [5]
wherein an outermost die of the one or more dies includes a third surface generally orthogonal to the second surface; [6]
a plurality of wirebonds extending from the second surface of the second substrate to at least one of (a) the first surface of the first substrate, or (b) the third surface of the outermost die; [7]
a third substrate having a third surface; [24]
a fourth substrate having a fourth surface;
and a fifth substrate having a fifth surface;
wherein, the third, fourth and fifth surfaces are each generally orthogonal to the first surface. [25]
Regarding claim 7, ‘820 claim 8 has all the limitations of claim 1 except [14]-[16] and [26-27]. Appelt teaches a stacked die structure wherein the second die and the top surface of the first die are separated by a vertical separation (up and down separation between 92 and 52 in figure 23); a connector positioned at least partially between the first and second dies (56a and connected bump on the right side of figure 23. They collectively connect, and can thus be considered a connector), the connector having a thickness matching the vertical separation (the part of the connector that includes both 56a and the bump spans all the way from first die 92 to second die 52, and thus that thickness matches the vertical separation between those dies) and including a distal end portion located away from the first and second dies (end portion in line with edge of 94); and a mold material over the substrate and the first and second dies (14, 24, 34, 54, and 94 in Appelt figure 23). Appelt uses the connector, circuit layer 26, to electrically connect the die to other layers, and the edge of the package to be connected to other neighboring packages or devices. Furthermore, the mold encapsulation material provides structural support to the die package. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the connector and mold material of Appelt to arrive at the claimed invention in order to connect the dies to outside packages or devices and provide support to the die package.
The additional limitations introduced in claim 7 are found in ‘820 claim 1 (see above table).
Claims 8, 10, 12, and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. US 10453820 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim
Current Application
Claim
US 10453820 B2
8
A semiconductor package, comprising:
a first substrate having a first surface with a pair of opposing peripheral edges; [1]
a second substrate having a second inner surface opposite a second outer surface [9]
with both second inner and outer surfaces extending generally orthogonal to the first surface, [2]
wherein: the second substrate includes a connection site having a conductive material on the second outer surface configured to be electrically coupled to an external circuit, [11]
the conductive material extending along a vertical direction across the second outer surface [28]
the second substrate is attached to the first substrate, [3]
and the first and second substrates are non-integral; [4]
at least one die over the first surface, [5]
wherein at least one die includes a third surface generally orthogonal to the second inner and outer surfaces; [6]
and at least one wire directly coupling contact points on the second inner surface and the third surface.[7]
1
A semiconductor package, comprising:
a first substrate having a first surface, [1]
wherein the first substrate includes a plurality of first bond pads at the first surface;
a second substrate having a second surface generally orthogonal to the first surface, [2]
wherein: the second substrate is rigidly attached directly to the first substrate [3]
via a bonding material, [8]
and the second substrate includes a plurality of second bond pads at the second surface;
one or more dies over the first surface, [5]
wherein an outermost die of the one or more dies includes a third surface generally orthogonal to the second surface; [6]
and a plurality of wirebonds extending from the second surface of the second substrate to at least one of (a) the first surface of the first substrate, or (b) the third surface of the outermost die, [7]
wherein the plurality of wirebonds extend between the first bond pads and the second bond pads.
10
The semiconductor package of claim 8, wherein the at least one wire extends from the second surface of the second substrate to at least one of (a) the first surface of the first substrate, or (b) an outermost surface of the at least one die. [7]
2
The semiconductor package of claim 1 [1-7, see above]
wherein the second substrate includes a first side and a second side opposite the first side,
wherein the second surface is at the first side, [9]
and wherein the second side includes an external connection site having an exposed conductive material configured to be electrically coupled to an external package. [11]
15
A semiconductor package, comprising:
a first substrate having a first surface; [1]
a second substrate having a second inner surface opposite a second outer surface [9]
with both second inner and outer surfaces extending generally orthogonal to the first surface, [2]
wherein the first and second substrates are non-integral; [4]
wherein: the second substrate includes a connection site having a conductive material on the second outer surface configured to be electrically coupled to an external circuit, [11]
the conductive material extending along a vertical direction across the second outer surface [28]
and at least one die over the first surface, [5]
wherein the at least one die includes a third surface generally orthogonal to the second inner surface; [6]
wherein components on the first, second, and/or third surfaces are electrically coupled to each other; [8]
a plurality of wirebonds extending from the second inner surface of the second substrate to at least one of (a) the first surface of the first substrate, or (b) an outermost portion of the at least one die. [7]
In regards to claim 8, claim 1 of US 10453820 B2 (hereinafter referred to as ‘820) has limitations [1]-[3] and [5]-[7]. With limitation [1], it would be obvious to have the substrate surface have a pair of opposing peripheral edges, since it is difficult to imagine a common substrate that would not have these. Limitation [4], “and the first and second substrates are non-integral” would have been obvious to one of ordinary skill in the art, since limitations [3] and [8] in claim 1 of ‘820 recite that two substrates are attached together with a bonding material, which makes one envision a non-integral structure. For limitation [28], since all 2D objects extend in all directions, the conductive material would extend in a vertical direction.
In regards to claim 10, see above chart.
Regarding claim 12, since the connection sites are configured to connect to external packages, it would be obvious that the wirebonds which couple the dies to the second substrate which has these connection sites would need to be coupled to the connection sites.
In regards to claim 15, claim 1 of ‘820 has limitation [1]-[2] and [5]-[7]. Limitations [4] and [28] are discussed in the section on claim 8. Limitation [8] “wherein components on the first, second, and/or third surfaces are electrically coupled to each other” would have been obvious to one of ordinary skill in the art because claim 1 in ‘830 recites wirebonds between these surfaces, which would electrically couple these surfaces together.
Claims 9, 14, 16, and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. US 10453820 B2 in view of Chung.
In regards to claim 9, the limitations of claim 8 are discussed above. The limitation added in claim 9 is taught by Chung: a third die separated from the first surface of the first substrate by a first distance, (230 in Chung figure 2) wherein the second substrate includes an edge separated from the first surface of the first substrate by a second distance greater than or equal to the first distance (top of CF in Chung figure 2). Chung teaches that the connection film CF is there to connect the dies to the substrate while minimizing the length of the bond wires (Chung page 3, lines 9-12, page 4, 16-17), and thus it is natural to have it extend up higher than the third die. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second substrate extend higher than the third die as in Chung in order to limit the length of the bond wires.
In regards to claim 14, the limitations of claim 8 are discussed above. The limitation added in claim 14 is taught by Chung: a mold material at least partially covering: the at least one die, the first surface, the second inner surface, or a combination thereof (Chung page 5, lines 6-11). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the encapsulating mold of Chung in order to rigidly protect the components of the die stack and the bond wires.
In regards to claim 16, the limitations of claim 15 are discussed above. Claim 1 from US 10453820 B2 does not explicitly recite that the second substrate extends vertically away from the base substrate. Chung teaches the first substrate is a base substrate (200 in Chung figure 2) and the second substrate is a side substrate attached to the base substrate and extending vertically away from the base substrate. (CF in Chung figure 2). Chung teaches that the connection film CF is there to connect the dies to the substrate while minimizing the length of the bond wires (Chung page 3, lines 9-12, page 4, 16-17), and thus it is natural to have it extend up in the vertical direction. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second substrate extend in the vertical direction as in Chung in order to limit the length of the bond wires.
In regards to claim 19, The limitations of claim 15 are discussed above. The limitation added in claim 19 is taught by Chung: a mold material encapsulating: the at least one die and at least partially covering the first surface, the second inner surface, or both (Chung page 5, lines 6-11). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the encapsulating mold of Chung in order to rigidly protect the components of the die stack and the bond wires.
Claims 11, and 17-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. US 10453820 B2 in view of Lin.
In regards to claim 11, the limitations of claim 8 are discussed above. Claim 11 adds the limitation “wherein the second substrate is attached to the first substrate via a uniform bonding material over the first surface.” Claim 1 of US 10453820 B2 recites that the substrates are bonded, but not specifically that it is a uniform bonding material. Lin teaches a uniform bonding material (174 in Lin figure 6A. It is 1 single, uniform layer of a Thermal Interface Material adhesive). Lin also teaches that this bonding material is used because it has a high thermal conductivity, which allows for increased heat transfer out of the dies and through the substrates (Lin paragraph 0031). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the second substrate using the bonding material of Lin in order to facilitate faster thermal conduction away from the dies.
In regards to claim 17, the limitations of claim 15 are discussed above. Claim 17 adds the limitation “wherein the first substrate and the second substrate are attached to one another via a bonding material extending vertically along each of the first substrate and the second substrate.” Claim 1 of US 10453820 B2 recites that the substrates are bonded, but not specifically that the bonding material extends vertically. Lin teaches the bonding material extending vertically (174 in Lin figure 6A. It extends vertically and is along both substrates). Lin also teaches that this bonding material is used because it has a high thermal conductivity, which allows for increased heat transfer out of the dies and through the substrates (Lin paragraph 0031). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the second substrate using the bonding material as disposed in Lin in order to facilitate faster thermal conduction away from the dies.
In regards to claim 18, The limitations of claim 15 are discussed above. The new limitation is taught by Lin. Lin teaches a plurality of additional substrates surrounding the at least one dies (76 in Lin figure 6A. paragraph 0032). Furthermore, Lin teaches that multiple heat spreading paths improves heat efficiency (paragraph 0034). Therefore, it would have been obvious to one of ordinary skill in the art to have the multiple additional substrates of Lin in order to improve the heat efficiency of the semiconductor package.
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. US 10453820 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Current Application
US 10453820 B2
The semiconductor package of claim 8,
wherein the conductive material corresponds to an array of contacts. [12]
The semiconductor package of claim 2
wherein the conductive material corresponds to an array of contacts. [12]
In regards to claim 13, the dependency on claim 12 is covered by ‘820 claim 3’s dependency on ‘820 claim 2 (see discussion above). The additional limitations are recited in ‘820 claim 3 (see chart above).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
