DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I invention, claims 1-19, and withdrawing claim 20, in the reply filed on August 26, 2026, is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8-14, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. Pub. 2023/0008539) in view of Lim (U.S. Pub. 2018/0350830).
Regarding claims 1 and 12, Lee [Figs.4-5] discloses a 3D memory device, including:
a stacked structure, including a plurality of conductive layers and a plurality of insulating layers alternately stacked [GST]; and
at least one channel structure [CH], penetrating from a top surface of the stacked structure to a bottom surface of the stacked structure, wherein the least one channel structure includes a top portion and a bottom portion [Fig.4];
a 3D memory device, including:
a stacked structure, including a plurality of word lines and a plurality of insulating layers alternately stacked [GST] [Paras.42-44]; and
a plurality of channel structures [CH], penetrating through the stacked structure, wherein each of the plurality of channel structures includes a top portion and a bottom portion.
Lee [Para.70] discloses the channel holes [115] having narrower width at the bottom portions. Lee fails to explicitly disclose the claimed bottom to top width ratio. However, Lim [Figs.12-14] discloses and makes obvious to obtain a channel structure with minimal width variations along its vertical length [Para.94],
wherein a ratio of a first width of the bottom portion of the at least one channel structure surrounded by one of the plurality of conductive layers to a second width of the top portion of the at least one channel structure surrounded by another one of the plurality of conductive layers is in a range from 0.85 to 0.95;
wherein a ratio of a first width of the bottom portion of the plurality of channel structures surrounded by one of the plurality of word lines to a second width of the top portion of the plurality of word lines surrounded by another one of the plurality of word lines is in a range from 0.85 to 0.95.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to incorporate the teachings of Lim into the method of Lee to provide the claimed channel structure width ratio. The ordinary artisan would have been motivated to modify Lee in the manner set forth above for at least the purpose of obtaining a better quality device having a high degree of uniformity of electrical characteristics among its various different memory sections in a vertical direction [Lim; Para.102]. Additionally, it would have been obvious to apply a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 2-3 and 13-14, Lee [Figs.4-5] and Lim [Figs.12-14] disclose a 3D memory device,
wherein the first width is disposed at the bottom portion of the at least one channel structure surrounded by the bottommost conductive layer of the plurality of conductive layers;
wherein the second width is disposed at the top portion of the at least one channel structure surrounded by the topmost conductive layer of the plurality of conductive layers.
Regarding claims 8-11 and 19, Lee [Figs.4-5] and Lim [Figs.12-14] disclose a 3D memory device
wherein the at least one channel structure [CH] includes:
an insulating pillar [143], extending downwards through the stacked structure;
a channel layer [141], surrounding the insulating pillar; and
a charge storage structure [137], surrounding the channel layer [Lee; Fig.5C];
wherein the charge storage structure includes a tunneling layer, a charge storage layer and a blocking layer, and the tunneling layer, the charge storage layer and the blocking layer surround the channel layer in this sequence [131,133,135] [137] [Lee; Fig.5C];
further including a substrate located under the bottom portion of the at least one channel structure [STL_S/SUB] [Lee; Fig.4];
further including a substrate located over the top portion of the at least one channel structure [STL_S/SUB] [Lee; Fig.4].
Allowable Subject Matter
Claims 4-7 and 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not fairly disclose or make obvious the claimed device/method taken as a whole, and specifically, the limitations of
wherein one of the insulating layers includes a first insulating layer and a second insulating layer, and the second insulating layer is located between the first insulating layer and the at least one channel structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art is considered analogous art and discloses at least some of the claimed subject matter of the current invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BAC H AU/Primary Examiner, Art Unit 2898
