DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ryou et al. (US Pat. App. Pub. No. 2018/0308638) in view of Po (US 6,066,537).
With respect to claim 1, Ryou teaches a hybrid capacitor comprising: a silicon substrate (see FIG. 2, element 110 and paragraph [0030]); a first capacitor pattern (see FIG. 2, element 140 and paragraph [0046]) disposed on the silicon substrate along a plurality of first trenches (see FIG. 2, element 130 and paragraph [0046]); a layer formed on the silicon substrate on which the first capacitor pattern is disposed (see FIG. 2, element 121); a second capacitor pattern disposed on the layer along a plurality of second trenches (see FIG. 2, capacitor pattern 160 and trenches 150); and a through-hole configured to electrically connect the first capacitor pattern and the second capacitor pattern (see FIG. 2, through-hole electrode 171 and paragraph [0074]) .
Ryou fails to teach that layer on the silicon substrate with the second capacitor pattern disposed thereon is an oxide layer.
Po, on the other hand, teaches an oxide layer with a second capacitor pattern disposed thereon. See FIG. 2, layer 25, and col. 3, lines 36-45. Such an arrangement results in a known electrically insulated layer which also isolates the capacitor structures from noise and other unwanted signals. See col. 3, lines 36-45.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify Ryou, as taught by Po, in order to provide an electrically insulated layer that further isolates the capacitor structures from noise and other unwanted signals.
With respect to claim 9, Ryou teaches a method of manufacturing a hybrid capacitor, the method comprising: forming a plurality of first trenches in a silicon substrate (see FIG. 8 and paragraph [0094]); forming a first capacitor pattern on the silicon substrate along the plurality of first trenches (see FIG. 9 and paragraph [0096]); forming a layer on the first capacitor pattern (see FIG. 12 and paragraph [0112]); forming a plurality of second trenches in the oxide layer (see FIG. 13 and paragraph [0115]); forming a second capacitor pattern on the layer along the plurality of second trenches (see FIG. 14 and paragraph [0118]); and forming a through-hole passing through at least a portion of the second capacitor pattern and the layer (see FIG. 16, element 172c’ and paragraph [0131]), wherein the through-hole includes a conductive connection pattern configured to electrically connect the first capacitor pattern and the second capacitor pattern (see FIG. 17, element 172b and paragraph [0132]) .
Ryou fails to teach that layer on the silicon substrate with the second capacitor pattern disposed thereon is an oxide layer.
Po, on the other hand, teaches an oxide layer with a second capacitor pattern disposed thereon. See FIG. 2, layer 25, and col. 3, lines 36-45. Such an arrangement results in a known electrically insulated layer which also isolates the capacitor structures from noise and other unwanted signals. See col. 3, lines 36-45.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify Ryou, as taught by Po, in order to provide an electrically insulated layer that further isolates the capacitor structures from noise and other unwanted signals.
Claims 2-8 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ryou et al. (US Pat. App. Pub. No. 2018/0308638) in view of Po (US 6,066,537), and further, in view of Chen et al. (US 7,561,407).
With respect to claim 2, the combined teachings of Ryou and Po fail to teach that the first capacitor pattern is arranged in a first direction on an upper surface of the silicon substrate, and the second capacitor pattern is arranged in a second direction intersecting the first direction on an upper surface of the oxide layer.
However, Chen, on the other hand, teaches that the first capacitor pattern is arranged in a first direction on an upper surface of the silicon substrate, and the second capacitor pattern is arranged in a second direction intersecting the first direction on an upper surface of the oxide layer. See FIGS. 1A-1F. Such an arrangement results in reduced parasitic resistance and inductance. See col. 1, lines 44-54.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify the combined teachings of Ryou and Po, as taught by Chen, in order to reduce parasitic resistance and inductance.
With respect to claim 3, the combined teachings of Ryou, Po, and Chen teach that the first capacitor pattern is arranged in the first direction on the upper surface of the silicon substrate, and the second capacitor pattern is arranged perpendicular to the first direction on the upper surface of the oxide layer. See Chen, FIG. 2.
With respect to claim 4, the combined teachings of Ryou, Po, and Chen teach that the plurality of first trenches are spaced apart from each other at a preset interval on the silicon substrate and are each formed to have a preset depth from an upper surface of the silicon substrate. See Ryou, paragraph [0035]).
With respect to claim 5, the combined teachings of Ryou and Po teach that each of the plurality of second trenches is formed to correspond to a preset number of the plurality of first trenches in the oxide layer and is formed at the same interval and the same depth as each of the plurality of first trenches. See Ryou, paragraph [0057], noting that the width and depth of the second trenches are taught to be a design choice determined by desired capacitance of the second capacitor layer.
With respect to claim 6, the combined teachings of Ryou, Po, and Chen teach that the first capacitor pattern includes a first capacitor electrode layer formed on the upper surface of the silicon substrate along the plurality of first trenches, a first capacitor dielectric layer formed to cover at least one surface of the first capacitor electrode layer, and a second capacitor electrode layer formed to cover at least one surface of the first capacitor dielectric layer. See Ryou, FIG. 2, elements 141, 142, 145, and paragraph [0036].
With respect to claim 7, the combined teachings of Ryou, Po, and Chen teach that the second capacitor pattern includes a third capacitor electrode layer formed on the upper surface of the oxide layer along the plurality of second trenches, a second capacitor dielectric layer formed to cover at least one surface of the third capacitor electrode layer, and a fourth capacitor electrode layer formed to cover at least one surface of the second capacitor dielectric layer. See Ryou, FIG. 2, elements 161, 162, 165, and paragraph [0058].
With respect to claim 8, the combined teachings of Ryou, Po, and Chen teach that the first capacitor pattern further includes at least one first additional capacitor dielectric layer formed to cover the second capacitor electrode layer, and at least one first additional electrode layer arranged to alternate with the at least one first additional capacitor dielectric layer, and the second capacitor pattern further includes at least one second additional capacitor dielectric layer formed to cover the fourth capacitor electrode layer, and at least one second additional electrode layer arranged to alternate with the at least one second additional capacitor dielectric layer. See Ryou, FIG. 2, noting multiple dielectric layers 145 and 165, additional electrode layers 141 and 161, and paragraphs [0039] and [0061].
With respect to claim 10, the combined teachings of Ryou and Po fail to teach that the forming of the first capacitor pattern includes forming the first capacitor pattern to extend in a first direction on an upper surface of the silicon substrate, and the forming of the second capacitor pattern includes forming the second capacitor pattern to extend perpendicular to an extending direction of the first capacitor pattern on an upper surface of the oxide layer.
However, Chen, on the other hand, teaches that the forming of the first capacitor pattern includes forming the first capacitor pattern to extend in a first direction on an upper surface of the silicon substrate, and the forming of the second capacitor pattern includes forming the second capacitor pattern to extend perpendicular to an extending direction of the first capacitor pattern on an upper surface of the oxide layer. See FIGS. 1A-1F. Such an arrangement results in reduced parasitic resistance and inductance. See col. 1, lines 44-54.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify the combined teachings of Ryou and Po, as taught by Chen, in order to reduce parasitic resistance and inductance.
With respect to claim 11, the combined teachings of Ryou, Po, and Chen teach that the forming of the first capacitor pattern includes forming a first capacitor electrode layer along an upper surface of the silicon substrate in which the plurality of first trenches are formed, forming a first capacitor dielectric layer on the first capacitor electrode layer, and forming a second capacitor electrode layer on the first capacitor dielectric layer. See Ryou, FIG. 9 and paragraph [0096].
With respect to claim 12, the combined teachings of Ryou, Po, and Chen teach that the forming of the second capacitor pattern includes forming a third capacitor electrode layer along an upper surface of the oxide layer in which the plurality of second trenches are formed, forming a second capacitor dielectric layer on the third capacitor electrode layer, and forming a fourth capacitor electrode layer on the second capacitor dielectric layer. See Ryou, FIG. 14 and paragraph [0118].
With respect to claim 13, the combined teachings of Ryou, Po, and Chen teach that the forming of the first capacitor pattern further includes forming at least one first additional capacitor dielectric layer and at least one first additional capacitor dielectric layer on the second capacitor electrode layer to alternate with each other, and the forming of the second capacitor pattern further includes forming at least one second additional capacitor dielectric layer and at least one second additional capacitor dielectric layer on the fourth capacitor electrode layer to alternate with each other. See Ryou, paragraphs [0122]-[0123].
With respect to claim 14, the combined teachings of Ryou, Po, and Chen teach that the forming of the second capacitor pattern includes forming the second capacitor pattern having a corresponding shape at a position vertically corresponding to a shape of the first capacitor pattern. See Ryou, FIG. 14.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ryou et al. (US Pat. App. Pub. No. 2018/0308638) in view of Po (US 6,066,537), and further, in view of Lu et al. (US Pat. App. Pub. No. 2020/0066443).
With respect to claim 15, the combined teachings of Ryou and Po fail to teach that after the forming of the first capacitor pattern, removing a portion of a bottom surface of the silicon substrate.
Lu, on the other hand, teaches that after the forming of the first capacitor pattern, removing a portion of a bottom surface of the silicon substrate. See paragraph [0124]. Such an arrangement results in the ease of connection to a lower electrode that connects to an external apparatus. See FIG. 26.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify the combined teachings of Ryou and Po, as taught by Lu, in order to reduce parasitic resistance and inductance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shin et al. (US 2019/0096587), Kim et al. (US 2014/0092524), and Hwang (US 2009/0141426) each teach three-dimensional capacitor stacks wherein trench capacitors are stacked on top of each other, but fail to teach the recited oxide layer and through-hole electrodes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DION R FERGUSON whose telephone number is (571)270-7566. The examiner can normally be reached Monday-Friday, 5:30 a.m. - 4:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DION R. FERGUSON/Primary Examiner, Art Unit 2847
Prosecution Insights