DETAILED ACTION
Response to Amendment
1. Amendments filed on 09/11/2025 have been entered. Claims 1 and 17 have been amended.
Response to Arguments
2. Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public liuse, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. Claim(s) 1-5, 7-15, 17-20 are is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Su et al (US 2022/0101770).
As to claim 1, Su teaches a display panel, comprising:
N types of display areas, and the N types of display areas comprise an i-th type display area (out1, out4, and out6, fig. 16A), a j-th type display area (out2 and out5, fig. 16A) and a g-th type display area (out3, fig. 16A);
a display process of the display panel comprises a data writing time period (when the gate signal is high as illustrated in fig. 16A) and a light- emitting time period (the rest of period in the frame after the gate signal as illustrated in fig. 16A);
a data writing time period of the i-th type display area (out1, out4, and out6, fig. 16A), a data writing time period of the j-th type display area (out2 and out5, fig. 16A) and a data writing time period of the g-th type display area (out3, fig. 16A) overlap ([0107] as shown in FIG. 16A, the clock signals CLK1 to CLK14 are sequentially shifted by H, so that output signals OUT1 to OUT14 of shift registers GOA1 to GOA14 are sequentially shifted by H. Examiner’s note: since the width of the gate signal is 6H and the signal is shifted by 1H, then signals from OUT1 to OUT6 overlap), and a light-emitting time period of the i-th type display area, the light-emitting time period of the j-th type display area and a light-emitting time period the g- th type display area at least partially do not overlap (see Fig. 16A), wherein N is an integer greater than or equal to two, each of I ,j and g is an integer greater than zero and less than or equal to N, and I ,j and g are not equal with each other (I = 3, j = 2, and g = 1, fig. 16A);
the display panel comprises M display parts (two display parts), wherein M is an integer greater than or equal to two;
the M display parts comprise a first display part (the first display part includes out1, out2, and out3, fig. 16A) and a second display part (the second display part includes out4, out5, and out6, fig. 16A), the first display part comprises at least one i-th type display area (out1, fig. 16A), and the second display part comprises at least one i-th type display area (out4, fig. 16A);
at least one j-th type display area (out2, fig. 16A) and at least one g-th type display area (out3, fig. 16A) are arranged between the at least one i-th type display area (out1, fig. 16A) comprised in the first display part (the first display part includes out1, out2, and out3, fig. 16A) and the at least one i-th type display area (out4, fig. 16A) comprised in the second display part (the second display part includes out4, out5, and out6, fig. 16A); and
a first write data signal is written into sub-pixels comprised in the first display part (the first display part includes out1, out2, and out3, fig. 16A) during a first data writing time period (period from the first horizontal period to the third horizontal period, fig. 16A), and a second write data signal is written into sub-pixels comprised in the second display part (the second display part includes out4, out5, and out6, fig. 16A) during a second data writing time period (period from the fourth horizontal period to the sixth horizontal period, fig. 16A).
As to claim 2, Su teaches the display panel, wherein a start time of the light- emitting time period of the i-th type display area (out1, fig. 16A) is earlier than a start time of the light-emitting time period of the j-th type display area (out2, fig. 16A).
As to claim 3, Su teaches the display panel, wherein an end time of the data writing time period of the j-th type display area (out2, fig. 16A) is earlier than the start time of the light- emitting time period of the i-th type display area (out4, fig. 16A).
As to claim 4, Su teaches the display panel, wherein the light-emitting time period of the i-th type display area (out1, fig. 16A) and the light-emitting time period of the j-th type display area (out2, fig. 16A) do not overlap (the light emitting period of out1 and out2 at least do not partially overlap, fig. 16A).
As to claim 5, Su teaches the display panel, wherein the data writing time period (that is the partial data write period of out2, fig. 16A) is between the light-emitting time period of the i-th type display area (out1, fig. 16A) and the light-emitting time period of the j-th type display area (out2, fig. 16A).
As to claim 7, Su teaches the display panel, wherein the M display parts are arranged along a column direction (see fig. 16A), and for at least one of the M display parts (for example, the first display part includes out1, out2, and out3, fig. 16A), a write data signal is written into each sub pixel comprised in said display part during one data writing time period (a period from out1 to out3, fig. 16A).
As to claim 8, Su teaches the display panel, wherein one of the M display parts comprises a plurality of i-th type display areas (out1, out4, and out6, fig. 16A), wherein the plurality of i-th type display areas are arranged along the column direction (fig. 16A), and the plurality of i-th type display areas are not adjacent to each other (out1, out4, and out6 are not adjacent to each other as illustrated in fig. 16A).
As to claim 9, Su teaches the display panel, wherein the light-emitting time period of the i-th type display area (the lighting period of the previous frame of out1, fig. 16A) and the light-emitting time period of the j-th type display area (the lighting period of the current frame out2, fig. 16A) are located between two adjacent data writing time period (data writing period of the present frame out1 and the data writing period of the present frame out2, fig. 16A).
As to claim 10, Su teaches the display panel, wherein the first display part (the first display part includes out1, out2, and out3, fig. 16A) and the second display part (the second display part includes out4, out5, and out6, fig. 16A) comprise a same type and the same number of display areas among the N types of display areas (both comprises I, j, and g); and an arrangement order of types of display areas in the first display part is the same as an arrangement order of types of display areas in the second display part in a column direction (both display parts comprise both comprises I, j, and g in the same order, see fig. 16A).
As to claim 11, Su teaches the display panel, wherein the display panel comprises a plurality of pixel rows arranged along the column direction, sub-pixels in each pixel row are arranged along a row direction, and the row direction intersects the column direction([0091] s shown in FIG. 8A , in the first mode, output signals OUT1 to OUT10 of the gate driving circuit 600 are sequentially shifted by H, so as to implement row by row scanning of sub-pixels); and one of the N types of display areas comprises one pixel row ([0091] the first mode… to implement row by row scanning of sub-pixels).
As to claim 12, Su teaches the display panel, wherein the display panel comprises a plurality of pixel rows arranged along the column direction, sub-pixels in each pixel row are arranged along a row direction, and the row direction intersects the column direction ([0107] output signals of the two adjacent stages of shift registers are synchronized, while the output signals of the two adjacent stages of shift registers are shifted by 2H relative to output signals of the next two adjacent stages of shift registers, thereby implementing two-rows by two-rows scanning of sub-pixels); and one of the N types of display areas comprises at least two pixel rows ([0107, fig. 16B).
As to claim 13, Su teaches the display panel, wherein each of the M display parts comprises the N types of display areas (out1, out2, out3 in the first display part and out4, out5, out6 in the second display part), and arrangement orders of the N types of display areas in the M display parts are the same in the column direction (see fig. 16A).
As to claim 14, Su teaches the display panel, wherein the first display part comprises n types of display areas (three out1, out2, and out3, fig. 16A), wherein n is an integer less than or equal to N, the n types of display areas are arranged sequentially along a column direction (out1, out2, and out3 as illustrated in fig. 16A), light-emitting time periods of the n types of display areas do not overlap (the light emitting periods of out1, out2, and out3 are at least partially do not overlap as illustrated in fig. 16A), and the n types of display areas emit lights sequentially along the column direction (see fig. 16A).
As to claim 15, Su teaches the display panel, wherein data writing time periods of the n types of display areas overlap (the data writing period (the high period of the signals out1-out6) at least partially overlap, fig. 16A).
As to claim 17, Su teaches a method for driving a display panel,
wherein the display panel comprises N types of display areas, and the N types of display areas comprise an i-th type display area (out1, out4, and out6, fig. 16A), a j-th type display area (out2 and out5, fig. 16A) and a g-th type display area (out3, fig. 16A);
a display process of the display panel comprises a data writing time period (when the gate signal is high as illustrated in fig. 16A) and a light- emitting time period (the rest of period in the frame after the gate signal as illustrated in fig. 16A);
a data writing time period of the i-th type display area (out1, out4, and out6, fig. 16A), a data writing time period of the j-th type display area (out2 and out5, fig. 16A) and a data writing time period of the g-th type display area (out3, fig. 16A) overlap ([0107] as shown in FIG. 16A, the clock signals CLK1 to CLK14 are sequentially shifted by H, so that output signals OUT1 to OUT14 of shift registers GOA1 to GOA14 are sequentially shifted by H. Examiner’s note: since the width of the gate signal is 6H and the signal is shifted by 1H, then signals from OUT1 to OUT6 overlap), and a light-emitting time period of the i-th type display area, the light-emitting time period of the j-th type display area and a light-emitting time period the g- th type display area at least partially do not overlap (see Fig. 16A), wherein N is an integer greater than or equal to two, each of I, j and g is an integer greater than zero and less than or equal to N, and i, j and g are not equal with each other (I = 3, j = 2, and g = 1, fig. 16A);
the display panel comprises M display parts (two display parts), wherein M is an integer greater than or equal to two;
the M display parts comprise a first display part (the first display part includes out1, out2, and out3, fig. 16A) and a second display part (the second display part includes out4, out5, and out6, fig. 16A), the first display part comprises at least one i-th type display area (out1, fig. 16A), and the second display part comprises at least one i-th type display area (out4, fig. 16A);
at least one j-th type display area (out2, fig. 16A) and at least one g-th type display area (out3, fig. 16A) is arranged between the at least one i-th type display area (out1, fig. 16A) comprised in the first display part (the first display part includes out1, out2, and out3, fig. 16A) and the at least one i-th type display area (out4, fig. 16A) comprised in the second display part (the second display part includes out4, out5, and out6, fig. 16A); and
a first write data signal is written into sub-pixels comprised in the first display part (the first display part includes out1, out2, and out3, fig. 16A) during a first data writing time period (period from the first horizontal period to the third horizontal period, fig. 16A), and a second write data signal is written into sub-pixels comprised in the second display part (the second display part includes out4, out5, and out6, fig. 16A) during a second data writing time period (period from the fourth horizontal period to the sixth horizontal period, fig. 16A);
wherein the method comprises:
in a first time period, controlling sub-pixels comprised in the i-th type display area to emit lights (out1, out4, and out6, fig. 16A); and
in a second time period, controlling sub-pixels comprised in the j-th type display area to emit lights (out2 and out5, fig. 16A);
wherein the first time period and the second time period do not overlap (periods for out1, out4, and out6 and periods for out2 and out5 at least do not partially overlap, fig. 16A).
As to claim 18, Su teaches the method, wherein the display panel comprises a first display part (the first display part includes out1, out2, and out3, fig. 16A), and the first display part comprises the i-th type display area (out1, fig. 16A) and the j-th type display area (out2, fig. 16A); wherein the method further comprises: in a third time period (previous frame period), writing a data signal to each type display area in the first display part (out1, out2, and out3, fig. 16A); wherein an end time of the third time period (previous frame period, fig. 16A) is earlier than at least one of the following: a start time of the first time period (present frame period); and a start time of the second time period (next time period).
As to claim 19, Su teaches the method, wherein the display panel further comprises a second display part (the second display part includes out4, out5, and out6, fig. 16A), the second display part comprises the i-th type display area (out4, fig. 16A) and the j-th type display area (out5, fig. 16A), and the i-th type display area of the first display part (out1, fig. 16A) and the i-th type display area of the second display part (out4, fig. 16A) both emit lights during the first time period (see fig. 16A).
As to claim 20, Su teaches the method, wherein a data writing time period of the first display part (the first display part includes out1, out2, and out3, fig. 16A) is earlier than a data writing time period of the second display part (the second display part includes out4, out5, and out6, fig. 16A); wherein in the first time period, the i-th type display area of the first display part emits lights based on a data signal of a current frame (out1 of the first display part includes out1, out2, and out3, fig. 16A), and the i-th type display area of the second display part (out4 of the first display part includes out4, out5, and out6, fig. 16A) emits lights based on a data signal of a previous frame (fig. 16A illustrates the light emitting period of out4, out5, and out6 of previous period corresponding to the current frame of out1, out2 and out3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al (US 2022/0101770) in view of Zhou et al (US 2022/0335894).
As to claim 6, Su does not teach the display panel as claimed.
However, Zhou teaches the display panel, wherein an interval t between light- emitting time periods of two types of display areas with adjacent light-emitting time periods satisfies at least one of the following: the interval t is greater than or equal to 1 microsecond (fig. 6 illustrates adjacent emitting rows having non overlapping light-emitting time periods); and the interval t is less than or equal to T/2 (fig. 6 obviously illustrates adjacent emitting rows having non overlapping light-emitting time periods with the gap less than T/2); wherein T represents a duration of a light-emitting time period (see fig. 6).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to include the teachings of Zhou. The motivation would have been in order to provide “a driving method, so as to avoid the problem that a leakage current generated between adjacent light-emitting elements” ([0005]).
5. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al (US 2022/0101770) in view of Shigeta et al (US 2020/0265777).
As to claim 16, Su does not teach the display panel as claimed.
However, Shigeta teaches the display panel, wherein the display panel comprises sub-pixels (sub-pixel, fig. 9A) and a pixel driving circuit (PWM pixel circuit 120, fig. 6A); the pixel driving circuit comprises: a pulse width modulation module (a fourth transistor 125, fig. 6A), configured to receive at least a sweep signal (sweep voltage, fig. 6A), provide a pulse width setting signal and control a light emitting time of at least one of the sub-pixels ([0086] a pulse width modulation (PWM) pixel circuit for controlling the pulse width (or the duty ratio or the driving time) of a driving current provided to a light emitting element); the driving transistor, configured to output a driving current based on a signal of a gate of the driving transistor and a signal of a first end of the driving transistor (fig. 6A, [0139]); and the light emitting control module, configured to control the sub-pixels to emit a light in response to the driving current under control of a light emitting control signal ([0147], fig. 6A); and among the N types of display areas, sub-pixels in the same type of display area share the sweep signal and the light emitting control signal (fig. 6B illustrates sweep voltage and first driving signal).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to include the teachings of Shigeta. The motivation would have been in order to provide “a display panel wherein a data voltage can be stably set and a high light emission duty ratio can be secured” ([0011]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
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/AMEN W BOGALE/ Examiner, Art Unit 2628
/NITIN PATEL/ Supervisory Patent Examiner, Art Unit 2628