DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/12/2026 has been entered.
Response to Amendment
1. Amendments filed on 01/12/2026 have been received. Claims 1, 10, and 19 have been amended, claims 4-6, and 13-15 have been canceled, and new claim 21 has been added.
Response to Arguments
2. Applicant’s arguments with respect to claim(s) 1-3, 7-12, and 16-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. Claim(s) 1-3, 8-12, and 17-20 and is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 2021/0210003).
As to claim 1, Kim teaches a display panel, comprising:
N types of display areas (the N type include the first and the third odd Emi_PWM lines, and one even second line, Emi_PWM line, fig. 14) and M display parts (the display comprises two parts: a first display part including first, second, and third Emi-PWM lines, and a second display part including fourth and fifth Emi_PWM lines, fig. 14), wherein N is an integer greater than or equal to two (three, fig. 14), and M is an integer greater than or equal to two (two, fig. 14);
wherein the N types of display areas comprise an i-th type display area (odd Emi_PWM line, fig. 14) and a j -th type display area (even Emi_PWM line, fig. 14), and a light-emitting time period of sub-pixels in the i-th type display area and a light-emitting time period of sub-pixels in the j-th type display area at least partially do not overlap (Figure 14 illustrates that the signal of Emi_PWM(2) is delayed compared to the signal of Emi_PWM(1); thus, the signals do not fully overlap each other), wherein each of I (there are two odd lines, fig. 14) and j (there is one even line, fig. 14) is an integer greater than zero and less than or equal to N (three, fig. 14), and i is not equal to j (the first part include two odd lines, Emi_PWM lines, that are the first odd line and the third odd line and one even line);
wherein the M display parts comprise a first display part (the first display part including first, second, and third Emi-PWM lines, fig. 14) and a second display part (the second display part including the fourth and fifth Emi_PWM lines, fig. 14), the first display part comprises at least one i-th type display area (two odd lines, the first and the third lines, fig. 14) and at least one j-th type display area (one eve line, the second line, fig. 14), and the second display part comprises at least one i-th type display area (the fifth line, fig. 14) and at least one j-th type display area (the fourth line, fig. 14);
wherein an effective period of a sweep signal (Sweep, fig. 14) received by a pixel driving circuit connected to a sub-pixel and a light-emitting stage of the sub-pixel overlap (Emi_PWM, fig. 14);
wherein an operation process of the display panel comprises:
in a third time period, pixel driving circuits connected to sub-pixels in the i-th type display area and the j-th type display area in the first display part receive data signals;
in a first time period, sweep signals received by pixel driving circuits connected to at least sub-pixels in the i-th type display area in the first display part and at least sub-pixels in the i-th type display area in the second display part are in an effective time period;
in a fourth time period, pixel driving circuits connected to sub-pixels in the i-th type display area and the j-th type display area in the second display part receive data signals; and
in a second time period, sweep signals received by pixel driving circuits connected to at least sub-pixels in the j-th type display area in the first display part and at least sub-pixels in the j-th type display area in the second display part are in an effective time period; or,
wherein an operation process of the display panel comprises:
in a first time period (1 frame time, fig. 14), at least one of a sweep signal (Sweep(1), fig. 14) received by a pixel driving circuit connected to a sub-pixel in the i-th type display area (odd Emi_PWM line, fig. 14) in the first display part (the first display part including first, second, and third Emi-PWM lines, fig. 14) and a sweep signal (Sweep(2), fig. 14) received by a pixel driving circuit connected to a sub-pixel in the i-th type display area (odd Emi_PWM line, fig. 14) in the second display part (the second display part including the fourth and fifth Emi_PWM lines, fig. 14) is in an effective time period (emission period, fig. 14), and at least one of a pixel driving circuit connected to a sub-pixel in the j-th type display area (even Emi_PWM line, fig. 14) in the first display part (the first display part including first, second, and third Emi-PWM lines, fig. 14) and a pixel driving circuit connected to a sub-pixel in the j-th type display area (even Emi_PWM line, fig. 14) in the second display part (the second display part including the fourth and fifth Emi_PWM lines, fig. 14) receives a data signal (signal SP(n), fig. 14); and
in a second time period (in the next frame time next to the 1 frame time shown in fig. 14), at least one of a sweep signal (Sweep(1), fig. 14) received by a pixel driving circuit connected to a sub-pixel in the j-th type display area (even Emi_PWM line, fig. 14) in the first display part (the first display part including first, second, and third Emi-PWM lines, fig. 14) and a sweep signal (Sweep(2), fig. 14) received by a pixel driving circuit connected to a sub-pixel in the j-th type display area (even Emi_PWM line, fig. 14) in the second display part (the second display part including the fourth and fifth Emi_PWM lines, fig. 14) in an effective time period (emission period, fig. 14), and at least one of a pixel driving circuit connected to a sub-pixel in the i-th type display area (odd Emi_PWM line, fig. 14) in the first display part (the first display part including first, second, and third Emi-PWM lines, fig. 14) and a pixel driving circuit connected to a sub-pixel in the i-th type display area (odd Emi_PWM line, fig. 14) in the second display part receives a data signal (signal SP(n), fig. 14), or
in a second time period, at least one of a sweep signal received by a pixel driving circuit connected to a sub-pixel in the j-th type display area in the first display part and a sweep signal received by a pixel driving circuit connected to a sub-pixel in the j-th type display area in the second display part in an effective time period, and at least one of a pixel driving circuit connected to a sub-pixel in a c-th type display area in the first display part and a pixel driving circuit connected to a sub-pixel in a c-th type display area in the second display part receives a data signal, wherein c is an integer greater than zero and less than or equal to N, c is not equal to i, and c is not equal to j.
As to claim 2, Kim teaches the display panel, wherein the pixel driving circuit comprises at least one of a pulse width modulation module (a PWM circuit 111, fig. 12) and an amplitude modulation module (circuit 112, fig. 12), wherein the data signal is a pulse width data signal PWM_DATA (VDD_PWM, fig. 12) received by the pulse width modulation module (a PWM circuit 111, fig. 12); and/or the data signal is an amplitude data signal PAMDATA (VDD_PAM, fig. 12) received by the amplitude modulation (circuit 112, fig. 12) module ([0188] the sub pixel circuit 110 may control the brightness of light emitted by the inorganic light emitting element 120 by driving the inorganic light emitting element 120 through pulse amplitude modulation (PAM) and/or pulse width modulation (PWM)).
As to claim 3, Kim teaches the display panel, wherein the pulse width modulation module (PWM circuit 111, fig. 12) is configured to receive at least a sweep signal (Sweep(n), fig. 12) and output a pulse width setting signal (Emi_PWM); and/or, the amplitude modulation module (circuit 112, fig. 12) is configured to output an amplitude setting signal (Emi_PAM).
4-6. (Canceled)
As to claim 8, Kim teaches the display panel, wherein in the third time period (in the third frame time, fig. 14), the pixel driving circuits connected to the sub-pixels in the i-th type display area (odd Emi_PWM line, fig. 14) and the j-th type display area (even Emi_PWM line, fig. 14) in the first display part (the first display part including first, second, and third Emi-PWM lines, fig. 14) simultaneously or sequentially receive the data signals (SP(1) and SP(2), fig. 14); and/or in the fourth time period (in the fourth frame time, fig. 14), the pixel driving circuits connected to the sub-pixels in the i-th type display area (odd Emi_PWM line, fig. 14) and the j-th type display area (even Emi_PWM line, fig. 14) in the second display part (the second display part including the fourth and fifth Emi_PWM lines, fig. 14) simultaneously or sequentially receive the data signals (SP(1) and SP(2), fig. 14).
As to claim 9, Kim teaches the display panel, wherein an operation process of the display panel comprises:
in a first time period (1 frame time, fig. 14), at least one of a sub-pixel in the i-th type display area (odd Emi_PWM line, fig. 14) in the first display part (the first display part including first, second, and third Emi-PWM lines, fig. 14) and a sub-pixel in the i-th type display area (odd Emi_PWM line, fig. 14) in the second display part (the second display part including the fourth and fifth Emi_PWM lines, fig. 14) emits light (active Emi_PWM, fig. 14), and at least one of a pixel driving circuit connected to a sub-pixel in the j-th type display area (even Emi_PWM line, fig. 14) in the first display part (the first display part including first, second, and third Emi-PWM lines, fig. 14) and a pixel driving circuit connected to a sub-pixel in the j-th type display area in the second display part (the second display part including the fourth and fifth Emi_PWM lines, fig. 14) receives a data signal (SP, fig. 14);
wherein a duration of at least one of the pixel driving circuit connected to the sub-pixel in the j-th type display area (even Emi_PWM line, fig. 14) in the first display part (the first display part including first, second, and third Emi-PWM lines, fig. 14) and the pixel driving circuit connected to the sub-pixel in the j-th type display area (even Emi_PWM line, fig. 14) in the second display part (the second display part including the fourth and fifth Emi_PWM lines, fig. 14) receiving the data signal is less than a duration of a light-emitting stage of the sub pixel in at least one of the i-th type display area (odd Emi_PWM line, fig. 14) in the first display part (the first display part including first, second, and third Emi-PWM lines, fig. 14) and the i-th type display area (the fifth line, fig. 14) in the second display part (the second display part including the fourth and fifth Emi_PWM lines, fig. 14. Note that both the first and second display parts include three odd lines, whereas only two even lines are present in each part).
As to claim 10, Kim teaches a display panel, comprising:
N types of display areas (the N type include the first and the third odd Emi_PWM lines, and one even second line, Emi_PWM line, fig. 14) and M display parts (the display comprises two parts: a first display part including first, second, and third Emi-PWM lines, and a second display part including fourth and fifth Emi_PWM lines, fig. 14), wherein N is an integer greater than or equal to two (three, fig. 14), and M is an integer greater than or equal to two (two, fig. 14);
wherein the N types of display areas comprise an i-th type display area (odd Emi_PWM line, fig. 14) and a j-th type display area (even Emi_PWM line, fig. 14), and a light-emitting time period of sub-pixels in the i-th type display area and a light-emitting time period of sub-pixels in the j-th type display area at least partially do not overlap (Figure 14 illustrates that the signal of Emi_PWM(2) is delayed compared to the signal of Emi_PWM(1); thus, the signals do not fully overlap each other), wherein each of i (there are two odd lines, fig. 14) and j (there is one even line, fig. 14) is an integer greater than zero and less than or equal to N (three, fig. 14), and i is not equal to j (the first part include two odd lines, Emi_PWM lines, that are the first odd line and the third odd line and one even line);
wherein the M display parts comprise a first display part (the first display part including first, second, and third Emi-PWM lines, fig. 14) and a second display part (the second display part including the fourth and fifth Emi_PWM lines, fig. 14), the first display part comprises at least one i-th type display area (two odd lines, the first and the third lines, fig. 14) and at least one j-th type display area (one eve line, the second line, fig. 14), and the second display part comprises at least one i-th type display area (the fifth line, fig. 14) and at least one j-th type display area (the fourth line, fig. 14);
wherein an effective period of a sweep signal (Sweep, fig. 14) received by a pixel driving circuit connected to a sub-pixel and a light-emitting stage of the sub-pixel overlap (Emi_PWM, fig. 14);
wherein an operation process of the display panel comprises:
in a third time period, pixel driving circuits connected to sub-pixels in the i-th type display area and the j-th type display area in the first display part receive data signals;
in a first time period, sweep signals received by pixel driving circuits connected to at least sub-pixels in the i-th type display area in the first display part and sub-pixels in the i-th type display area in the second display part are in an effective time period; and
in a second time period, sweep signals received by pixel driving circuits connected to at least sub-pixels in the j-th type display area in the first display part and sub-pixels in the j-th type display area in the second display part are in an effective time period; or,
wherein an operation process of the display panel comprises:
in a first time period (1 frame time, fig. 14), a sweep signal (Sweep(1), fig. 14) received by a pixel driving circuit connected to a sub pixel in the i-th type display area (odd Emi_PWM line, fig. 14) is in an effective time period (emission period, figure. 14), and a pixel driving circuit connected to a sub pixel in the j-th type display area (even Emi_PWM line, fig. 14) receives a data signal (signal SP(n), fig. 14);
in a second time period (in the next frame time next to the 1 frame time shown in fig. 14), a sweep signal (Sweep(1), fig. 14) received by a pixel driving circuit connected to a sub pixel in the j-th type display area (even Emi_PWM line, fig. 14) is in an effective time period (emission period, figure. 14), and a pixel driving circuit connected to a sub pixel in the i-th type display area (odd Emi_PWM line, fig. 14) receives a data signal (signal SP(n), fig. 14), or
in a second time period, a sweep signal received by a pixel driving circuit connected to a sub pixel in the j-th type display area is in an effective time period, and a pixel driving circuit connected to a sub pixel in a c-th type display area receives a data signal, wherein c is an integer greater than zero and less than or equal to N, c is not equal to i, and c is not equal to j.
As to claim 11, Kim teaches the display panel, wherein the pixel driving circuit comprises at least one of a pulse width modulation module (a PWM circuit 111, fig. 12) and an amplitude modulation module (circuit 112, fig. 12), wherein the data signal is a pulse width data signal PWM_DATA received by the pulse width modulation module (VDD_PWM, fig. 12); and/or the data signal is an amplitude data signal PAM_DATA received by the amplitude modulation (VDD_PAM, fig. 12) module ([0188] the sub pixel circuit 110 may control the brightness of light emitted by the inorganic light emitting element 120 by driving the inorganic light emitting element 120 through pulse amplitude modulation (PAM) and/or pulse width modulation (PWM)).
As to claim 12, Kim teaches the display panel, wherein the pulse width modulation module (PWM circuit 111, fig. 12) is configured to receive at least a sweep signal (Sweep(n), fig. 12) and output a pulse width setting signal (Emi_PWM); and/or, the amplitude modulation module (circuit 112, fig. 12) is configured to output an amplitude setting signal (Emi_PAM).
13-15. (Canceled)
As to claim 17, Kim teaches the display panel, wherein in the third time period (in the third frame time, fig. 14), the pixel driving circuits connected to the sub-pixels in the i-th type display area (odd Emi_PWM line, fig. 14) and the j-th type display area (even Emi_PWM line, fig. 14) in the first display part (the first display part including first, second, and third Emi-PWM lines, fig. 14) simultaneously or sequentially receive the data signals (SP(1) and SP(2), fig. 14).
As to claim 18, Kim teaches the display panel, wherein an operation process of the display panel comprises: in a first time period (1 frame time, fig. 14), a sub pixel in the i-th type display area (odd Emi_PWM line, fig. 14) emits light (active Emi_PWM, fig. 14), and a pixel driving circuit connected to a sub pixel in the j-th type display area (even Emi_PWM line, fig. 14) receives a data signal (SP, fig. 14); wherein a duration of the pixel driving circuit connected to the sub-pixel in the j-th type display area (even Emi_PWM line, fig. 14) receiving the data signal is less than a duration of a light-emitting stage of the sub pixel in the i-th type display area (Note that the first display parts include two odd lines (i-th lines) and one even line (j-th line).
As to claim 19, Kim teaches a display device, comprising the display panel according to claim 1 (see the detail claim rejection of claim 1).
As to claim 20, Kim teaches a display device, comprising the display panel according to claim 10 (see the detail claim rejection of claim 10).
Allowable Subject Matter
4. Claim 21 is allowed.
The following is an examiner’s statement of reasons for allowance: The prior art of record alone, or in combination, fails to teach or render obvious, “A display panel, comprising: N types of display areas and M display parts, wherein N is an integer greater than or equal to two, and M is an integer greater than or equal to two; wherein the N types of display areas comprise an i-th type display area and a j-th type display area, and a light-emitting time period of sub-pixels in the i-th type display area and a light-emitting time period of sub-pixels in the j-th type display area at least partially do not overlap, wherein each of i and j is an integer greater than zero and less than or equal to N, and i is not equal to j; wherein the M display parts comprise a first display part and a second display part, the first display part comprises at least one i-th type display area and at least one j-th type display area, and the second display part comprises at least one i-th type display area and at least one j-th type display area; in a third time period, pixel driving circuits connected to sub-pixels in the i-th type display area and the j-th type display area in the first display part receive data signals; in a first time period, sub-pixels in the i-th type display area in the first display part and sub-pixels in the i-th type display area in the second display part emit light; and in a second time period, sub-pixels in the j-th type display area in the first display part and sub-pixels in the j-th type display area in the second display part emit light; wherein in at least one of the first time period and the second time period, the data signals received by the pixel driving circuits connected to the sub-pixels in the i-th type display area and the j-th type display area in the first display part are data signals of a current frame, and the data signals received by the pixel driving circuits connected to the sub-pixels in the i-th type display area and the j-th type display area in the second display part are data signals of a previous frame.” in combination with the other claimed limitations set forth in claim 21.
5. Claims 7 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
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/AMEN W BOGALE/ Examiner, Art Unit 2628
/NITIN PATEL/ Supervisory Patent Examiner, Art Unit 2628