CTNF 18/609,004 CTNF 81310 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement filed on 03/19/2024 & 07/30/2025 has been considered and placed in the application file. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 8, 11-13, 15, 18 and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Pertijs (U.S. 7,834,685) . Regarding claims 1 and 15, Pertijs (hereinafter, Ref~685 ) discloses (please see e.g., Figs. 1-12 and related text for details) an electronic device/method (e.g., system of Fig. 9 or Fig. 10) comprising: a controller (906 of Fig. 9 and/or 1002 of Fig. 10); a plurality of transconductance amplifiers (e.g., amplifiers 102/104 of Fig. 1) including a first transconductance amplifier (e.g., 102 of Fig. 1) and a second transconductance amplifier (104 of Fig. 1); and switching circuitry (110:136 of Fig. 1) including one or more first input switches (e.g., 110/112 of Fig. 1), one or more second input switches (114/116 of Fig. 1), one or more first output switches (e.g., 126/130/134 of Fig. 1), and one or more second output switches (128/132/136 of Fig. 1), wherein during a first period of time (at least during the duration from 1202 of Fig. 12): the one or more first input switches are configured by the controller to operate the first transconductance amplifier in a transconductance operation phase by coupling an input (input of 102 of Fig. 1) of the first transconductance amplifier to an input voltage (Vin of Fig. 1) via the one or more first input switches, and by coupling an output of the first transconductance amplifier to an output load (1112 of Fig. 11) via the one or more first output switches, and the one or more second input switches are configured by the controller to operate the second transconductance amplifier in one or more calibration phases (at least during the duration from 1204 of Fig. 12 and/or during the pre-charging phase shown/disclosed in Fig. 5) by decoupling an input of the second transconductance amplifier from the input voltage using the one or more second input switches and by decoupling an output of the second transconductance amplifier from the output load via the one or more second output switches, meeting claims 1 and 15 . Regarding claim 2, Ref~685 discloses the electronic device of claim 1, wherein during a second period of time (at least during the duration from 1206 of Fig. 12), different from the first period of time: the one or more first input switches are configured by the controller to operate the first transconductance amplifier in the one or more one or more calibration phases (at least during the duration from 1208 of Fig. 12) by decoupling the input of the first transconductance amplifier from the input voltage using the one or more first input switches and by decoupling the output of the first transconductance amplifier from the output load via the one or more first output switches, and the one or more second input switches are configured by the controller to operate the second transconductance amplifier in the transconductance operation phase by coupling the input of the second transconductance amplifier to the input voltage via the one or more second input switches, and by coupling the output of the second transconductance amplifier to the output load via the one or more second output switches as described throughout the disclosure, meeting claim 2 . Regarding claim 3, Ref~685 discloses the electronic device of claim 1, further comprising an auto-zeroing amplifier (124 of Fig. 1), wherein during a first sub-period of the first period of time the one or more second input switches are configured by the controller to operate the second transconductance amplifier in an auto-zeroing sub-phase of the one or more calibration phases by shorting (via switches 116 of Fig. 1) a first terminal (e.g., inverting terminal of 104 of Fig. 1) of the input of second transconductance amplifier to a second terminal (non-inverting terminal of 104 of Fig. 1) of the input of the second transconductance amplifier and by storing a correction current using compensation capacitors (120 of Fig. 1) associated with the auto-zeroing amplifier, meeting claim 3 . Regarding claim 8, Ref~685 supports the broadly claimed “wherein the one or more calibration phases during the first time period includes an auto-zeroing subphase followed by a gain correction subphase” due to the pre-charge feature provided by amplifier 506 and/or amplifier 508 of Fig. 5 that occurred between the auto-zeroing phase and the amplification phase as described in col. 6, between lines 20-40, meeting claim 8 . Regarding claim 11 , Ref~685 supports the broadly claimed “wherein during the first period of time the switching circuitry is configured in a first configuration and a second configuration and during a second period of time the switching circuitry is configured in a third configuration and a fourth configuration” as shown in Fig. 2 and/or Fig. 6, meeting claim 11 . Regarding claim 12, Ref~685 supports the claimed “wherein the first configuration for the switching circuitry corresponds to the transconductance operation phase for the first transconductance amplifier and an auto-zeroing sub-phase of the one or more calibration phases for the second transconductance amplifier, and the second configuration for the switching circuitry corresponds to the transconductance operation phase for the first transconductance amplifier and a gain correction sub-phase of the one or more calibration phases for the second transconductance amplifier” due to the ping-pong structure/configuration (see col. 3 for details) having various/alternate operations/configurations provided by switching networks shown in Figs. 2, 6 and/or 12, meeting claim 12 . Regarding claim 13, Ref~685 supports the claimed “wherein the third configuration for the switching circuitry corresponds to the transconductance operation phase for the second transconductance amplifier and the auto-zeroing sub-phase of the one or more calibration phases for the first transconductance amplifier, and the fourth configuration for the switching circuitry corresponds to the transconductance operation phase for the second transconductance amplifier and the gain correction sub-phase of the one or more calibration phases for the first transconductance amplifier” as shown in Figs. 2, 6 and/or 12, meeting claim 13 . Regarding claim 18, Ref~685 supports the claimed “wherein the gain correction subphase includes using circuitry (506 and/or 508 of Fig. 5) included in the electronic device to change a gain of the second transconductance amplifier until one or more criteria are satisfied”, since the buffer amplifiers 506-508 can charge the input capacitors 502-504 to target/specific level, namely Vin approximately as described in col. 6, between lines 20-40, meeting claim 18 . Regarding claim 20, Ref~685 further discloses the method of claim 15, further comprising: during the first period of time, concurrently calibrating a third transconductance amplifier (704b of Fig. 7 received the same clock signal that provided to 704a of Fig. 7) while measuring the transconductance using the first amplifier, wherein the calibrating includes the auto-zero subphase and the gain correction subphase, meeting claim 20 . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4-7, 9-10, 14, 16-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YOUNGHUIE HAN (Jessica) can be reached on 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /HIEU P NGUYEN/Primary Examiner, Art Unit 2843 Application/Control Number: 18/609,004 Page 2 Art Unit: 2843 Application/Control Number: 18/609,004 Page 3 Art Unit: 2843 Application/Control Number: 18/609,004 Page 4 Art Unit: 2843 Application/Control Number: 18/609,004 Page 5 Art Unit: 2843 Application/Control Number: 18/609,004 Page 6 Art Unit: 2843 Application/Control Number: 18/609,004 Page 7 Art Unit: 2843
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