DETAILED ACTION
This office action is in response to the application filed on 03/19/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/19/2024 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 11, 14 and 19-20 are objected to because of the following informalities: Claim 11 last line “of the synchronous boost converter.” this should be “of the synchronous boost converter and generating the at least one pulse”. Claim 14 line 3 “of a current flowing” this should be “of the current flowing”. Claim 19 last lines “based on the current flowing” this should be “based on a current flowing”. Claim 20 last lines “with an output voltage” this should be “with the output voltage”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites “generating of the at least one pulse” and at line 11-12 “generating, by a digital switching block of the feedback-based pulse generator, a switching control signal to control the second switch”. Claim 7 recites “generating, by a feedback-based pulse generator of the feedback based ZCD circuit, at least one pulse for constantly controlling the second switch”. It is not clear if the switching control signal and the one pulse are the same signal or different signals. For purposes of examination the limitations are going to be interpreted as the same signal.
Claim 10 is also rejected to under 35 U.S.C. 112(b), for being dependent on a rejected claim under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vaidya US 2017/0187283 in view of Erisman US 6879136.
Regarding Claim 1, Vaidya teaches (Figures 1 and 3-5) a feedback based zero current detection (ZCD) circuit (106 and at 104) in a synchronous boost converter (boost configuration, par. 14), the feedback based ZCD circuit comprising: a feedback-based pulse generator (306, Fig. 3) configured to: a bypass switch (120) connected in parallel to an inductor (L) included in the synchronous boost converter, and generate at least one control voltage signal based on the detected magnitude of the current (from 106, see fig. 3); and generate a clock switch signal (105b) to control a switch (114b) included in the synchronous boost converter at each switching cycle until the current flowing through the bypass switch reaches zero (Fig. 4, 406), based on the at least one control voltage signal (from 106), and turn on or turn off the switch (114b) connected between the inductor and an output terminal of the synchronous boost converter (in a boost configuration, par. 14) in response to the clock switch signal (105b). (For example: Par. 18-21 and 34-42)
Vaidya does not teach a switched capacitor integrator configured to: detect a magnitude of a current flowing through a bypass switch connected in parallel to an inductor included in the synchronous boost converter, and generate at least one control voltage signal based on the detected magnitude of the current.
Erisman teaches (Figures 1-3) a switched capacitor integrator (16) configured to: detect a magnitude of a current flowing through a bypass switch (ZRS switch) connected in parallel to an inductor (L), and generate at least one control voltage signal (emulated inductor current signal) based on the detected magnitude of the current. (For example: Par. Col. 3)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Vaidya to include a switched capacitor integrator configured to: detect a magnitude of a current flowing through a bypass switch connected in parallel to an inductor, and generate at least one control voltage signal based on the detected magnitude of the current, as taught by Erisman to improve the quality of the sensed signal.
Regarding Claim 2, Vaidya teaches (Figures 1 and 3-5) a circuit.
Vaidya does not teach wherein the switched capacitor integrator is configured to detect the magnitude of the current flowing through the bypass switch by sampling a voltage drop across the bypass switch.
Erisman teaches (Figures 1-3) wherein the switched capacitor integrator (16) is configured to detect the magnitude of the current flowing through the bypass (ZRS switch) switch by sampling a voltage drop across the bypass switch (Vc see fig. 2). (For example: Par. Col. 3)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Vaidya to include wherein the switched capacitor integrator is configured to detect the magnitude of the current flowing through the bypass switch by sampling a voltage drop across the bypass switch, as taught by Erisman to improve the quality of the sensed signal.
Regarding Claim 3, Vaidya teaches (Figures 1 and 3-5) wherein the feedback-based pulse generator (106 and at 104) is configured to generate the clock switch signal (105b) based on the current flowing through the bypass switch being reached zero (Fig. 4, 406). (For example: Par. 18-21 and 34-42)
Regarding Claim 4, Vaidya teaches (Figures 1 and 3-5) wherein the clock switch signal is a second clock switch signal (105b), and wherein the feedback-based pulse generator (106 and at 104) is configured to generate the second clock switch signal based on a first clock switch signal from a pulse width modulation circuit included in the synchronous boost converter (par. 18-20 for PWM operation). (For example: Par. 18-21 and 34-42)
Regarding Claim 7, Vaidya teaches (Figures 1 and 3-5) an operation method (Fig. 5) of a synchronous boost converter (par. 14 for boost configuration) including an inductor (L), a bypass switch (120), first and second switches (114a-b), and a feedback based zero current detection (ZCD) circuit (106 and at 104), the operation method comprising: the bypass switch (120) connected in parallel to the inductor (L) and connected to a first end of each of the first and second switches (114a-b) through a first node (118); and generating, by a feedback-based pulse generator of the feedback based ZCD circuit (106 and at 104), at least one pulse (105b) for constantly controlling the second switch (114b) connected between the first node and an output terminal (at Vout) of the synchronous boost converter (boost configuration, par. 14) at each switching cycle until the current flowing through the bypass switch reaches zero in the first phase (fig. 4, at 406), based on receiving the at least one control voltage signal (from 306). (For example: Par. 18-21 and 34-42)
Vaidya does not teach detecting, in a first phase, by a switched capacitor integrator of the feedback based ZCD circuit, a magnitude of a current flowing through the bypass switch, generating, by the switched capacitor integrator, at least one control voltage signal based on the detected magnitude of the current;
Erisman teaches (Figures 1-3) detecting, in a first phase (on time of ZRS or On time of s2), by a switched capacitor integrator (16) of the feedback based ZCD circuit (16 and ZRS switch), a magnitude of a current flowing through the bypass switch (ZRS switch), generating, by the switched capacitor integrator, at least one control voltage signal (emulated inductor current signal) based on the detected magnitude of the current. (For example: Par. Col. 3)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Vaidya to include detecting, in a first phase, by a switched capacitor integrator of the feedback based ZCD circuit, a magnitude of a current flowing through the bypass switch, generating, by the switched capacitor integrator, at least one control voltage signal based on the detected magnitude of the current, as taught by Erisman to improve the quality of the sensed signal.
Regarding Claim 8, Vaidya teaches (Figures 1 and 3-5) the converter.
Vaidya does not teach wherein the detecting of the magnitude of the current flowing through the bypass switch includes sampling a voltage drop across the bypass switch in the first phase.
Erisman teaches (Figures 1-3) wherein the detecting of the magnitude of the current flowing through the bypass switch (ZRS switch) includes sampling a voltage drop across the bypass switch in the first phase (Vc, see fig. 2). (For example: Par. Col. 3)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Vaidya to include wherein the detecting of the magnitude of the current flowing through the bypass switch includes sampling a voltage drop across the bypass switch in the first phase, as taught by Erisman to improve the quality of the sensed signal.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vaidya US 2017/0187283 in view of AAPA (Applicant’s Admitted Prior Art).
Regarding Claim 13, Vaidya teaches (Figures 1 and 3-5) a synchronous boost converter (par. 14) comprising: a first switch (114a) connected to a first node (118) and configured to operate in response to a first clock switch signal (105a); a second switch (114b) connected between the first node and an output terminal (Vout) of the synchronous boost converter and configured to operate in response to a second clock switch signal (105b); an inductor (L); a bypass switch (120) connected in parallel to the inductor; a pulse width modulation (PWM) circuit (at 104) configured to generate the first clock switch signal based on a feedback voltage from an output voltage of the output terminal of the synchronous boost converter and a reference voltage (par. 18-20); and a feedback based zero current detection circuit (106 and at 104 for producing 105b) configured to generate the second clock switch signal (105b) based on a current flowing through the bypass switch being reached zero (see fig. 4 at 406). (For example: Par. 18-21 and 34-42)
Vaidya does not teach an inductor connected between the first node and an input voltage source; and a feedback based zero current detection circuit configured to generate the second clock switch signal based on the first clock switch signal.
AAPA teaches (Figure 3) an inductor (L) connected between the first node and an input voltage source (Vin); and a feedback based zero current detection circuit (ZCD circuit) configured to generate the second clock switch signal (clksw2) based on the first clock switch signal (clksw1). (For example: Par. 6)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Vaidya to include an inductor connected between the first node and an input voltage source; and a feedback based zero current detection circuit configured to generate the second clock switch signal based on the first clock switch signal, as taught by AAPA to provide the desired output level.
Claim(s) 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vaidya US 2017/0187283 in view of AAPA (Applicant’s Admitted Prior Art) and further in view of Erisman US 6879136.
Regarding Claim 14, Vaidya teaches (Figures 1 and 3-5) wherein the feedback based ZCD circuit (106 and at 104).
Vaidya does not teach a switched capacitor integrator configured to detect a magnitude of a current flowing through the bypass switch, and generate at least one control voltage signal based on the detected magnitude of the current; and a feedback-based pulse generator configured to generate the second clock switch signal based on the at least one control voltage signal and the first clock switch signal.
AAPA teaches (Figure 3) a feedback based zero current detection circuit (ZCD circuit) configured to generate the second clock switch signal (clksw2) based on the at least one control voltage signal (sent to nand gate) and the first clock switch signal (clksw1). (For example: Par. 6)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Vaidya to include a feedback based zero current detection circuit configured to generate the second clock switch signal based on the at least one control voltage signal and the first clock switch signal., as taught by AAPA to provide the desired output level.
Vaidya as modified does not teach a switched capacitor integrator configured to detect a magnitude of a current flowing through the bypass switch, and generate at least one control voltage signal based on the detected magnitude of the current.
Erisman teaches (Figures 1-3) a switched capacitor integrator (16) configured to detect a magnitude of a current flowing through the bypass switch (at ZRS switch), and generate at least one control voltage signal based on the detected magnitude of the current (emulated inductor current signal). (For example: Par. Col. 3)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Vaidya to include a switched capacitor integrator configured to detect a magnitude of a current flowing through the bypass switch, and generate at least one control voltage signal based on the detected magnitude of the current, as taught by Erisman to improve the quality of the sensed signal.
Regarding Claim 15, Vaidya teaches (Figures 1 and 3-5) the converter.
Vaidya as modified does not teach wherein the switched capacitor integrator is configured to detect the magnitude of the current by sampling a voltage drop across the bypass switch in a first phase.
Erisman teaches (Figures 1-3) wherein the switched capacitor integrator (16) is configured to detect the magnitude of the current by sampling a voltage drop across the bypass switch in a first phase (Vc, see fig. 2). (For example: Par. Col. 3)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Vaidya to include wherein the switched capacitor integrator is configured to detect the magnitude of the current by sampling a voltage drop across the bypass switch in a first phase, as taught by Erisman to improve the quality of the sensed signal.
Regarding Claim 16, Vaidya teaches (Figures 1 and 3-5) the converter.
Vaidya as modified does not teach in a discontinuous conduction mode (DCM) is configured to operate in the first phase, a second phase, and a third phase, wherein the inductor is configured to be charged based on the first switch being turned on in the second phase, and wherein the inductor is configured to be discharged based on the second switch being turned on in the third phase.
Erisman teaches (Figures 1-3) in a discontinuous conduction mode (see fig. 2) is configured to operate in the first phase (ZRS on), a second phase (S1 on), and a third phase (S2 on), wherein the inductor is configured to be charged based on the first switch being turned on in the second phase (Fig. 2), and wherein the inductor is configured to be discharged based on the second switch being turned on in the third phase (Fig. 2). (For example: Par. Col. 3)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Vaidya to include in a discontinuous conduction mode (DCM) is configured to operate in the first phase, a second phase, and a third phase, wherein the inductor is configured to be charged based on the first switch being turned on in the second phase, and wherein the inductor is configured to be discharged based on the second switch being turned on in the third phase, as taught by Erisman to improve the quality of the sensed signal.
Regarding Claim 17, Vaidya teaches (Figures 1 and 3-5) wherein the feedback-based pulse generator (106 and at 104) is configured to: generate the second clock switch signal (105b) being turned on based on the first clock switch (105a) signal being turned off (see fig. 4), and generate the second clock switch signal being turned off based on the current flowing through the bypass switch being reached zero (see fig. 4, at 406). (For example: Par. 18-21 and 34-42)
Allowable Subject Matter
Claim 5-6, 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 9-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claims 5 18; prior art of record fails to disclose either by itself or in combination: “…wherein the feedback-based pulse generator comprises: an analog adder configured to: add the at least one control voltage signal from the switched capacitor integrator and a modulated delay voltage signal from the PWM circuit, and generate an added output signal based on the at least one control voltage signal and the modulated delay voltage signal; a first comparator configured to: compare the added output signal from the analog adder with a ramp clock signal, and generate a comparison output signal based on a result of the comparison of the first comparator; and a digital switching block configured to: generate the second clock switch signal in response to the comparison output signal from the first comparator and the first clock switch signal, trigger the second switch to turn on based on a falling edge of the first clock switch signal, and trigger the second switch to turn off based on a current flowing through the inductor being reached zero.”
Claims 6, 19; prior art of record fails to disclose either by itself or in combination: “…wherein the feedback-based pulse generator comprises: a voltage controlled delay line (VCDL) configured to generate a control signal based on the at least one control voltage signal from the switched capacitor integrator and the first clock switch signal; and a NAND gate configured to: generate a switching control signal to control the second switch based on the control signal from the VCDL and an inversion signal of the first clock switch signal, trigger the second switch to turn on, based on a falling edge of the first clock switch signal, and trigger the second switch to turn off based on the current flowing through the inductor being reached zero.”
Claims 6, 19; prior art of record fails to disclose either by itself or in combination: “…wherein the generating of the at least one pulse includes: generating, by a voltage controlled delay line (VCDL) of the feedback-based pulse generator, a control signal based on the at least one control voltage signal from the switched capacitor integrator and a first clock switch signal from a pulse width modulation (PWM) circuit; generating, by a NAND gate of the feedback-based pulse generator, a switching control signal to control the second switch, based on receiving the control signal from the VCDL and a clock bar signal of inversion of the first clock switch signal; and converting, by a level shifter of the feedback-based pulse generator, a lower magnitude of the switching control signal to a higher magnitude to match with an output voltage of the output terminal of the synchronous boost converter”.
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Conclusion
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838