DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 9 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 7th, 2026. Therefore, the restriction requirement submitted on May 7th, 2026, is made FINAL.
Status of Claims
Following Applicant’s reply to restriction requirement filed on July 7th, 2026, Claims 1-8 and 10-20 are pending examination, with Claim 9 being withdrawn from further consideration as being drawn to a non-elected species.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
The information disclosure statement (IDS) filed on March 19th, 2024, is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The abstract is objected to for failing to for failing to be in narrative form. Applicant is reminded of the proper language and format for an abstract of the disclosure: The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. See MPEP § 608.01(b).
The specification is objected to as the section headings are in bold type. Pursuant to MPEP
608.01(a) and 37 C.F.R. 1.77(c), “The text of the specification sections defined in paragraphs (b)(1)
through (b)(12) of this section, if applicable, should be preceded by a section heading in uppercase and
without underlining or bold type” (emphasis added). The instant application has section headings with
bold type. Appropriate correction is required.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
a) 134_R – Fig. 8 is not mentioned in the specification. More specifically, in [0057] it is meant to read 134_R but the reference character 132_R is repeated instead.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 10-13, 17-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over More, et al. (US 20230058459 A1; hereinafter referred to as More) and further in view of Kumar, Raj, et al. (“Impact of dose and energy of argon (40Ar+) and fluorine (19F+) ion implantation on uniformity of silicon oxidation”, Vacuum 81, 2006, 260-264; hereinafter referred to as Kumar).
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Regarding Claim 1, More discloses an integrated circuit device (integrated circuit, [0002], Fig. 19) comprising:
a fin-type active region (fin-type active region, see Annotated Fig. 19) that protrudes from a substrate (substrate 201, [0018], Fig. 19) and extends in a first horizontal direction (Fig. 19);
a plurality of semiconductor patterns on the fin-type active region and separated from each other in a vertical direction (channel members 2080, [0040], Fig. 19);
a gate line on the fin-type active region (gate structure 260, [0041], Fig. 19), the gate line surrounding the plurality of semiconductor patterns and extending in a second horizontal direction that intersects the first horizontal direction (Fig. 19);
a source/drain region on the fin-type active region (source/drain features 244, [0033], Fig. 19), adjacent to the gate line and connected to the plurality of semiconductor patterns (Fig. 19), wherein the source/drain region includes a first semiconductor layer that contacts the plurality of semiconductor patterns (first epitaxial layer 238, [0034], Fig. 19), and wherein the first semiconductor layer includes a semiconductor material ([0034]), and
an inner spacer between the source/drain region and the gate line (inner spacer features 236, [0029], Fig. 19), the inner spacer including an oxide including the first element or a nitride including the first element ([0030], “inner spacer material may include . . . silicon oxynitride”).
More fails to explicitly disclose that the semiconductor material for the first semiconductor layer includes a first element that includes at least one selected from the group consisting of fluorine, oxygen, argon, and nitrogen, as More only discloses that the first semiconductor [epitaxial] layer includes a semiconductor material (e.g., germanium) with tin, while also having doping concentrations of phosphorus, arsenic, or boron to ensure the first semiconductor [epitaxial] layer coupled to the semiconductor patterns [channel layers] are without substantial lattice mismatch ([0034]).
However, in analogous art, Kumar discloses the use of doping a semiconductor material (e.g., silicon) with argon and fluorine in semiconductor devices as the dopant ([Introduction]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the integrated circuit of More such that the first semiconductor layer was doped and/or comprised of argon/fluorine as disclosed by Kumar. One would be motivated to do so because using argon and fluorine as the dopant/first element for the first semiconductor layer leads to improved and more uniform oxidation rates of the first semiconductor layer (Kumar: [Abstract]) which can lead to more efficient manufacturing in the semiconductor device.
Regarding Claim 10, More/Kumar discloses the integrated circuit device of claim 1, wherein the first semiconductor layer includes: an outer sidewall that is in contact with the inner spacer (More: see Annotated Fig. 19); and an inner sidewall that is opposite to the outer sidewall (More: see Annotated Fig. 19), and
wherein the source/drain region further includes a second semiconductor layer on the inner sidewall of the first semiconductor layer (More: second epitaxial layer 240, [0033], Fig. 19).
Regarding Claim 11, More/Kumar discloses the integrated circuit device of claim 1, wherein the first semiconductor layer includes fluorine-doped Si, fluorine-doped SiGe, fluorine-doped SiP, fluorine-doped SiGeB, oxygen-doped Si, oxygen-doped SiGe, oxygen-doped SiP, oxygen-doped SiGeB, argon-doped Si, argon-doped SiGe, argon-doped SiP, argon-doped SiGeB, nitrogen-doped Si, nitrogen-doped SiGe, nitrogen-doped SiP, or nitrogen-doped SiGeB, or a combination of two or more thereof (More: [0030], Kumar: [Abstract]; More discloses that the first semiconductor layer is a semiconductor material (e.g., Si, SiGe) that is doped by an n-type or p-type dopant, and Kumar discloses that argon and fluorine may be used as said dopant material).
Regarding Claim 12, More/Kumar discloses the integrated circuit device of claim 1, wherein the inner spacer includes an oxide of at least one semiconductor material selected from the group consisting of fluorine-doped Si, fluorine-doped SiGe, fluorine-doped SiP, fluorine-doped SiGeB, oxygen-doped Si, oxygen-doped SiGe, oxygen-doped SiP, oxygen-doped SiGeB, argon-doped Si, argon-doped SiGe, argon-doped SiP, and argon-doped SiGeB, or a nitride of at least one semiconductor material selected from the group consisting of nitrogen-doped Si, nitrogen-doped SiGe, nitrogen-doped SiP, and nitrogen-doped SiGeB (More: [0030]; as is stated above, More discloses the spacers are formed of a doped semiconductor material and Kumar discloses that said dopant can be fluorine and argon and, therefore, argon-doped Si and fluorine-doped Si is taught by the combination of More/Kumar).
Regarding Claim 13, More discloses an integrated circuit device comprising:
a fin-type active region (fin-type active region, see Annotated Fig. 19) that protrudes from a substrate (substrate 201, [0018], Fig. 19) and extends in a first horizontal direction (Fig. 19);
a plurality of semiconductor patterns on the fin-type active region and overlapping with each other in a vertical direction (channel members 2080, [0040], Fig. 19);
a gate line on the fin-type active region (gate structure 260, [0041], Fig. 19), the gate line surrounding the plurality of semiconductor patterns and extending in a second horizontal direction that intersects the first horizontal direction (Fig. 19);
a source/drain region on the fin-type active region (source/drain features 244, [0033], Fig. 19), adjacent to the gate line and connected to the plurality of semiconductor patterns (Fig. 19); and
an inner spacer between the source/drain region and the gate line (inner spacer features 236, [0029], Fig. 19),
wherein the source/drain region includes:
a first semiconductor layer having an outer sidewall and an inner sidewall (first epitaxial layer 238, [0034], Fig. 19), the outer sidewall in contact with the plurality of semiconductor patterns and the inner spacer (see Annotated Fig. 19), and the inner sidewall opposite to the outer sidewall (see Annotated Fig. 19); and
a second semiconductor layer on the inner sidewall of the first semiconductor layer (second epitaxial layer 240, [0033], Fig. 19),
wherein the inner spacer includes an oxide including the first element or a nitride including the first element ([0030]).
More fails to explicitly disclose that the semiconductor material for the first semiconductor layer includes a first element that includes at least one selected from the group consisting of fluorine, oxygen, argon, and nitrogen, as More only discloses that the first semiconductor [epitaxial] layer includes a semiconductor material (e.g., germanium) with tin, while also having doping concentrations of phosphorus, arsenic, or boron to ensure the first semiconductor [epitaxial] layer coupled to the semiconductor patterns [channel layers] are without substantial lattice mismatch ([0034]).
However, in analogous art, Kumar discloses the use of doping a semiconductor material (e.g., silicon) with argon and fluorine in semiconductor devices as the dopant ([Introduction]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the integrated circuit of More such that the first semiconductor layer was doped and/or comprised of argon/fluorine as disclosed by Kumar. One would be motivated to do so because using argon and fluorine as the dopant/first element for the first semiconductor layer leads to improved and more uniform oxidation rates of the first semiconductor layer (Kumar: [Abstract]) which can lead to more efficient manufacturing in the semiconductor device.
Regarding Claim 17, More discloses an integrated circuit device comprising:
a fin-type active region (fin-type active region, see Annotated Fig. 19) that protrudes from a substrate (substrate 201, [0018], Fig. 19) and extends in a first horizontal direction (Fig. 19);
a plurality of semiconductor patterns on the fin-type active region and separated from each other in a vertical direction (channel members 2080, [0040], Fig. 19);
a gate line on the fin-type active region (gate structure 260, [0041], Fig. 19), the gate line surrounding the plurality of semiconductor patterns and extending in a second horizontal direction that intersects the first horizontal direction (Fig. 19);
a source/drain region on the fin-type active region (source/drain features 244, [0033], Fig. 19), adjacent to the gate line and connected to the plurality of semiconductor patterns (Fig. 19);
an inner spacer between the source/drain region and the gate line (inner spacer features 236, [0029], Fig. 19); and
a gate insulating layer between the gate line and the plurality of semiconductor patterns and between the gate line and the inner spacer (gate dielectric layer 254, [0041], Fig. 17),
wherein the source/drain region includes:
a buffer layer having an outer sidewall and an inner sidewall (first epitaxial layer 238, [0034], Fig. 19), the outer sidewall in contact with the plurality of semiconductor patterns and the inner spacer (see Annotated Fig. 19), and the inner sidewall opposite from the outer sidewall (see Annotated Fig. 19); and
a main semiconductor layer on the inner sidewall of the buffer layer (second epitaxial layer 240, [0033], Fig. 19),
wherein the outer sidewall of the buffer layer includes a plurality of grooves (grooves, see Annotated Fig. 17), the plurality of grooves separated from each other in the vertical direction at locations corresponding to the inner spacer (second height H2, [0031], Fig. 16).
More fails to explicitly disclose that the semiconductor material for the buffer layer includes a first element that includes at least one selected from the group consisting of fluorine, oxygen, argon, and nitrogen, as More only discloses that the buffer [first epitaxial] layer includes a semiconductor material (e.g., germanium) with tin, while also having doping concentrations of phosphorus, arsenic, or boron to ensure the buffer [first epitaxial] layer coupled to the semiconductor patterns [channel layers] are without substantial lattice mismatch ([0034]).
However, in analogous art, Kumar discloses the use of doping a semiconductor material (e.g., silicon) with argon and fluorine in semiconductor devices as the dopant ([Introduction]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the integrated circuit of More such that the buffer layer was doped and/or comprised of argon/fluorine as disclosed by Kumar. One would be motivated to do so because using argon and fluorine as the dopant/first element for the buffer layer leads to improved and more uniform oxidation rates of the first semiconductor layer (Kumar: [Abstract]) which can lead to more efficient manufacturing in the semiconductor device.
Regarding Claim 18, More/Kumar discloses the integrated circuit device of claim 17, wherein the inner spacer includes an oxide including the first element or a nitride including the first element (More: [0030]).
Regarding Claim 20, More/Kumar discloses the integrated circuit device of claim 17, wherein the inner spacer includes:
a first sidewall that faces the source/drain region (More: see Annotated Fig. 17); and
a second sidewall that faces the gate line and is opposite to the first sidewall (More: see Annotated Fig. 17).
wherein the first sidewall of the inner spacer has a convex profile in contact with the plurality of grooves (More: see Annotated Fig. 17).
Claim(s) 2-4, 6-8, 14-16, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over More/Kumar as applied to claims 1, 10-13, 17-18, and 20 above, and further in view of Chen, et al. (US 20230035791 A1; hereinafter referred to as Chen).
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Regarding Claim 2, More/Kumar discloses the integrated circuit device of claim 1, wherein the inner spacer includes:
a first sidewall that faces the source/drain region (More: see Annotated Fig. 17); and
a second sidewall that faces the gate line and is opposite to the first sidewall (More: see Annotated Fig. 17).
The combination of More/Kumar fails to disclose wherein the first sidewall of the inner spacer protrudes from a sidewall of the plurality of semiconductor patterns toward the source/drain region and has a convex profile.
However, in analogous art, Chen discloses an inner spacer wherein the first sidewall of the inner spacer (inner spacer 126b, [0035], Fig. 4D) protrudes from a sidewall of the plurality of semiconductor patterns toward the source/drain region and has a convex profile (Fig. 4D).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the inner spacers of More/Kumar such that the first sidewall of the inner spacer protrudes from a sidewall of the plurality of semiconductor patterns and has a convex profile as disclose by Chen. One would be motivated to do so because a thicker inner spacer may improve parasitic capacitance and reduce leakage current between subsequently formed source/drain epitaxial structures and the gate structures (Chen: [0041]).
Regarding Claim 3, More/Kumar/Chen discloses the integrated circuit device of claim 2, wherein the first semiconductor layer includes a plurality of grooves (More: grooves, see Annotated Fig. 17), and wherein each of the plurality of grooves is in contact with the first sidewall of the inner spacer (More: see Annotated Fig. 17).
Regarding Claim 4, More/Kumar/Chen discloses the integrated circuit device of claim 3, wherein the plurality of grooves are separated from each other in the vertical direction at locations corresponding to the inner spacer (More: second height H2, [0031], Fig. 16), and the first semiconductor layer includes a first portion and a second portion, the first portion at a same vertical level as at least a portion of the plurality of semiconductor patterns, and the second portion at a same vertical level as at least a portion of the inner spacer (More: see annotated Fig. 17), and
wherein the first portion of the first semiconductor layer has a first width in the first horizontal direction (More: see Annotated Fig. 17), and the second portion of the first semiconductor layer has a second width that is less than the first width in the first horizontal direction (Chen: Fig. 4D; due to the inner spacer 126b of Chen overlapping with the source/drain, with that feature being taught, in combination with More, the second width would be less than the first width).
Regarding Claim 6, More/Kumar/Chen discloses the integrated circuit device of claim 2, wherein the gate line includes a main gate portion and a sub gate portion (More: see Annotated Fig. 19), the main gate portion on a topmost semiconductor pattern among the plurality of semiconductor patterns (More: see Annotated Fig. 19), and the sub gate portion between two adjacent semiconductor patterns among the plurality of semiconductor patterns (More: see Annotated Fig. 19),
wherein the inner spacer is between the sub gate portion and the first semiconductor layer (More: [0030], see Annotated Fig. 19).
Regarding Claim 7, More/Kumar/Chen discloses the integrated circuit device of claim 6, wherein the second sidewall of the inner spacer protrudes from the sidewall of the plurality of semiconductor patterns toward the gate line and has a convex profile (Chen: Fig. 4D).
Regarding Claim 8, More/Kumar/Chen discloses the integrated circuit device of claim 6, wherein a sidewall of the sub gate portion has a concave profile corresponding to a shape of the second sidewall of the inner spacer (More: Figs. 17-18).
Regarding Claim 14, More/Kumar discloses the integrated circuit device of claim 13, wherein the inner spacer includes:
a first sidewall that faces the source/drain region (More: see Annotated Fig. 17); and
a second sidewall that faces the gate line and is opposite to the first sidewall (More: see Annotated Fig. 17).
The combination of More/Kumar fails to disclose wherein the first sidewall of the inner spacer protrudes from a sidewall of the plurality of semiconductor patterns toward the source/drain region and has a convex profile.
However, in analogous art, Chen discloses an inner spacer wherein the first sidewall of the inner spacer (inner spacer 126b, [0035], Fig. 4D) protrudes from a sidewall of the plurality of semiconductor patterns toward the source/drain region and has a convex profile (Fig. 4D).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the inner spacers of More/Kumar such that the first sidewall of the inner spacer protrudes from a sidewall of the plurality of semiconductor patterns and has a convex profile as disclose by Chen. One would be motivated to do so because a thicker inner spacer may improve parasitic capacitance and reduce leakage current between subsequently formed source/drain epitaxial structures and the gate structures (Chen: [0041]).
Regarding Claim 15, More/Kumar/Chen discloses the integrated circuit device of claim 14, wherein the first semiconductor layer includes a plurality of grooves (More: grooves, see Annotated Fig. 17), the plurality of grooves being separated from each other in the vertical direction at a location corresponding to the inner spacer (More: second height H2, [0031], Fig. 16),
wherein a portion of the inner spacer vertically overlaps the first semiconductor layer (Chen: Fig. 4D; the inner spacer 126b, while also horizontally overlapping, will vertically overlap with the first semiconductor layer), and
wherein another portion of the inner spacer vertically overlaps the plurality of semiconductor patterns (Chen: Fig. 4D; the inner spacer 126a vertically overlaps with portions of the semiconductor patterns).
Regarding Claim 16, More/Kumar discloses the integrated circuit device of claim 13, wherein the first semiconductor layer includes a first portion and a second portion (More: see annotated Fig. 17), the first portion at a same vertical level as at least a portion of the plurality of semiconductor patterns, and the second portion at a same vertical level as at least a portion of the inner spacer (More: see annotated Fig. 17),
wherein the first portion of the first semiconductor layer has a first width in the first horizontal direction (More: see annotated Fig. 17), and
More/Kumar fails to disclose the second portion of the first semiconductor layer has a second width that is less than the first width in the first horizontal direction.
However, in analogous art, Chen discloses wherein the second portion of the first semiconductor layer has a second width that is less than the first width in the first horizontal direction (Chen: Fig 4D; since the inner spacer 126b extends into the source/drain region, it would be obvious that the second width would be less than the first width because the inner spacer extends beyond the semiconductor pattern).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first semiconductor layer of More/Kumar such that there is a second portion which has a second width that is less than the first width in the first horizontal direction as disclosed by Chen. One would be motivated to do so because by having the inner spacers extend beyond the semiconductor patterns, and therefore by extension having a lesser width than the first width, you can improve parasitic capacitance and reduce leakage current between the active layers of the device (Chen: [0041]).
Regarding Claim 19, More/Kumar discloses the integrated circuit device of claim 17.
The combination of More/Kumar fails to explicitly disclose that a first distance between the main semiconductor layer and a sidewall of the plurality of semiconductor patterns in the first horizontal direction is greater than a second distance between the main semiconductor layer and the inner spacer in the first horizontal direction.
However, in analogous art, Chen discloses wherein a first distance between the main semiconductor layer and a sidewall of the plurality of semiconductor patterns in the first horizontal direction is greater than a second distance between the main semiconductor layer and the inner spacer in the first horizontal direction (Chen: Fig. 4D; since the inner spacer extends into the main semiconductor layer (source/drain region) and beyond the semiconductor patterns in a horizontal direction, the distance between the inner spacer and the main semiconductor layer would be less than the distance between the main semiconductor layer and the sidewall of the plurality of semiconductor patterns).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the distances between the main semiconductor layer and the inner spacer as disclosed by More/Kumar such that said distance is less than the distance between the main semiconductor layer and the sidewalls of the plurality of semiconductor patterns as taught in Chen. One would be motivated to do so because this would imply that the inner spacers extend beyond the semiconductor patterns and into the source/drain region which can improve parasitic capacitance and reduce leakage current between the gate structures and the source/drain (Chen: [0041]).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over More/Kumar/Chen as applied to claims 1-4, 6-8, and 10-20 above, and further in view of Chang, et al. (US 2024/0055485 A1; hereinafter referred to as Chang).
Regarding Claim 5, More/Kumar/Chen discloses the integrated circuit device of claim 4.
The combination of More/Kumar/Chen does not explicitly disclose that the first width of the first semiconductor layer is greater than or equal to 0.5 nanometers (nm).
However, in analogous art, Chang discloses wherein the first width of the first semiconductor layer (Chang: second epitaxial layer 146b, Fig. 12; said second epitaxial layer 146b is analogous to the first semiconductor layer of the instant application as both are doped semiconductor layers, Chang: [0037], in contact with the spacers and conductor pattern) is greater than or equal to 0.5 nanometers (nm) (Chang: [0037], “The second epitaxial layer 146b may have a thickness in a range between about 0.1 nm and about 1 nm”; the thickness of the second epitaxial layer is equivalent to the first width of the instant application as both are measurements of the distance from the semiconductor patterns to interface between the second epitaxial layer/buffer layer and the third epitaxial layer/main semiconductor layer).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first semiconductor layer of the combination of More/Kumar/Chen such that it has a width greater than or equal to 0.5 nanometers as disclosed by Chang. One would be motivated to do so to ensure the first semiconductor layer is thick enough to function as a leakage barrier between the active channel layers and the main semiconductor layer (Chang: [0037]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a) Song, et al. (US 20200395482 A1); discloses an integrated circuit structure wherein the source/drain feature includes a buffer layer.
b) Cheng, et al. (US 20230052084 A1); discloses an integrated circuit structure wherein the source/drain feature includes a buffer layer and grooves.
c) Wu, et al. (US 20230010657 A1); discloses an integrated circuit structure with inner spacers protruding from the semiconductor patterns/channel layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/Noah C. Robertson/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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