DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-6, 8-9, 13-14, 16-18, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 4377000 (“Staab”) in view of US Patent Application Publication No. 20170269984 (“Idapalapati”) and US Patent Application Publication No. 20070168716 (“Donlin”).
Regarding claim 1, Staab teaches
A method for system fault handling, comprising: (Col. 8, Lines 45-55: system fault recovery)
receiving, from a CPU sub-system (CPUSS) of a system…, by a central processing unit (CPU) control processor (CPUCP) of the [system]…, a fault alert associated with…a first processor…of the [system], wherein the [system] comprises the first processor…and a second processor…; (Fig. 1, Col. 4, Lines 35-60, Col. 8, Lines 45-55: a system bootstrap controller (SBC), which controls CPUs, receives a deadman signal from a CPU of a system comprising multiple CPUs)
without resetting the [system], initiating, by the CPUCP, based on the fault alert, a fault handling process comprising: (Fig. 2, Col. 8, Lines 45-65: in response to the deadman signal, the SBC indicates a fault recovery process without resetting the system)
halting…the first processor…and the second processor… prior to performing a reset operation for at least a portion of the first processor…; (Fig. 2, Col. 8, Lines 45-65: halt the CPUs prior to reset)
performing the reset operation for at least a portion of the first processor…; and (Fig. 2, Col. 8, Lines 45-65: reset the CPUs)
resuming the processors that were halted in the first processor…and the second processor… after the performing of the reset operation for at least the portion of the first processor cluster and (Fig. 2, Col. 8, Lines 45-65: resume the CPUs after reset)
after performing the fault handling process, performing one or more actions using…the first processor…(Fig. 2, Col. 8, Lines 45-65: after resuming from reset, the CPUs execute)
Staab does not teach a system-on-chip, a CPUCP that performs power management, or a first processor cluster and a second processor cluster.
Idapalapati teaches
a system on chip (SoC) (Fig. 1, [0033]: SoC)
a central processing unit (CPU) control processor (CPUCP) of the SoC that performs power management for the SoC (Fig. 1, [0036], [0037]: the reset controller for the SoC contains a power manager)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine Idapalapati’s recovery architecture with Staab’s recovery.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination because Idapalapati’s architecture can be applied to any computing device to allow for quicker detection and recovery of a hung CPU while preventing a system reset (Idapalapati, [0022], [0024]).
Staab in view of Idapalapati does not teach a first processor cluster and a second processor cluster.
Donlin teaches
a first processor cluster and a second processor cluster ([0026]: clusters of CPUs)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine Donlin’s architecture with Staab in view of Idapalapati’s architecture.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination to improve performance while maintaining reliability (Donlin, [0004], [0008]).
Regarding claim 2, Staab in view of Idapalapati and Donlin further teaches
wherein a fault indicated in the fault alert comprises a processor hang event and (Idapalapati, [0038]: hung CPU)
wherein the fault handling process further comprises masking interrupts for the first processor cluster (Donlin, [0038]: failsoft process 240 (FIG. 9). the conventional cpu-set control structure is modified 246 to remove the failed cpu (disabling interrupts, etc.) and the conventional private data area control structure for the failed cpu is modified 248 to disable interrupts and scheduling for the failed cpu.)
Regarding claim 4, Staab in view of Idapalapati and Donlin further teaches
wherein the fault handling process further comprises performing a cache clean for the processor in the first processor cluster. (Donlin, [0032]: a check against a transient error threshold for the cache line is performed 106. If the limit has been exceeded, the limit flag is set 108. The system then invalidates the data of the cache line)
Regarding claim 5, Staab in view of Idapalapati and Donlin further teaches
wherein the fault handling process does not comprise resetting a central processing unit control processor (CPUCP) of the SoC. (Staab, [0038]: the controller is not reset).
Regarding claim 6, Staab in view of Idapalapati and Donlin further teaches
wherein the fault handling process further comprises collecting a scan dump. (Idapalapati [0056], [0057]: collecting diagnosis information)
Regarding claim 8, Staab in view of Idapalapati and Donlin further teaches
wherein the fault handling process further comprises migrating run queue tasks and interrupts away from the first processor cluster. (Donlin, [0038]: The run queue tasks and clock interrupt processing for the failed cpu are redirected)
Regarding claim 9, Staab in view of Idapalapati and Donlin further teaches
wherein the fault handling process further comprises marking one or more cores of the first processor cluster as offline. (Donlin, [0033]: When the cpu is part of a set, the failsoft status flags for disabling this cpu and idling this cpu are set)
Claim(s) 13-14, 16-18, the system(s) that implement(s) the method(s) of claim(s) 1-2, 4-6, respectively, is/are rejected on the same grounds as claim(s) 1-2, 4-6, respectively.
Staab in view of Idapalapati and Donlin further teaches
A processing system comprising: one or more memories comprising processor-executable instructions; and one or more processors configured to execute the processor-executable instructions and cause the processing system to: (Idapalapati, [0089]: memory storing instructions for execution by a processor to implement the methods)
Claim(s) 20, the apparatus(s) that implement(s) the method(s) of claim(s) 1, respectively, is/are rejected on the same grounds as claim(s) 1, respectively.
Staab in view of Idapalapati and Donlin further teaches
An apparatus, comprising: means for (Idapalapati, [0089]: memory storing instructions for execution by a processor to implement the methods)
Claim(s) 3, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 20210232451 (“Staab”) in view of US Patent Application Publication No. 20170269984 (“Idapalapati”), US Patent Application Publication No. 20070168716 (“Donlin”), and US Patent Application Publication No. 20040199813 (“Hillman”).
Regarding claim 3, Staab in view of Idapalapati and Donlin does not further teach the remaining limitations.
Hillman teaches
wherein the reset operation comprises resetting and clamping one or more processor cores in the first processor cluster. ([0074]: holding the processor in reset mode)
Holding the processor in reset mode corresponds to resetting and clamping.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine Staab in view of Idapalapati and Donlin’s fault handling with Hillman’s fault handling.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination to prevent resource contention with operating processors (Hillman, [0074]).
Claim(s) 15, the system(s) that implement(s) the method(s) of claim(s) 3, respectively, is/are rejected on the same grounds as claim(s) 3, respectively.
Claim(s) 7, 12, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 20210232451 (“Staab”) in view of US Patent Application Publication No. 20170269984 (“Idapalapati”), US Patent Application Publication No. 20070168716 (“Donlin”), and US Patent Application Publication No. 20180039552 (“Moskowiz”).
Regarding claim 7, Staab in view of Idapalapati and Donlin does not further teach the remaining limitations.
Moskowiz teaches
wherein the fault handling process further comprises resetting power control for the first processor cluster and not for the second processor cluster. (Fig. 1, 3, [0010]: [0020]: resetting a BMC in a first processor cluster but not a second processor cluster).
BMCs are a type of power management device and correspond to power control
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine Staab in view of Idapalapati and Donlin’s fault handling with Moskowiz’s fault handling.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination because the determination that a service processor is working properly indicates other components of the device, e.g., general purpose processors, are also working properly, which helps distribute fault management (Moskowiz, [0009], [0016]).
Regarding claim 12, Staab in view of Idapalapati, Donlin, and Moskowiz further teaches
wherein the fault comprises a firmware fault, and wherein the reset operation comprises executing a firmware reset in the first processor cluster. (Moskowiz, Fig. 1, 3, [0010], [0020]: resetting a faulty BMC).
In light of the specification, [0025], [0058], the broadest reasonable interpretation of a firmware fault encompasses a power and debug processor fault. BMCs are a type of power management device and correspond to power and debug processors.
Claim(s) 19, the system(s) that implement(s) the method(s) of claim(s) 7, respectively, is/are rejected on the same grounds as claim(s) 7, respectively.
Claim(s) 10, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 20210232451 (“Staab”) in view of US Patent Application Publication No. 20170269984 (“Idapalapati”), US Patent Application Publication No. 20070168716 (“Donlin”), and US Patent No. 4805107 (“Kieckhafer”).
Regarding claim 10, Staab in view of Idapalapati and Donlin does not further teach the remaining limitations.
Kieckhafer teaches
wherein the fault handling process further comprises notifying an operating system (OS) scheduler for the first processor cluster that the fault handling process is being performed. (Col. 33, Lines 15-25, Col. 34, Lines 10-20, Fig. 69, Col. 69, Lines 35-55: setting a flag to notify the OS scheduler that the processor is undergoing fault handling and unavailable for scheduling)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine Staab in view of Idapalapati and Donlin’s fault handling with Kieckhafer’s scheduler.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination to enable graceful degradation and restoration for workload scheduling in response to faulty nodes (Kieckhafer, Col. 10, Lines 10-25).
Regarding claim 11, Staab in view of Idapalapati, Donlin, and Kieckhafer further teaches
wherein the fault handling process further comprises notifying the OS scheduler for the first processor cluster that the reset operation is complete. (Kieckhafer Fig. 69, Col. 69, Lines 45-67: after the reset in the fault handling process, set a flag to indicate to the scheduler that the processor is ready for scheduling)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/A.L./Examiner, Art Unit 2113
/MARC DUNCAN/Primary Examiner, Art Unit 2113