DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on/after Mar. 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Allowable Subject Matter
Claims 7-9, 18-20, and 27-29 are objected to as being dependent upon a rejected base claim, but would be ALLOWABLE if rewritten in independent form including ALL of the limitations of the base claim AND any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claims 7, 18, and 27, the prior art of record does not teach, suggest, or disclose the claim limitation “determining … that the GPU is operating in a bin foveation mode” in combination with the claim limitation “storing … downsampled data in an LRZ region corresponding to the … pixel tiles among the … LRZ regions” and in combination with the other recited claim limitations both inherited directly from the independent claims and otherwise recited within the dependent claims. Dependent claims 8-9, 19-20, and 28-29 are similarly objected to due to their respective dependencies stemming from dependent claims 7, 18, and 27.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 USC 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 10-13, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Nordlund (U.S. PG-PUB 2012/0280998, 'NORDLUND') in view of Davies et al. (U.S. PG-PUB 2019/0295313, 'DAVIES') .
Regarding claim 1, NORDLUND discloses a graphics processing unit (GPU) (NORDLUND; FIG. 1 ‘graphics processing unit 6’; ¶ 0025) comprising:
([DAVIES discloses this limitation EXPLICITLY.]); and
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a sliced low-resolution Z buffer (LRZ) communicatively coupled to each hardware slice … and comprising … LRZ regions (NORDLUND; ¶ 0021-22; “… during the binning pass for an image surface, the GPU may update a low-resolution buffer, referred to as a low-resolution Z-buffer or "LRZ buffer." The low-resolution buffer may be a [2-D] buffer with … storage locations. Each storage location in the low-resolution buffer may correspond to a block of pixels [‘LRZ regions’] represented on the display. … the number of storage locations within the low-resolution buffer may be less than the number of pixels to be represented on the display. During the binning pass for an image surface, the GPU may determine whether that image surface includes surface pixels that correspond to a storage location within the low-resolution buffer. … the GPU may divide the image surface into … blocks of surface pixels. The size of the blocks of surface pixels may be similar to the size of the blocks of pixels on the display that correspond to one storage location in the low-resolution buffer.” FIG. 1, ‘low-resolution buffer’; ¶ 0025; ¶ 0045; “… device 2 may include … GPU cores [‘hardware slices’], similar to GPU 6. The graphics processing tasks may be split among these … GPU cores.” ¶ 0052); wherein
each hardware slice … stores, in an LRZ region corresponding exclusively to the hardware slice among the … LRZ regions, a pixel tile assigned to the hardware slice (NORDLUND; ¶ 0023; “For each block of surface pixels [‘pixel tile’] within an image surface, the GPU may store the surface identifier of the image surface within corresponding storage locations of the low-resolution buffer [‘hardware slice’]. … during the binning pass of a first image surface, the GPU may store the surface identifier of the first image surface within storage locations of the low-resolution buffer that correspond to each block of surface pixels within the first image surface. The GPU may perform similar functions during the binning pass of each of the image surfaces.” ¶ 0053; “Low-resolution buffer 18 may be a [2-D] buffer with … storage locations. … low-resolution buffer 18 [is] formed as a part of storage device 12 … Low-resolution buffer 18 may promote efficient indication of which pixels should be rendered to avoid unnecessarily rendering pixels that are subsequently occluded. Each storage location in low-resolution buffer 18 may correspond to a block of pixels … Low-resolution buffer 18 may be considered as a low-resolution buffer because each storage location of low-resolution buffer 18 corresponds to a plurality of pixels, rather than a single pixel.”).
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NORDLUND does not explicitly disclose hardware slices, which DAVIES discloses (DAVIES; FIG. 5; ¶ 0071; “… graphics processor 500 includes scalable thread execution resources featuring modular cores 580A-580N (… referred to as core slices), each having multiple sub-cores 550A-550N, 560A-560N (… referred to as core sub-slices). … graphics processor 500 can have … graphics cores 580A through 580N. … graphics processor 500 includes multiple graphics cores 580A-580N, each including a set of first sub-cores 550A-550N and a set of second sub-cores 560A-560N. Each sub-core in the set of first sub-cores 550A-550N includes at least a first set of execution units 552A-552N and media/texture samplers 554A-554N. Each sub-core in the set of second sub-cores 560A-560N includes at least a second set of execution units 562A-562N and samplers 564A-564N. … each sub-core 550A-550N, 560A-560N shares a set of shared resources 570A-570N. … the shared resources include shared cache memory and pixel operation logic.”).
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to modify the graphics processing unit (GPU) of NORDLUND to include the hardware slices of DAVIES. The motivation for this modification is to implement a graphics processor comprised of shader core(s), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. Additionally, this graphics processor includes an inter-core task manager, which acts as a thread dispatcher to dispatch execution threads to shader core(s) and a tiling unit to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches (DAVIES; ¶ [0133]).
Independent claim 11 exhibits similar limitations/scope when compared to claim 1; therefore, the same motivation(s) to combine references will be maintained.
Regarding claim 11, NORDLUND-DAVIES disclose a graphics processing unit (GPU), comprising means for storing a pixel tile, assigned to a hardware slice of … the GPU (NORDLUND; ¶ 0047; “For binning, GPU 6 may divide the pixels on display 8 into … blocks of pixels referred to as tiles.” ¶ 0049; “Tile memory 20 may indicate the particular tiles to which an image surface belongs, during the binning pass. … tile memory 20 may be formed as a part of storage device 12 [‘storing a pixel tile’] … GPU 6 may store the surface identifier value for an image surface within appropriate storage locations of tile memory 20 based on which tiles the image surface belongs, during the binning pass for that image surface. Tile memory 20 may be considered as including … layers. Each layer may correspond to one of the image surfaces. Each layer may be a [2-D] layer that includes … storage locations. Each storage location may correspond to one of the tiles of display 8.”), in a low-resolution Z buffer (LRZ) region corresponding exclusively to the hardware slice among … LRZ regions of a sliced LRZ communicatively coupled to each hardware slice … (NORDLUND; ¶ 0023; “For each block of surface pixels [‘pixel tile’] within an image surface, the GPU may store the surface identifier of the image surface within corresponding storage locations of the low-resolution buffer. … during the binning pass of a first image surface, the GPU may store the surface identifier of the first image surface within storage locations of the low-resolution buffer that correspond to each block of surface pixels within the first image surface. The GPU may perform similar functions during the binning pass of each of the image surfaces.” ¶ 0053; “Low-resolution buffer 18 may be a [2-D] buffer with … storage locations. … low-resolution buffer 18 [is] formed as a part of storage device 12 … Low-resolution buffer 18 may promote efficient indication of which pixels should be rendered to avoid unnecessarily rendering pixels that are subsequently occluded. Each storage location in low-resolution buffer 18 may correspond to a block of pixels … Low-resolution buffer 18 may be considered as a low-resolution buffer because each storage location of low-resolution buffer 18 corresponds to a plurality of pixels, rather than a single pixel.”).
Independent claim 12 exhibits similar limitations/scope when compared to claim 1; therefore, the same motivation(s) to combine references will be maintained.
Regarding claim 12, NORDLUND-DAVIES disclose a method for operating a … (GPU) comprising … hardware slices (DAVIES; FIG. 5; ¶ 0071), comprising
storing, by a hardware slice …, a pixel tile assigned to the hardware slice (NORDLUND; ¶ 0047) in a low-resolution Z buffer (LRZ) region corresponding exclusively to the hardware slice among … LRZ regions of a sliced LRZ communicatively coupled to each hardware slice … (NORDLUND; ¶ 0023, 0053).
Independent claim 21 exhibits similar limitations/scope when compared to claim 1; therefore, the same motivation(s) to combine references will be maintained.
Regarding claim 21, NORDLUND-DAVIES disclose a non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor device of a processor-based device (NORDLUND; ¶ 0119-120; “… the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as … instruction(s) or code on an article of manufacture comprising a non-transitory computer-readable medium. Computer-readable media may include computer data storage media. Data storage media may be any available media that can be accessed by … computer(s) or … processor(s) to retrieve instructions, code and/or data structures …”), cause the processor device to store a pixel tile (NORDLUND; ¶ 0023; “For each block of surface pixels within an image surface, the GPU may store the surface identifier of the image surface within corresponding storage locations of the low-resolution buffer. … during the binning pass of a first image surface, the GPU may store the surface identifier of the first image surface within storage locations of the low-resolution buffer that correspond to each block of surface pixels within the first image surface. The GPU may perform similar functions during the binning pass of each of the image surfaces.” ¶ 0049-51), assigned to a hardware slice … of a … (GPU) of the processor-based device (NORDLUND; FIG. 1; ¶ 0045; “Although one GPU 6 is illustrated …, aspects of this disclosure are not so limited. … device 2 may include a plurality of … GPU cores, similar to GPU 6. The graphics processing tasks may be split among these … GPU cores.”), … ([See the rationale for the rejection of these limitations repeated verbatim from independent claims 11/12 in the Office action above.]).
Regarding claim 2, claim 13, and claim 22, NORDLUND-DAVIES disclose the GPU of claim 1, the method of claim 12, and the non-transitory computer-readable medium of claim 21, wherein storing the pixel tile assigned to the hardware slice comprises:
mapping screen coordinates for the pixel tile into slice coordinates (NORDLUND; FIGS. 2A, 2B, 2C; ¶ 0078-80; “FIG. 2A illustrates image surface 22 … Image surface 22 may include 16*16 surface pixels [‘screen coordinates for the pixel tile’] with vertex coordinates of (0, 0), (0, 15), (15, 0), and (15, 15) [‘slice coordinates’]. Image surface 22 may be the back-most image surface, and … GPU 6 may assign image surface 22 the surface identifier value of 0. … GPU 6 may perform the binning pass [‘mapping’] starting from the back-most image surface, and continuing to the front-most image surface.” ¶ 0083-84; “GPU 6 may determine the tiles to which image surface 22 belongs. … in the example of FIG. 2A, each tile includes 8*8 pixels. Also, in the example of FIG. 2A, image surface 22 includes four blocks of 8*8 pixels, e.g., a block from (0, 0) to (7, 7), a block from (0, 7) to (7, 15), a block from (7, 0) to (15, 7), and block from (7, 7) to (15, 15). … in this example, image surface 22 belongs to four tiles, i.e., because there are four blocks of 8*8 pixels in image surface 22 and each tile includes 8*8 pixels [‘mapping screen coordinates for the pixel tile into slice coordinates’].”);
calculating an LRZ X index, an LRZ Y index (NORDLUND; ¶ 0085; “FIG. 2B illustrates updates to low-resolution buffer 18 which GPU 6 may update during the binning pass of image surface 22 illustrated in FIG. 2A. In the example of FIG. 2B, low resolution buffer 18 includes 16*16 storage locations. … in the example of FIG. 2B, display 8 may include 64*64 pixels. … in the example of FIG. 2B, each storage location of low-resolution buffer 18 may correspond to 4*4 blocks of pixels. … the storage location of low-resolution buffer 18 located at (0, 0) may correspond to pixels located at (0, 0) to (3, 3) on display 8. The storage location of low-resolution buffer 18 located at (1, 0) may correspond to pixels located (3, 0) to (7, 3) on display 8, and so forth. … the storage location of low-resolution buffer 18 located at (15 [‘LRZ X index’], 15 [‘LRZ Y index’]) may correspond to pixels located (59, 59) to (63, 63) …”), and an LRZ offset using the slice coordinates (NORDLUND; ¶ 0118; “… during the binning pass of the first image surface, GPU 6 may store the surface identifier value [‘LRZ offset’] of the first image surface within a storage location of low resolution buffer 18 that corresponds to a block of the … surface pixels of the first image surface (34). … with respect to FIG. 2B, each of blocks 23 of image surface 22 may correspond to one storage location of low-resolution buffer 18.”); and
determining a block address for the pixel tile within the sliced LRZ (NORDLUND; ¶ 0049; “Tile memory 20 may indicate the particular tiles to which an image surface belongs, during the binning pass. … tile memory 20 may be formed as a part of storage device 12 … GPU 6 may store the surface identifier value for an image surface within appropriate storage locations of tile memory 20 based on which tiles the image surface belongs, during the binning pass for that image surface. Tile memory 20 may be considered as including … layers. Each layer may correspond to one of the image surfaces. Each layer may be a [2-D] layer that includes … storage locations. Each storage location may correspond to one of the tiles …”) using the LRZ X index, the LRZ Y index (NORDLUND; ¶ 0085), and a slice pitch for the LRZ region (NORDLUND; ¶ 0072; “To render the image for a certain tile, GPU 6 may retrieve the values stored in low resolution buffer 18 that correspond to the pixels within that tile [‘determining a block address for the pixel tile within the sliced LRZ’]. … each storage location within low resolution buffer 18 corresponds to a 4*4 block of pixels, and each tile includes 64*48 pixels. … each tile corresponds to 192 storage locations within low resolution buffer 18, e.g., 64*48 divided by 4*4 equals 192 [‘slice pitch for the LRZ region’].”).
Regarding claim 10, NORDLUND-DAVIES disclose the GPU of claim 1, integrated into a device selected from the group consisting of: a set top box; a communications device; a mobile phone; a cellular phone; a smart phone; a tablet; a phablet; a computer; a portable computer; a mobile computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a digital video player; a video player; a portable digital video player; NORDLUND; FIG. 1; ¶ 0025; “Examples of device 2 include … wireless devices, mobile telephones, personal digital assistants (PDAs), video gaming consoles that include video displays, mobile video conferencing units, laptop computers, desktop computers, television set-top boxes, tablet computing devices, e-book readers …”).
Claims 3-4, 14-15, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over NORDLUND in view of DAVIES as applied to claims 1, 12, and 21 above, respectively, and further in view of Van Dyke et al. (U.S. Patent 6,961,057; ‘VAN DYKE’).
Regarding claim 3, claim 14, and claim 23, NORDLUND-DAVIES disclose the GPU of claim 1, the method of claim 12, and the non-transitory computer-readable medium of claim 21; however, NORDLUND-DAVIES do not explicitly disclose the following limitations, which VAN DYKE discloses:
the GPU further comprises a sliced LRZ fast clear buffer communicatively coupled to each hardware slice of the … hardware slices (VAN DYKE; Col. 16, Lines 27-62); the sliced LRZ fast clear buffer comprises
… LRZ fast clear buffer regions each corresponding to a hardware slice … (VAN DYKE; Col. 16, Lines 27-62); each LRZ fast clear buffer region … comprises
a fast clear bit corresponding to the pixel tile assigned to the hardware slice (VAN DYKE; Col. 16, Lines 27-62); and the method further comprises
updating, by the hardware slice, the fast clear bit corresponding to the pixel tile assigned to the hardware slice to indicate whether to clear the pixel tile (VAN DYKE; Col. 16, Lines 27-62; “(53) FIG. 8E shows a block diagram generally illustrating a compressed fast clear tile of Z data at 540 including a 128-bit portion of Z data including a lower 64-bit portion 542, and an upper 64-bit portion 544 [‘LRZ fast clear buffer regions’]. Because the Z buffer is re-used for each frame of image data, it is important to initialize the Z buffer as quickly as possible after a given frame has been processed. During a fast clear operation, all (x, y) positions of the Z buffer are initialized to a background value [‘LRZ fast clear buffer’]. Therefore, the Z value for each of the pixels of a tile is initialized to the same value, and so a plane defined by the Z values associated with each of the pixels of the tile has no tilt. Therefore, for the fast clear operation, the X gradient value, Y gradient value, and each of the minor Z difference values are all determined to be zero. So, only the anchor Z value is needed for fast clearing the Z buffer. Since the upper 64-bit portion 544 of Z data includes only minor predictor values which are all set to zero in accordance with fast clear operations, the upper 64-bit portion 544 of Z data provides no value for fast clear frames. … a fast clear bit 546 is used in the lower 64-bit portion 542 of compressed Z data, the fast clear bit 546 indicating whether or not each of the bits of the upper 64-bit portion 544 of compressed Z data [‘pixel tile’] is set to zero. If the fast clear bit 546 is set to zero, indicating that the frame is not a fast clear frame, the [GPU] 12 (FIG. 2B) must read the lower 64 bit portion 542 and the upper 64-bit portion 544. When the fast clear bit is set to one, indicating that the bits of the upper 64-bit portion 544 are all equal to zero, the [GPU] need not read the upper 64-bit portion [‘fast clear bit corresponding to the pixel tile’].”).
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to modify the GPU of claim 1, the method of claim 12, and the non-transitory computer-readable medium of claim 21 of NORDLUND-DAVIES to include the various teachings of VAN DYKE. The motivation for this modification is to realize an 8* improvement in efficiency over prior art uncompressed Z buffer fast clear operations by executing a fast clear of the Z buffer. This may be accomplished by using fast clear operations, in which the GPU only writes the lower 64-bit portion to the Z buffer, and only one clock cycle is required to write the entire fast clear tile to the Z buffer, instead of two (VAN DYKE; Col. 16, Lines 57-62).
Regarding claim 4, claim 15, and claim 24, NORDLUND-DAVIES-VAN DYKE disclose the GPU of claim 3, the method of claim 14, and the non-transitory computer-readable medium of claim 23, further comprising:
reading, by the hardware slice, from any of the … LRZ fast clear buffer regions; and
writing, by the hardware slice, only to the LRZ fast clear buffer region corresponding to the hardware slice among the … LRZ fast clear buffer regions (VAN DYKE; Col. 5, Lines 8-13; “… fast clear operations … provide a … large increase in effective Z data bandwidth. Because the Z values are written out in a compressed format, the read and write operations may be performed very quickly, thereby allowing for increased performance of Z-buffering operations.” Col. 6, Lines 21-26; “[Read-modify-write] operations are inherent to Z-buffer operations which include the steps of: receiving current generated Z values from upstream stages of the 3D pipeline; reading previous Z values from associated memory locations in the Z-buffer; merging the current Z data with the previous Z data; and then writing back the merged data to the Z-buffer.”).
Claims 5, 16, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over NORDLUND in view of DAVIES as applied to claims 1, 12, and 21 above, respectively, and further in view of Fuller (U.S. PG-PUB 2019/0362533, ‘FULLER’).
Regarding claim 5, claim 16, and claim 25, NORDLUND-DAVIES disclose the GPU of claim 1, the method of claim 12, and the non-transitory computer-readable medium of claim 21; however, NORDLUND-DAVIES do not explicitly disclose the following limitations, which FULLER discloses:
the GPU further comprises a sliced LRZ metadata buffer (FULLER; FIG. 1; ¶ 0035) communicatively coupled to each hardware slice … (DAVIES; FIG. 5; ¶ 0069; “… graphics processor 500 includes a ring interconnect 502, a pipeline front-end 504, a media engine 537, and graphics cores 580A-580N. … ring interconnect 502 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. … the graphics processor is one of many processors integrated within a multi-core processing system.”); the sliced LRZ metadata buffer comprises
… LRZ metadata buffer regions (FULLER; FIG. 1; ¶ 0035) each corresponding to a hardware slice … (DAVIES; FIG. 5; ¶ 0071); each LRZ metadata buffer region … comprises
a metadata indicator (FULLER; FIG. 1; ¶ 0035); and the method further comprises
updating the metadata indicator of the LRZ metadata buffer region corresponding to the hardware slice (FULLER; FIG. 1; ¶ 35; “The GPU 120 may include GPU depth data 129 for storing depth data related to a full resolution rendering. … the GPU depth data 129 … includes a hierarchical depth buffer 130, [also known as] hierarchical z buffer or HZB. The hierarchical depth buffer 130 may also include metadata 132 [‘LRZ metadata buffer’], which may include additional information for [pixel groups]. … the hierarchical depth buffer 130 and metadata 132 may include information for 8×8 groups of pixels referred to as tiles [‘LRZ metadata buffer regions’]. The hierarchical depth buffer 130 contains the minimum and/or maximum depth values for the set of pixels contained in that tile. These minimum/maximum depth values [are] conservatively quantized, … whereas full resolution depth data 136 [is] stored using more bits … The hierarchical depth buffer 130 may have less precision than the actual GPU 120 calculations. The metadata 132 may also include a clear state bit and other data used to accelerate depth testing or clear operations [‘metadata indicator’].”).
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to modify the GPU of claim 1, the method of claim 12, and the non-transitory computer-readable medium of claim 21 of NORDLUND-DAVIES to include the various teachings of FULLER. The motivation for this modification is to provide a method of rendering an image at a full resolution that includes rendering an occlusion geometry at a reduced resolution lower than the full resolution. The method may include sampling a depth value of pixels of the occlusion geometry. The method may include pre-populating GPU depth data (e.g., hierarchical depth buffer metadata) based on the sampled depth values. The method may include culling at least one tile or pixel from a full resolution rendering process in response to a depth of the … tile(s) or pixel(s) being further away than a corresponding depth value in the GPU depth data. The method may include performing the full resolution rendering process on remaining tiles or pixels to generate the image at the full resolution (FULLER; ¶ [0007]). This prevents overdraw, which occurs when a closer object is drawn using pixels that already include another object. The existing pixels are replaced with pixels for the closer object. Generally, overdrawing is considered wasteful because the properties of each overdrawn pixel are determined multiple times, using additional processing resources (FULLER; ¶ [0002]).
Claims 6, 17, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over NORDLUND in view of DAVIES and FULLER as applied to claims 5, 16, and 25 above, respectively, and further in view of VAN DYKE.
Regarding claim 6, claim 17, and claim 26, NORDLUND-DAVIES-FULLER disclose the GPU of claim 5, the method of claim 16, and the non-transitory computer-readable medium of claim 25; however, NORDLUND-DAVIES-FULLER do not explicitly and fully disclose that the GPU of claim 5, the method of claim 16, and the non-transitory computer-readable medium of claim 25 further comprise:
READING, by the hardware slice (DAVIES; FIG. 5; ¶ 0071), from only the LRZ metadata buffer region (FULLER; FIG. 1; ¶ 0035) corresponding to the hardware slice among the … LRZ metadata buffer regions (FULLER; FIG. 1; ¶ 0035); and
WRITING, by the hardware slice (DAVIES; FIG. 5; ¶ 0071), to only the LRZ metadata buffer region (FULLER; FIG. 1; ¶ 0035) corresponding to the hardware slice among the … LRZ metadata buffer regions (VAN DYKE; Col. 5, Lines 8-13; “… fast clear operations … provide a particularly large increase in effective Z data bandwidth. Because the Z values are written out in a compressed format, the read and write operations may be performed very quickly, thereby allowing for increased performance of Z-buffering operations.” Col. 6, Lines 21-26; “[Read-modify-write] operations are inherent to Z-buffer operations which include the steps of: receiving current generated Z values from upstream stages of the 3D pipeline; reading previous Z values from associated memory locations in the Z-buffer; merging the current Z data with the previous Z data; and then writing back the merged data to the Z-buffer.”).
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to modify the GPU of claim 5, the method of claim 16, and the non-transitory computer-readable medium of claim 25 of NORDLUND-DAVIES-FULLER to include the various teachings of VAN DYKE. The motivation for this modification is to realize an 8* improvement in efficiency over prior art uncompressed Z buffer fast clear operations by executing a fast clear of the Z buffer. This may be accomplished by using fast clear operations, in which the GPU only writes the lower 64-bit portion to the Z buffer, and only one clock cycle is required to write the entire fast clear tile to the Z buffer, instead of two (VAN DYKE; Col. 16, Lines 57-62).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN M COFINO whose telephone number is (303) 297-4268. The examiner can normally be reached Monday-Friday 10A-4P MT.
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/JONATHAN M COFINO/Examiner, Art Unit 2614
/KENT W CHANG/Supervisory Patent Examiner, Art Unit 2614
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