DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Amendment on 02/12/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 11-15 and 17-19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Fiocchi (US 2022/0171417).
Regarding claim 1, Fiocchi discloses (see figures 1-6) a regulator circuit (figure 1) configured to generate a regulated voltage (figure 1, part regulated voltage at OUT from MPOUT) for a load (figure 1, part load at Iload) based on an unregulated supply voltage (figure 1, part unregulated supply voltage VS), the regulator circuit (figure 1) comprising: a regulator (figure 1, part regulator generated by MPOUT and AMP), configured to receive the unregulated supply voltage (figure 1, part unregulated supply voltage VS) and to generate the regulated voltage (figure 1, part regulated voltage at OUT from MPOUT) based on the unregulated supply voltage (figure 1, part unregulated supply voltage VS) (paragraphs [0044]-[0046]; FIG. 1 shows an example embodiment of voltage regulator comprising an amplifier AMP… An output side of the amplifier AMP is electrically connected to the output transistor MPOUT. In this particular embodiment the output transistor MPOUT is a PMOS transistor with its gate connected to the output side of the amplifier AMP. Furthermore, the source of the output transistor MPOUT is connected to a supply terminal VS. A controlled section, e.g. the drain, of the output transistor MPOUT is connected to a load, represented as load current source Iload and, further, to the supply terminal VS), where in the regulated voltage (figure 1, part regulated voltage at OUT from MPOUT) comprises noise (figure 1, part noise of the regulated voltage at OUT from MPOUT) from the unregulated supply voltage (figure 1, part unregulated supply voltage VS); and a noise compensation circuit (figure 1, part noise compensation circuit generated by OC) configured to amplify noise (figure 1, part through MREP, M1, R and C) of the unregulated supply voltage (figure 1, part unregulated supply voltage VS), and to inject the amplified noise (figure 1, part through M2) onto the regulated voltage (figure 1, part regulated voltage at OUT from MPOUT) (paragraphs [0044]-[0052]; In operation the output transistor MPOUT is connected to the load current source Iload and senses a load current. The reference terminal VR is connected to a reference supply such that at its output side the amplifier AMP provides an output in terms of the reference supply. The current mirror mirrors and attenuates the load current which is supplied by the output transistor MPOUT as power transistor. Thus, an attenuated load current, or replica of the load current, is supplied by the replica transistor MREP. The replica is then filtered by the filter circuit. The filtered replica is then re-injected in parallel to the load current as an additional load to the output transistor MPOUT via the output terminal).
Regarding claim 2, Fiocchi discloses everything claimed as applied above (see claim 1). Further, Fiocchi discloses (see figures 1-6) the regulator (figure 1, part regulator generated by MPOUT and AMP) generates the regulated voltage (figure 1, part regulated voltage at OUT from MPOUT) using a feedback loop having a bandwidth (figure 1, part feedback loop at VFB), and wherein the injected amplified sensed noise (figure 1, part through M2) as frequency components (figure 1, part through M2) which are outside of the bandwidth of the feedback loop (figure 1, part feedback loop at VFB).
Regarding claim 3, Fiocchi discloses everything claimed as applied above (see claim 1). Further, Fiocchi discloses (see figures 1-6) the noise compensation circuit (figure 1, part noise compensation circuit generated by OC) comprises a noise sensor circuit (figure 1, part noise sensor circuit generated by MREP) configured to sense noise in the unregulated supply voltage (figure 1, part unregulated supply voltage VS), and to generate a noise signal based on the sensed noise (figure 1, part noise signal from the noise sensor circuit generated by MREP).
Regarding claim 4, Fiocchi discloses everything claimed as applied above (see claim 3). Further, Fiocchi discloses (see figures 1-6) the noise compensation circuit (figure 1, part noise compensation circuit generated by OC) comprises a noise amplification circuit (figure 1, part noise amplification circuit generated by MREP, M1, R and C) configured to receive the noise signal (figure 1, part noise signal from the noise sensor circuit generated by MREP), and to amplify the noise signal to generate an amplified noise signal (figure 1, part amplified noise signal from the noise amplification circuit generated by MREP, M1, R and C).
Regarding claim 5, Fiocchi discloses everything claimed as applied above (see claim 4). Further, Fiocchi discloses (see figures 1-6) the noise compensation circuit (figure 1, part noise compensation circuit generated by OC) comprises a noise injection circuit (figure 1, part noise injection circuit generated by M2) configured to generate a noise injection signal (figure 1, part noise injection signal from noise injection circuit generated by M2) corresponding with the amplified noise signal (figure 1, part amplified noise signal from the noise amplification circuit generated by MREP, M1, R and C), and to inject the noise injection signal (figure 1, part noise injection signal from noise injection circuit generated by M2) onto the regulated voltage (figure 1, part regulated voltage at OUT from MPOUT).
Regarding claim 6, Fiocchi discloses everything claimed as applied above (see claim 5). Further, Fiocchi discloses (see figures 1-6) the noise injection signal (figure 1, part noise injection signal from noise injection circuit generated by M2) at least partially compensates (figure 1, part noise injection signal from noise injection circuit generated by M2) for the noise in the regulated voltage (figure 1, part noise of the regulated voltage at OUT from MPOUT) from the unregulated supply voltage (figure 1, part unregulated supply voltage VS).
Regarding claim 7, Fiocchi discloses everything claimed as applied above (see claim 5). Further, Fiocchi discloses (see figures 1-6) the noise injection circuit (figure 1, part noise injection circuit generated by M2) comprises a transconductance stage (figure 1, part M2).
Regarding claim 8, Fiocchi discloses everything claimed as applied above (see claim 5). Further, Fiocchi discloses (see figures 1-6) the noise injection circuit (figure 1, part noise injection circuit generated by M2) comprises an inverting stage (figure 1, part M2).
Regarding claim 11, Fiocchi discloses (see figures 1-6) a noise compensation circuit (figure 1, part noise compensation circuit generated by OC) configured to compensate noise in a regulated voltage (figure 1, part noise of the regulated voltage at OUT from MPOUT) generated from an unregulated supply voltage (figure 1, part unregulated supply voltage VS) (paragraphs [0044]-[0046]; FIG. 1 shows an example embodiment of voltage regulator comprising an amplifier AMP… An output side of the amplifier AMP is electrically connected to the output transistor MPOUT. In this particular embodiment the output transistor MPOUT is a PMOS transistor with its gate connected to the output side of the amplifier AMP. Furthermore, the source of the output transistor MPOUT is connected to a supply terminal VS. A controlled section, e.g. the drain, of the output transistor MPOUT is connected to a load, represented as load current source Iload and, further, to the supply terminal VS), the noise compensation circuit (figure 1, part noise compensation circuit generated by OC) comprising: a noise amplification circuit (figure 1, part noise amplification circuit generated by MREP, M1, R and C) configured to amplify noise (figure 1, part noise amplification circuit generated by MREP, M1, R and C) from the unregulated supply voltage based (figure 1, part unregulated supply voltage VS); and a noise injection circuit (figure 1, part noise injection circuit generated by M2) configured to generate a noise injection signal (figure 1, part noise injection circuit generated by M2) corresponding with the amplified noise (figure 1, part amplified noise from noise amplification circuit generated by MREP, M1, R and C), and to inject the noise injection signal (figure 1, part through M2) onto the regulated voltage (figure 1, part the regulated voltage at OUT from MPOUT) (paragraphs [0044]-[0052]; In operation the output transistor MPOUT is connected to the load current source Iload and senses a load current. The reference terminal VR is connected to a reference supply such that at its output side the amplifier AMP provides an output in terms of the reference supply. The current mirror mirrors and attenuates the load current which is supplied by the output transistor MPOUT as power transistor. Thus, an attenuated load current, or replica of the load current, is supplied by the replica transistor MREP. The replica is then filtered by the filter circuit. The filtered replica is then re-injected in parallel to the load current as an additional load to the output transistor MPOUT via the output terminal).
Regarding claim 12, claim 3 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 13, claim 6 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 14, claim 7 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 15, claim 8 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 17, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 18, claim 6 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 19, claim 8 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Fiocchi (US 2022/0171417), in view of Shreepathi Bhat (11,592,854). Hereinafter Bhat.
Regarding claim 9, Fiocchi discloses everything claimed as applied above (see claim 3). Further, Fiocchi discloses (see figures 1-6) the noise sensor circuit (figure 1, part noise sensor circuit generated by MREP). However, Fiocchi does not expressly disclose a bias voltage generation circuit.
Bhat teaches (see figures 1-12) the noise sensor circuit (figure 9, part noise sensor circuit generated by 982, IBIAS, 980, 984 and 988) comprises a bias voltage generation circuit (figure 9, part bias voltage generation circuit generated by 976 [IBIAS], 980, 984 and 988) (column 16; lines 4-59).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the noise sensor circuit of Fiocchi with the bias voltage generation circuit features as taught by Bhat, because it provides more efficient regulation with more accurate noise compensation (column 3; lines 10-28).
Claims 10, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fiocchi (US 2022/0171417), in view of Chen et al. (US 2008/0265853), hereinafter Chen.
Regarding claim 10, Fiocchi discloses everything claimed as applied above (see claim 1). Further, Fiocchi discloses (see figures 1-6) the noise compensation circuit (figure 1, part noise compensation circuit generated by OC) comprises an amplification stage (figure 1, part amplification stage generated by MREP, M1, R and C). However, Fiocchi does not expressly disclose a plurality of amplification stages.
Chen teaches (see figures 1-6) the noise compensation circuit (figure 2, part noise compensation circuit generated by 220, 240 and 250) comprises a plurality of amplification stages (figure 2, part plurality of amplification stages generated by 220, 240 and M17).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the noise compensation circuit of Fiocchi with the plurality of amplification stages features as taught by Chen, because it provides more efficient voltage regulation with quick restore of the output voltage (paragraph [0007]).
Regarding claim 16, claim 10 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 20, claim 10 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Response to Arguments
Applicant's arguments filed 02/12/2026 have been fully considered but they are not persuasive.
Applicant’s argues on pages 5-7 of the Applicant's Response (“Fiocchi fails to disclose a noise compensation circuit configured to amplify noise of the unregulated supply voltage”).
The Examiner respectfully disagrees with Applicant’s arguments, because Fiocchi discloses a noise compensation circuit (figure 1, part noise compensation circuit generated by OC) configured to amplify noise (figure 1, part through MREP, M1, R and C) of the unregulated supply voltage (figure 1, part unregulated supply voltage VS), and to inject the amplified noise (figure 1, part through M2) onto the regulated voltage (figure 1, part regulated voltage at OUT from MPOUT) (paragraphs [0044]-[0052]). As discussed above, Fiocchi’s reference discloses the same structural stages as presented in Figure 7 of the application (Application; Figure 7, part 730). More specific, Fiocchi’s reference discloses the compensation circuit (figure 1, part noise compensation circuit generated by OC), wherein the noise of the unregulated supply voltage (figure 1, part noise of the unregulated supply voltage VS) is sensing through MREP stage that is connected to VS (figure 1, part MREP). This sensed noise is amplified and injected through M1, R/C and M2 stages (figures 1, parts M1, R/C and M2). The final noise compensation happens through M2 (figure 1, part M2) that is connected to the load (figure 1, part load at Iload). Therefore, Fiocchi meets with the claimed limitation with the same structural stages as presented in Figure 7 of the application (Application; Figure 7, part 730). Furthermore, Bhat’s reference teaches this noise compensation circuit features of amplify noise of the unregulated supply voltage (see figure 9, parts 976, 980, 984, 988, 982, 990 and 992; through Vnoise_rej). Additional, it should be noted that broad claim language as recited does not defines the specific structure stages used to generates this noise compensation circuit. The examiner suggests the applicant to positively recite in the claim language the specific structure stages used to generates this noise compensation circuit that differentiates this application, in order to distinguish the invention from the prior art of record.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/Supervisory Patent Examiner, Art Unit 2838
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