DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Request for Continued Examination (RCE) on 08/10/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-9, 11, 12, 14, 15, 17-19, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Shreepathi Bhat (11,592,854). Hereinafter Bhat, in view of Fiocchi (US 2022/0171417).
Regarding claim 1, Bhat discloses (see figures 1-12) a regulator circuit (figure 1, part 100) configured to generate a regulated voltage (figure 1, part VOUT) for a load (figure 1, part 168) based on an unregulated supply voltage (figure 1, part VIN) (column 3; lines 10-67; the linear voltage regulator 100 receives an input voltage, VIN at a voltage input 101, a reference voltage, VREF and provides an output voltage, VOUT (a voltage output 102)), the regulator circuit (figure 1, part 100) comprising: a regulator (figure 1, part regulator generated by 103, 112 and 120), configured to receive the unregulated supply voltage (figure 1, part VIN) and to generate the regulated voltage (figure 1, part VOUT; through 120) based on the unregulated supply voltage (figure 1, part VIN), wherein the regulated voltage (figure 1, part VOUT; through 120) comprises noise (figure 1, part noise at VOUT [VOUT_AC]; without noise compensation circuit) from the unregulated supply voltage (figure 1, part VIN) (column 4; lines 3-57; The linear voltage regulator 100 is configured such that the output voltage, VOUT remains constant in situations where the input voltage, VIN experiences noise, such as frequency spurs, voltage flickers, etc… The power transistor 120 also includes an input node 124 coupled to the input voltage, VIN at the voltage input 101 and an output node 128 that provides the output voltage, VOUT at the voltage output 102 of the linear voltage regulator 100 that is also coupled to the second input node 106 of the op-amp 103); and a noise compensation circuit (figure 1, part noise compensation circuit generated by 136 and 156) (figure 9, part noise compensation circuit generated by 940 and 920) configured to amplify (figure 9, part noise compensation circuit generated by 940 and 920; through 982 and 990) noise of the unregulated supply voltage (figure 9, part noise of VIN [VIN_AC]), and to inject (figure 9, part noise compensation circuit generated by 940 and 920; through 992) the amplified noise in opposite phase (figure 9, part Vnoise_rej) to the noise from the unregulated supply voltage (figure 9, part noise of VIN [VIN_AC]) (column 18; lines 7-37; The feedforward module 920 receives the PSRR signal, VPSRR and the power supply rejection ratio capacitor 988 blocks the direct current (DC) portion of the PSRR signal, VPSRR, such that the noise component of the PSRR signal, VPSRR_AC is provided to the node 986 and amplified by the fourth PFET 982. The amplified version of the noise component of the PSRR signal, VPSRR_AC is provided to the current mirror formed by the first NFET 990 and the second NFET 992 and is coupled to the output node 968 of the feedforward module 920 outputs a noise rejection signal, VNOISE_REJ (alternatively referred to as a feedforward signal) is an amplified and inverted version of the PSRR signal, VPSRR_AC, which in turn is an amplified version of the noise in the input voltage, VIN_AC… Responsive to injection of the noise rejection signal, VNOISE_REJ, the buffer 912 and the power transistor 924 are configured to operate in concert to filter noise from the input voltage, VIN. More particularly, injection of the noise rejection signal, VNOISE_REJ injects an inverted version of the noise at the input voltage, VIN_AC into the output of the buffer 912, V.BUFF. Accordingly, the inverted version of the noise of the input voltage, VIN_AC is included in the signal driving the gate of the power transistor 924, such that the power transistor 924 cancels out the noise component from the input voltage, VIN_AC during amplification of the input voltage, VIN during operation in the linear region).
Bhat does not expressly disclose inject the amplified noise onto the regulated voltage.
Fiocchi teaches (see figures 1-6) a noise compensation circuit (figure 1, part noise compensation circuit generated by OC) configured to amplify noise (figure 1, part through MREP, M1, R and C) of the unregulated supply voltage (figure 1, part unregulated supply voltage VS), and to inject the amplified noise (figure 1, part through M2) onto the regulated voltage (figure 1, part regulated voltage at OUT from MPOUT) (paragraphs [0044]-[0052]; In operation the output transistor MPOUT is connected to the load current source Iload and senses a load current. The reference terminal VR is connected to a reference supply such that at its output side the amplifier AMP provides an output in terms of the reference supply. The current mirror mirrors and attenuates the load current which is supplied by the output transistor MPOUT as power transistor. Thus, an attenuated load current, or replica of the load current, is supplied by the replica transistor MREP. The replica is then filtered by the filter circuit. The filtered replica is then re-injected in parallel to the load current as an additional load to the output transistor MPOUT via the output terminal).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the noise compensation circuit of Bhat with the noise compensation circuit (more specific inject the noise compensation to the regulated voltage at the output) features as taught by Fiocchi and obtain a regulator circuit configured to generate a regulated voltage for a load based on an unregulated supply voltage, the regulator circuit comprising: a regulator, configured to receive the unregulated supply voltage and to generate the regulated voltage based on the unregulated supply voltage, wherein the regulated voltage comprises noise from the unregulated supply voltage; and a noise compensation circuit configured to amplify noise of the unregulated supply voltage, and to inject the amplified noise onto the regulated voltage in opposite phase to the noise from the unregulated supply voltage, because it provides more efficient controller with more direct compensation in order to obtain stable and accurate output more easy and quick (paragraph [0011]).
Regarding claim 2, Bhat and Fiocchi teach everything claimed as applied above (see claim 1). Further, Bhat discloses (see figures 1-12) the regulator (figure 1, part regulator generated by 103, 112 and 120) generates the regulated voltage (figure 1, part VOUT; through 120) using a feedback loop having a bandwidth (figure 1, part feedback loop at 106), and wherein the injected amplified sensed noise (figure 9, part Vnoise_rej) comprises frequency components (figure 9, part Vnoise_rej) which are outside of the bandwidth of the feedback loop (figure 1, part feedback loop at 106) (figure 9, part feedback loop at lower input of 904).
Regarding claim 3, Bhat and Fiocchi teach everything claimed as applied above (see claim 1). Further, Bhat discloses (see figures 1-12) the noise compensation circuit (figure 9, part noise compensation circuit generated by 940 and 920) comprises a noise sensor circuit (figure 9, part noise sensor circuit generated by 954) configured to sense noise in the unregulated supply voltage (figure 9, part VIN), and to generate a noise signal based on the sensed noise (figure 9, part noise signal VPSRR from the noise sensor circuit generated by 954) (column 14; lines 56-67; The first PFET 954, alternatively referred to as a sensing transistor or sensing PFET).
Regarding claim 4, Bhat and Fiocchi teach everything claimed as applied above (see claim 3). Further, Bhat discloses (see figures 1-12) the noise compensation circuit (figure 9, part noise compensation circuit generated by 940 and 920) comprises a noise amplification circuit (figure 9, part noise amplification circuit generated by 982 and 990) configured to receive the noise signal (figure 9, part noise signal VPSRR from the noise sensor circuit generated by 954), and to amplify the noise signal to generate an amplified noise signal (figure 9, part amplified noise signal from the noise amplification circuit generated by 982 and 990) (column 18; lines 7-37; The feedforward module 920 receives the PSRR signal, VPSRR and the power supply rejection ratio capacitor 988 blocks the direct current (DC) portion of the PSRR signal, VPSRR, such that the noise component of the PSRR signal, VPSRR_AC is provided to the node 986 and amplified by the fourth PFET 982. The amplified version of the noise component of the PSRR signal, VPSRR_AC is provided to the current mirror formed by the first NFET 990 and the second NFET 992 and is coupled to the output node 968 of the feedforward module 920 outputs a noise rejection signal, VNOISE_REJ (alternatively referred to as a feedforward signal) is an amplified and inverted version of the PSRR signal, VPSRR_AC, which in turn is an amplified version of the noise in the input voltage, VIN_AC… Responsive to injection of the noise rejection signal, VNOISE_REJ, the buffer 912 and the power transistor 924 are configured to operate in concert to filter noise from the input voltage, VIN. More particularly, injection of the noise rejection signal, VNOISE_REJ injects an inverted version of the noise at the input voltage, VIN_AC into the output of the buffer 912, VBUFF. Accordingly, the inverted version of the noise of the input voltage, VIN_AC is included in the signal driving the gate of the power transistor 924, such that the power transistor 924 cancels out the noise component from the input voltage, VIN_AC during amplification of the input voltage, VIN during operation in the linear region).
Regarding claim 5, Bhat and Fiocchi teach everything claimed as applied above (see claim 4). Further, Bhat discloses (see figures 1-12) the noise compensation circuit (figure 9, part noise compensation circuit generated by 940 and 920) comprises a noise injection circuit (figure 9, part noise injection circuit generated by 992) configured to generate a noise injection signal (figure 9, part noise injection signal Vnoise_rej from noise injection circuit generated by 992) corresponding with the amplified noise signal (figure 9, part amplified noise signal from the noise amplification circuit generated by 982 and 990), and to inject the noise injection signal (figure 9, part noise injection signal Vnoise_rej from noise injection circuit generated by 992) (column 18; lines 7-37; The feedforward module 920 receives the PSRR signal, VPSRR and the power supply rejection ratio capacitor 988 blocks the direct current (DC) portion of the PSRR signal, VPSRR, such that the noise component of the PSRR signal, VPSRR_AC is provided to the node 986 and amplified by the fourth PFET 982. The amplified version of the noise component of the PSRR signal, VPSRR_AC is provided to the current mirror formed by the first NFET 990 and the second NFET 992 and is coupled to the output node 968 of the feedforward module 920 outputs a noise rejection signal, VNOISE_REJ (alternatively referred to as a feedforward signal) is an amplified and inverted version of the PSRR signal, VPSRR_AC, which in turn is an amplified version of the noise in the input voltage, VIN_AC… Responsive to injection of the noise rejection signal, VNOISE_REJ, the buffer 912 and the power transistor 924 are configured to operate in concert to filter noise from the input voltage, VIN. More particularly, injection of the noise rejection signal, VNOISE_REJ injects an inverted version of the noise at the input voltage, VIN_AC into the output of the buffer 912, VBUFF. Accordingly, the inverted version of the noise of the input voltage, VIN_AC is included in the signal driving the gate of the power transistor 924, such that the power transistor 924 cancels out the noise component from the input voltage, VIN_AC during amplification of the input voltage, VIN during operation in the linear region). However, Bhat does not expressly disclose inject the noise injection signal onto the regulated voltage.
Fiocchi teaches (see figures 1-6) the noise compensation circuit (figure 1, part noise compensation circuit generated by OC) comprises a noise injection circuit (figure 1, part noise injection circuit generated by M2) configured to generate a noise injection signal (figure 1, part noise injection signal from noise injection circuit generated by M2) corresponding with the amplified noise signal (figure 1, part amplified noise signal from the noise amplification circuit generated by MREP, M1, R and C), and to inject the noise injection signal (figure 1, part noise injection signal from noise injection circuit generated by M2) onto the regulated voltage (figure 1, part regulated voltage at OUT from MPOUT).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the noise compensation circuit of Bhat with the noise compensation circuit (more specific inject the noise compensation to the regulated voltage at the output) features as taught by Fiocchi and obtain the noise compensation circuit comprises a noise injection circuit configured to generate a noise injection signal corresponding with the amplified noise signal, and to inject the noise injection signal onto the regulated voltage, because it provides more efficient controller with more direct compensation in order to obtain stable and accurate output more easy and quick (paragraph [0011]).
Regarding claim 7, Bhat and Fiocchi teach everything claimed as applied above (see claim 5). Further, Bhat discloses (see figures 1-12) the noise injection circuit (figure 9, part noise injection circuit generated by 992) comprises a transconductance stage (figure 9, part 992).
Regarding claim 8, Bhat and Fiocchi teach everything claimed as applied above (see claim 5). Further, Bhat discloses (see figures 1-12) the noise injection circuit (figure 9, part noise injection circuit generated by 992) comprises an inverting stage (figure 9, part 992).
Regarding claim 9, Bhat and Fiocchi teach everything claimed as applied above (see claim 1). Further, Bhat discloses (see figures 1-12) the noise sensor circuit (figure 9, part noise sensor circuit generated by 954) comprises a bias voltage generation circuit (figure 9, part bias voltage generation circuit generated by 976, 980, 984 and 988).
Regarding claim 11, Bhat discloses (see figures 1-12) a noise compensation circuit (figure 1, part noise compensation circuit generated by 136 and 156) (figure 9, part noise compensation circuit generated by 940 and 920) configured to compensate (figure 9, part noise compensation circuit generated by 940 and 920) noise in a regulated voltage (figure 1, part noise at VOUT [VOUT_AC]; without noise compensation circuit) generated from an unregulated supply voltage (figure 1, part VIN) (column 4; lines 3-57; The linear voltage regulator 100 is configured such that the output voltage, VOUT remains constant in situations where the input voltage, VIN experiences noise, such as frequency spurs, voltage flickers, etc), the noise compensation circuit (figure 9, part noise compensation circuit generated by 940 and 920) comprising: a noise amplification circuit (figure 9, part noise amplification circuit generated by 982 and 990) configured to amplify noise from the unregulated supply voltage (figure 1, part VIN); and a noise injection circuit (figure 1, part noise injection circuit generated by 992) configured to generate a noise injection signal phase (figure 1, part Vnoise_rej) corresponding with the amplified noise (figure 9, part amplified noise from noise amplification circuit generated by 982 and 990), and to inject (figure 1, part through 002) the noise injection signal (figure 1, part Vnoise_rej) in opposite phase (figure 1, part through 992) to the noise from the unregulated supply voltage (figure 1, part noise of VIN [VIN_AC]) (column 18; lines 7-37; The feedforward module 920 receives the PSRR signal, VPSRR and the power supply rejection ratio capacitor 988 blocks the direct current (DC) portion of the PSRR signal, VPSRR, such that the noise component of the PSRR signal, VPSRR_AC is provided to the node 986 and amplified by the fourth PFET 982. The amplified version of the noise component of the PSRR signal, VPSRR_AC is provided to the current mirror formed by the first NFET 990 and the second NFET 992 and is coupled to the output node 968 of the feedforward module 920 outputs a noise rejection signal, VNOISE_REJ (alternatively referred to as a feedforward signal) is an amplified and inverted version of the PSRR signal, VPSRR_AC, which in turn is an amplified version of the noise in the input voltage, VIN_AC… Responsive to injection of the noise rejection signal, VNOISE_REJ, the buffer 912 and the power transistor 924 are configured to operate in concert to filter noise from the input voltage, VIN. More particularly, injection of the noise rejection signal, VNOISE_REJ injects an inverted version of the noise at the input voltage, VIN_AC into the output of the buffer 912, VBUFF. Accordingly, the inverted version of the noise of the input voltage, VIN_AC is included in the signal driving the gate of the power transistor 924, such that the power transistor 924 cancels out the noise component from the input voltage, VIN_AC during amplification of the input voltage, VIN during operation in the linear region).
Bhat does not expressly disclose inject the noise injection signal onto the regulated voltage.
Fiocchi teaches (see figures 1-6) the noise compensation circuit (figure 1, part noise compensation circuit generated by OC) comprising: a noise amplification circuit (figure 1, part noise amplification circuit generated by MREP, M1, R and C) configured to amplify noise (figure 1, part noise amplification circuit generated by MREP, M1, R and C) from the unregulated supply voltage based (figure 1, part unregulated supply voltage VS); and a noise injection circuit (figure 1, part noise injection circuit generated by M2) configured to generate a noise injection signal (figure 1, part noise injection circuit generated by M2) corresponding with the amplified noise (figure 1, part amplified noise from noise amplification circuit generated by MREP, M1, R and C), and to inject the noise injection signal (figure 1, part through M2) onto the regulated voltage (figure 1, part the regulated voltage at OUT from MPOUT) (paragraphs [0044]-[0052]; In operation the output transistor MPOUT is connected to the load current source Iload and senses a load current. The reference terminal VR is connected to a reference supply such that at its output side the amplifier AMP provides an output in terms of the reference supply. The current mirror mirrors and attenuates the load current which is supplied by the output transistor MPOUT as power transistor. Thus, an attenuated load current, or replica of the load current, is supplied by the replica transistor MREP. The replica is then filtered by the filter circuit. The filtered replica is then re-injected in parallel to the load current as an additional load to the output transistor MPOUT via the output terminal).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the noise compensation circuit of Bhat with the noise compensation circuit (more specific inject the noise compensation to the regulated voltage at the output) features as taught by Fiocchi and obtain a noise compensation circuit configured to compensate noise in a regulated voltage generated from an unregulated supply voltage, the noise compensation circuit comprising: a noise amplification circuit configured to amplify noise from the unregulated supply voltage; and a noise injection circuit configured to generate a noise injection signal corresponding with the amplified noise, and to inject the noise injection signal onto the regulated voltage in opposite phase to the noise from the unregulated supply voltage, because it provides more efficient controller with more direct compensation in order to obtain stable and accurate output more easy and quick (paragraph [0011]).
Regarding claim 12, claim 3 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 14, claim 7 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 15, claim 8 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 17, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 18, Bhat and Fiocchi teach everything claimed as applied above (see claim 17). Further, Bhat discloses (see figures 1-12) the injected amplified noise (figure 9, part Vnoise_rej) at least partially compensates for the noise in the regulated voltage (figure 9, part VOUT from 924) from the unregulated supply voltage (figure 9, part VIN).
Regarding claim 19, claim 8 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 21, Bhat and Fiocchi teach everything claimed as applied above (see claim 1). Further, Bhat discloses (see figures 1-12) the noise compensation circuit (figure 9, part noise compensation circuit generated by 940 and 920) is configured to directly generate the amplified noise (figure 9, part Vnoise_rej) based on the unregulated supply voltage (figure 9, part VIN) without input from a feedback loop (figure 9, part noise compensation circuit generated by 940 and 920; without input from a feedback loop).
Regarding claim 22, Bhat and Fiocchi teach everything claimed as applied above (see claim 1). Further, Bhat discloses (see figures 1-12) a noise sensor circuit (figure 9, part noise sensor circuit generated by 954 and 982) comprising a noise-sensing transistor (figure 9, part 982); and a bias voltage generation circuit (figure 9, part bias voltage generation circuit generated by 976, 980, 984 and 988) comprising a diode-connected transistor (figure 9, part 980) configured to generate a bias voltage at a gate of the noise-sensing transistor (figure 9, part bias voltage at gate of 982) based on the unregulated supply voltage (figure 9, part VIN) and a current generator (figure 9, part Ibias).
Claims 10, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shreepathi Bhat (11,592,854). Hereinafter Bhat, in view of Fiocchi (US 2022/0171417), and further in view of Chen et al. (US 2008/0265853), hereinafter Chen.
Regarding claim 10, Bhat and Fiocchi teach everything claimed as applied above (see claim 1). Further, Bhat discloses (see figures 1-12) the noise compensation circuit (figure 9, part noise compensation circuit generated by 940 and 920) comprises an amplification stage (figure 9, part amplification stage generated by 982 and 990). However, Bhat does not expressly disclose a plurality of amplification stages.
Chen teaches (see figures 1-6) the noise compensation circuit (figure 2, part noise compensation circuit generated by 220, 240 and 250) comprises a plurality of amplification stages (figure 2, part plurality of amplification stages generated by 220, 240 and M17).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the noise compensation circuit of Bhat with the plurality of amplification stages features as taught by Chen, because it provides more efficient voltage regulation with quick restore of the output voltage (paragraph [0007]).
Regarding claim 16, claim 10 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 20, claim 10 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Response to Arguments
Applicant’s arguments with respect to claims 1, 11 and 17 have been considered but are moot because the new ground of rejection does not rely on the way the references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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