DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 11, 20: 2, 3, 4, 5, 7, 12, 14, 16, 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bruce et al. U.S. Pub. No. 2022/0392147 in view of Saeed et al. U.S. Pub. No. 2021/0304489.
Re: claims 1 and 11, Bruce teaches
1. (Currently Amended) A graphics processor that is operable to generate a render output by performing a ray tracing process in which rays are traced through a scene to be rendered, (“... a method of operating a graphics processing system including a graphics processor when rendering a frame that represents a view of a scene comprising one or more objects using a ray tracing process.”; Bruce, [0026])
The graphics processing system includes a graphics processor that renders a view of a scene using ray tracing (a graphics processor that is operable to generate a render output by performing a ray tracing process in which rays are traced through a scene to be rendered.
wherein the ray tracing process for a ray involves performing a traversal of at least one ray tracing acceleration data structure to determine geometry that is intersected or potentially intersected by the ray; (“wherein the ray tracing process uses a ray tracing acceleration data structure indicative of the distribution of geometry for the scene to be rendered to determine geometry for the scene that may be intersected by a ray being used for a ray tracing operation... the ray tracing process comprising performing for a plurality of rays a traversal of the ray tracing acceleration data structure to determine, by testing the rays for intersection with the volumes represented by the nodes of the acceleration data structure, geometry for the scene to be rendered that may be intersected by the rays; ”; Bruce, [0027])
The ray tracing process uses a ray acceleration data structure to determine the geometry for the scene that may be intersected by a ray being used for ray tracing. The ray tracing process includes traversal of the acceleration data structure by plural rays to determine, by testing the rays for intersection, geometry for the scene that may be intersected by the rays (the ray tracing process for a ray involves preforming traversal of at least one ray tracing acceleration data structure to determine geometry that is intersected or potentially intersected by the ray).
the graphics processor comprising: a programmable execution unit operable to execute graphics processing programs to perform rendering that includes performing a ray tracing process; (“the programmable execution unit:... executing a graphics processing program to render a frame that represents a view of a scene comprising one or more objects using a ray tracing process... the graphics processor comprising a programmable execution unit operable to execute programs to perform graphics processing operations...”; Bruce, [0025], [0026], [0033])
The programmable execution unit executes a graphics processing program to render a frame using a ray tracing process.
a ray tracing circuit operable to test rays against a ray tracing acceleration data structure for a ray tracing process; (“As shown in Fig. 6, the shader core 61 also includes an intersection testing circuit 74... which is also operable to perform the required ray-primitive testing during the ray tracing acceleration data structure traversals... for rays being processed as part of a ray tracing-based rendering process, in response to messages 75 received from the programmable execution unit 65.”; Bruce, [0385], Fig. 6)
The intersection testing circuit (ray tracing circuit) is operable to perform ray-primitive testing (operable to test rays) during the ray tracing acceleration data structure traversals (against a ray tracing acceleration data structure) for rays being processed as part of a ray tracing-based rendering process (for a ray tracing process).
and a programmable processing unit associated with and in communication with the ray tracing circuit, and configured to execute processing programs to perform processing relating to the operation of the ray tracing circuit, (“The graphics processor (GPU) shader cores 61, 62 are programmable processing units (circuits) that perform processing operations by running small programs for each “item” in an output to be generated such as a render target, e.g., frame.”; Bruce, [0378], Fig. 6)
Fig. 6 illustrates GPU shader cores that are programmable processing units that perform processing operation by running programs for rendering (execute processing programs).
(“Fig. 7 shows in more detail the communication between the intersection testing circuit 74 and the shader cores 61, 62.”; Bruce, [0388], Fig. 7)
Fig. 7 illustrates the communication between the shader cores (programmable processing unit) and the intersection testing circuit (ray tracing circuit).
(“... a method of operating a graphics processing system including a graphics processor when rendering a frame that represents a view of a scene comprising one or more objects using a ray tracing process.”; Bruce, [0026])
The GPU is part of the graphics processing system that performs renders frames representing a scene, using a ray tracing process. Thus, the processing programs are executed to perform processing relating to the operation of the ray tracing circuit.
(“As shown in Fig. 6, each shader core of the graphics processor 60 includes an appropriate programmable execution unit (execution engine) 65 that is operable to execute graphics shader programs for execution threads to perform graphics processing operations.”; Bruce, [0380], Fig. 6)
The shader core (programmable processing unit) includes a programmable execution unit that executes graphics shader programs to perform shader operations.
(“As shown in Fig. 6, the shader core 61 also includes an intersection testing circuit 74, which is in communication with the programmable execution unit 65, and which is operable to perform the required ray-volume testing during the ray tracing acceleration data structure traversals... for rays being processed as part of a ray tracing-based rendering process, in response to messages 75 received from the programmable execution unit 65.”; Bruce, [0385], Fig. 6)
Fig 6 illustrates, for example, shader core 0 that includes an intersection testing circuit 74 (ray tracing circuit), which performs ray-volume testing during ray tracing acceleration data structure traversals, in response to messages received from the programmable execution unit (that is included in the shader core).
Bruce is silent regarding the programmable processing unit is operable to, and configured to, execute programs using an instruction set different than an instruction set used by the programmable execution unit to execute graphics processing programs, however Saeed teaches
wherein the programmable processing unit is operable to, and configured to, execute programs using an instruction set different than an instruction set used by the programmable execution unit to execute graphics processing programs. (“... the technology described herein... uses a dedicated circuit (hardware) for the ray tracing acceleration data structure traversal operation only, but still performs the actual ray intersection determination by means of executing appropriate program instructions using a programmable processing circuit.”; Saeed, [0052])
The programmable processing circuit executes program instructions to determine the actual intersection of any geometry by a ray from the traversal of ray tracing acceleration data structure.
(“... the programmable execution unit:... executing a graphics processing program to render a frame that represents a view of a scene comprising one or more objects using a ray tracing process;”; Saeed, [0025], [0026])
The programmable execution unit executes a graphics processing program to render a frame that represents a view of a scene, using a ray tracing process. Thus, the program instruction sets for the programmable processing circuit and the programmable execution unit are different. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Bruce by adding the feature of the programmable processing unit is operable to, and configured to, execute programs using an instruction set different than an instruction set used by the programmable execution unit to execute graphics processing programs, in order to perform the ray tracing acceleration data traversal data structure more efficiently, thereby facilitating performing ray tracing and improved ray tracing on devices whose processing resources may be more limited, as taught by Saeed ([0050]).
Claim 20 is a medium analogous to the processor of claim 1, is similar in scope and is rejected under the same rationale. Claim 20 has an additional limitation. Re: claim 20, Bruce teaches
20. (Original) A non-transitory computer readable storage medium storing computer software code which when executing on one or more processors performs a method (“The methods in accordance with the technology described herein may be implemented at least partially using software (e.g., computer programs)... the technology described herein provides computer software specifically adapted to carry out the methods herein described when installed on a data processor, a computer program element comprising computer software code portions for performing the methods herein described when the program element is run on a data processor...”; Bruce, [0340])
The software is executed by a processor to perform the method.
(“The technology described herein also extends to a computer software carrier comprising such software... Such a computer software carrier could be a physical storage intermediate such as a ROM chip, CD ROM, RAM, flash memory, or disk...”; Bruce, [0341])
A software carrier, such as physical storage, stores software (storing computer software code).
Re: claim 2, Bruce and Saeed teach
2. (Original) The graphics processor of claim 1, wherein the programmable processing unit comprises a processor that can execute programs to perform processing operations, storage for storing a program or programs for execution by the processor and storage for storing data to be used by the processor when executing a program and/or for storing data that is generated by the processor when executing a program. (“The graphics processor and/or graphics processing system may also comprise, and/or be in communication with, one or more memories and/or memory devices that store the data described herein, and/or the output data generated by the graphics processor, and/or store software (e.g., (shader) programs) for performing the processes described herein.”; Bruce, [0328])
The graphics processor includes memory that stores shader programs for execution (a processor that can execute programs to perform processing operations... storage for storing a program or programs for execution by the processor) and memory that stores data and/or output data generated by the graphics processor (storage for storing data to be used by the processor when executing a program and/or for storing data that is generated when executing a program).
Re: claim 3, Bruce and Saeed teach
3. (Original) The graphics processor of claim 1, wherein the programmable execution unit is operable to cause a program for performing processing relating to the operation of the ray tracing circuit to be loaded into storage of the programmable processing unit. (“... the pooling and subsequent grouping of ray intersection determinations that are to be performed is used to control and select the pre-fetching of “surface processing” shader programs (instructions) to be executed and/or data (data structures), such as graphics textures, to be used, when performing the ray intersection determinations for a given group of ray intersection determinations, e.g., and in an embodiment, into local storage, e.g., a cache or caches, of or accessible to the programmable execution unit. For example, the relevant “surface processing” shader programs (instructions) to be executed and/or data (data structures), such as graphics textures, to be used, for a group of ray intersection determinations may be pre-fetched (pre-loaded), before the threads for the group of ray intersection determinations are generated and issued to perform the ray intersection determinations for the group. ”; Saeed, [0220])
Relevant shader programs to be executed are pre-loaded (the programmable execution unit is operable to cause a program for performing processing relating to the operation of the ray tracing circuit to be loaded into storage of the programmable processing unit) before the threads for the group of ray intersection determinations are generated to perform intersection ray determinations for the group. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Bruce, by adding the feature of the programmable execution unit is operable to cause a program for performing processing relating to the operation of the ray tracing circuit to be loaded into storage of the programmable processing unit in order to perform the ray tracing acceleration data traversal data structure more efficiently, thereby facilitating performing ray tracing and improved ray tracing on devices whose processing resources may be more limited, as taught by Saeed ([0050]).
Re: clam 4, Bruce and Saeed teach
4. (Original) The graphics processor of claim 1, wherein: the programmable execution unit is operable to cause data required for the execution of a program by the programmable processing unit to be loaded into storage of the programmable processing unit. (“The shader core 61 also includes an appropriate load/store unit 76 in communication with the programmable execution unit 65, that is operable, e.g., to load into an appropriate cache, data, etc., to be processed by the programmable execution unit 65, and to write data back to the memory system 68 (for data loads and stores for programs executed in the programmable execution unit). ”; Bruce, [0382], Fig. 6)
The shader core (programmable processing unit) includes a load/store unit in communication with the programmable execution unit, operable to load data into cache (the programmable execution unit is operable to cause data required for the execution of a program by the programmable processing unit to be loaded into storage of the programmable processing unit) to be processed by the programmable execution unit.
Re: claims 5 and 14 (which are rejected under the same rationale), Bruce and Saeed teach
5. (Original) The graphics processor of claim 1, wherein: the programmable execution unit is operable to cause the programmable processing unit to execute a processing program to perform processing relating to the operation of the ray tracing circuit. (“... as shown in Fig. 6, the shader core 61 further comprises a number of thread creators (generators) operable to generate execution threads for execution by the programmable execution unit 65, including... an “intersect” thread creator 73 (which is operable to generate execution threads to perform processing operations when the results of ray tracing acceleration data structure traversals are available from a ray tracing acceleration data structure traversal circuit 74...).”; Saeed, [0325], Fig. 6)
The shader core generates execution threads, such as intersect threads, which when executed by the programmable execution unit, perform operations on the results of the ray tracing acceleration data structure traversals (the programmable execution unit is operable to cause the programmable processing unit to execute a processing program to perform processing relating to the operation of the ray tracing circuit). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Bruce, by adding the feature of the programmable execution unit is operable to cause the programmable processing unit to execute a processing program to perform processing relating to the operation of the ray tracing circuit, in order to perform the ray tracing acceleration data traversal data structure more efficiently, thereby facilitating performing ray tracing and improved ray tracing on devices whose processing resources may be more limited, as taught by Saeed ([0050]).
Re: claims 7 and 16 (which are rejected under the same rationale), Bruce and Saeed teach
7. (Original) The graphics processor of claim 1, wherein: the programmable processing unit is programmable to perform processing relating to ray tracing acceleration data structure traversal operations that are being performed by the ray tracing circuit. (“As shown in Fig. 6, the shader core 61 also include an intersecting circuit 74, which is in communication with the programmable execution unit 65, and which is operable to perform the required ray-volume testing during the ray tracing acceleration data structure traversals... for rays being processed as part of a ray tracing-based rendering process...”; Bruce, [0385], Fig. 6)
Fig.6 illustrates a shader core (programmable processing unit) that includes an intersecting circuit (ray tracing circuit), which performs ray-volume testing during the ray tracing acceleration data structure traversals (the programmable processing unit is programmable to perform processing relating to ray tracing acceleration data structure traversal operations that are being performed by the ray tracing circuit).
Re: claim 12, Bruce and Saeed teach
12. (Original) The method of claim 11, further comprising loading data for performing processing relating to the operation of the ray tracing circuit into storage of the programmable processing unit; (“The graphics processor and/or graphics processing system may also comprise, and/or be in communication with, one or more memories and/or memory devices that store the data described herein, and/or the output data generated by the graphics processor, and/or store software (e.g., (shader) programs) for performing the processes described herein.”; Bruce, [0328])
The graphics processor includes memory that stores shader programs for execution (loading data for performing processing relating to the operation of the ray tracing circuit into storage of the programmable processing unit). Bruce is silent regarding the programmable processing unit then using that data when executing a program to perform processing relating to the operation of the ray tracing circuit, however, Saeed teaches
and the programmable processing unit then using that data when executing a program to perform processing relating to the operation of the ray tracing circuit. (“... as shown in Fig. 8, the ray tracing acceleration data structure traversal circuit 74 includes a multi-level ADS tree cache 93,in which data from ray tracing acceleration data structures can be stored locally to the ray tracing acceleration data structure traversal circuit 74... The results of the ray traversals are then stored in a traversal surface buffer 95, in which ray traversal results can be buffered, before they are returned for further processing to the programmable execution unit.”; Saeed, [0358], [0359], Figs. 6 and 8)
The results of the ray traversal, of the acceleration data structure, are stored in a traversal surface buffer (loading data for performing processing relating to the operation of the ray tracing circuit into storage of the programmable processing circuit).
(“... the results of the ray tracing acceleration data structure traversals are returned to, and processed by, the programmable execution unit of the graphics processor, by generating further execution threads, that then execute an appropriate “surface processing” shader program to perform the geometry intersection determination and any required further processing for the sampling position corresponding to the ray.”; Saeed, [0360])
The results of the ray tracing acceleration data structure traversals are returned to the programmable execution unit, which generates execution threads (executing a program) to process these results (programmable processing unit then using that data when executing a program to perform processing relating to the operation of the ray tracing circuit). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Bruce by adding the feature of the programmable processing unit then using that data when executing a program to perform processing relating to the operation of the ray tracing circuit, in order to perform the ray tracing acceleration data traversal data structure more efficiently, thereby facilitating performing ray tracing and improved ray tracing on devices whose processing resources may be more limited, as taught by Saeed ([0050]).
Re: claim 21, Bruce and Saeed teach
21. (New) The graphics processor of claim 1, wherein the programmable execution unit is separate to and distinct from the programmable processing unit. (“... the technology described herein... uses a dedicated circuit (hardware) for the ray tracing acceleration data structure traversal operation only, but still performs the actual ray intersection determination by means of executing appropriate program instructions using a programmable processing circuit.”; Saeed, [0052])
The programmable processing circuit executes program instructions to determine the actual intersection of any geometry by a ray from the traversal of ray tracing acceleration data structure.
(“The ray-tracing based rendering of a frame that is performed... is triggered and performed by the programmable execution unit of the graphics processor executing a graphics processing program that will cause (and that causes) the programmable execution unit to perform the necessary ray tracing rendering process... a graphics shader program or programs, including a set... of program instructions that when executed will perform the desired ray tracing rendering process, will be issued to the graphics processor and executed by the programmable execution unit.”;”; Saeed, [0071], [0072])
The programmable execution unit performs ray-tracing based rendering by executing graphics shader programs. The programmable processing circuit determines the actual ray intersection of geometry, which is used by the programmable execution unit to perform rendering. Thus, the programmable processing unit and the programmable execution unit are separate and distinct. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Bruce by adding the feature of the programmable execution unit is separate to and distinct from the programmable processing unit, in order to perform the ray tracing acceleration data traversal data structure more efficiently, thereby facilitating performing ray tracing and improved ray tracing on devices whose processing resources may be more limited, as taught by Saeed ([0050]).
Re: claim 22, Bruce and Saeed teach
22. (New) The graphics processor of claim 1, wherein the programmable processing unit has a control flow that is independent of any control flow of the programmable execution unit of the graphics processor. (“... the technology described herein... uses a dedicated circuit (hardware) for the ray tracing acceleration data structure traversal operation only, but still performs the actual ray intersection determination by means of executing appropriate program instructions using a programmable processing circuit.”; Saeed, [0052])
The control flow for the programmable processing unit includes performing the actual ray intersection determination.
(“... the programmable execution unit:... executing a graphics processing program to render a frame that represents a view of a scene comprising one or more objects using a ray tracing process;”; Saeed, [0025], [0026])
The control flow for the programmable execution unit rendering a scene using a ray tracing process. Thus, the control flows for the programmable processing unit and the programmable execution unit are independent. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Bruce by adding the feature of the programmable processing unit has a control flow that is independent of any control flow of the programmable execution unit of the graphics processor, in order to perform the ray tracing acceleration data traversal data structure more efficiently, thereby facilitating performing ray tracing and improved ray tracing on devices whose processing resources may be more limited, as taught by Saeed ([0050]).
Claim(s) 6 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bruce in view of Saeed as applied to claim 11 above, and further in view of Howson et al. U.S. Pub. No. 2017/0309059.
Re: claims 6 and 15 (which are rejected under the same rationale), Bruce and Saeed are silent regarding the programmable execution unit is configured to communicate with the programmable processing unit via the same communications interface that the programmable execution unit uses to communicate with the ray tracing circuit of the graphics processor, however Howson teaches
6. (Original) The graphics processor of claim 1, wherein: the programmable execution unit is configured to communicate with the programmable processing unit via the same communications interface that the programmable execution unit uses to communicate with the ray tracing circuit of the graphics processor. (“The ray tracing unit may be coupled to a Graphics Processing Unit (GPU), wherein the GPU is configured to execute shaders thereby outputting rays to be processed by the ray tracing unit... one or more shaders are executed at the GPU 106. For example, shaders may be executed by the compute engines 116 of the GPU 106”; Howson, [0011], Fig. 1)
Fig. 1 illustrates that the GPU includes compute engines, which execute shaders. The ray tracing circuit is coupled to the GPU, which executes shaders outputting rays to be processed by the ray tracing unit.
(“The computer system comprises a CPU 502, the GPU 106, the ray tracing unit 110, a memory 504 and other devices 506... The components of the computer system can communicate with each other via a communications bus 512.”; Howson, [0099], Fig. 5)
Fig. 5 illustrates a computer system, which includes a communication bus (communications interface), where the GPU, which includes programmable shaders, and the ray tracing unit communicate using the communications bus (programmable execution unit is configured to communicate with the programmable processing unit via the same communications interface that the programmable execution unit uses to communicate with the ray tracing circuit of the graphics processor). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Bruce by adding the feature of the programmable execution unit is configured to communicate with the programmable processing unit via the same communications interface that the programmable execution unit uses to communicate with the ray tracing circuit of the graphics processor, in order to enable efficient communication between the components of the computer system, as taught by Howson ([0099]).
Claim(s) 8, 9, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bruce in view of Saeed as applied to claim 1 and 11 above, and further in view of Rabbani Rankouhi et al. (hereinafter Rabbani).
Re: claim 8, Bruce and Saeed are silent regarding the programmable processing unit has communications interface(s) with the ray tracing circuit to allow it to monitor the performance of the ray tracing circuit when performing ray tracing acceleration data structure traversals, and to provide control information to the ray tracing circuit for the ray tracing circuit to then use when performing ray tracing acceleration data structure traversals, however Rabbani teaches
8. (Original) The graphics processor of claim 1, wherein: the programmable processing unit has communications interface(s) with the ray tracing circuit to allow it to monitor the performance of the ray tracing circuit when performing ray tracing acceleration data structure traversals, and to provide control information to the ray tracing circuit for the ray tracing circuit to then use when performing ray tracing acceleration data structure traversals. (“... programmable shader 16 sends an intersect ray command to ray intersection accelerator (MA) [sic] 190. The intersect ray command may be for a clique-A SIMD group that processes multiple rays, for example. RIA 190 traverses the acceleration data structure to generate intersection results for rays... the primitive test results may also indicate to (MA) [sic] 190 whether or not it should continue traversal for a given ray, e.g., based on whether there is a hit and the type of intersect requested. For a closest hit query, transversal ends when there is a hit. ”; Rabbani, [0120], [0121], Fig. 14A)
The programmable shader (programmable processing unit) sends (communications interface with the ray tracing circuit) a ray command to the ray intersection accelerator (RIA) that processes multiple rays. The RIA traverses the acceleration data structure to generate intersection results. For example, based on whether there is a hit (to allow it to monitor the performance of the ray tracing circuit when performing ray tracing acceleration data structure traversals), traversal ends (provide control information to the ray tracing circuit for the ray tracing circuit to then use when performing ray tracing acceleration data structure traversals). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Bruce by adding the feature of the programmable processing unit has communications interface(s) with the ray tracing circuit to allow it to monitor the performance of the ray tracing circuit when performing ray tracing acceleration data structure traversals, and to provide control information to the ray tracing circuit for the ray tracing circuit to then use when performing ray tracing acceleration data structure traversals, in order to reduce the average latency of primitive testing, as taught by Rabbani ([0122]).
Re: claim 17, Bruce and Saeed are silent regarding the programmable processing unit, when executing the program: monitoring the performance of ray tracing acceleration data structure traversals by the ray tracing circuit; and determining information for then providing to the ray tracing circuit for trying to improve its ray tracing acceleration data structure traversal operation based on the monitoring, however, Rabbani teaches
17. (Original) The method of claim 16, comprising the programmable processing unit, when executing the program: monitoring the performance of ray tracing acceleration data structure traversals by the ray tracing circuit; (“Fig. 14A is a block diagram illustrating an example technique for dynamically forming SIMD groups for primitive testing... programmable shader 160 sends an intersect ray command to ray intersection accelerator (MA) [sic] 190. The intersect ray command may be for a clique-A SIMD group that processes multiple rays, for example. RIA 190 traverses the acceleration data structure to generate intersection results for rays... In the illustrated example, RIA 190 does not actually perform primitive tests once a leaf is reached, but dynamically forms primitive tests SIMD groups 1405... to be executed by programmable shader 160. Programmable shade 160 executes the primitive test SIMD groups (clique-Ts) and may provide primitive tests results to MA [sic] 190... RIA 190 may aggregate test results for a given clique-A and provide the results back to programmable shader 160 when the results are ready or RIA 190 may provide results as they are complete and the clique-T may aggregate the results... the primitive test results may also indicate to (MA) [sic] 190 whether or not it should continue traversal for a given ray, e.g., based on whether there is a hit and the type of intersect requested. For a closest hit query, transversal ends when there is a hit. ”; Rabbani, [0119], [0120], [0121], Fig. 14A)
The programmable shader (programmable processing unit) sends a ray command to the ray intersection accelerator (RIA) (ray tracing circuit) that processes multiple rays. The RIA traverses the acceleration data structure to generate intersection results. For example, based on whether there is a hit (monitoring the performance of the ray tracing acceleration data structure traversals by the ray tracing circuit), traversal ends (provide control information to the ray tracing circuit for the ray tracing circuit to then use when performing ray tracing acceleration data structure traversals).
and determining information for then providing to the ray tracing circuit for trying to improve its ray tracing acceleration data structure traversal operation based on the monitoring. (“Fig. 14A is a block diagram illustrating an example technique for dynamically forming SIMD groups for primitive testing... programmable shader 160 sends an intersect ray command to ray intersection accelerator (MA) [sic] 190. The intersect ray command may be for a clique-A SIMD group that processes multiple rays, for example. RIA 190 traverses the acceleration data structure to generate intersection results for rays... RIA 190 does not actually perform primitive tests once a leaf is reached, but dynamically forms primitive test SMD groups 1405... to be executed by programmable shader 160. Programmable shader 160 executes the primitive test SIMD groups (clique-Ts) and may provide primitive test results to MA [sic] 190... ”; Rabbani, [0119], Fig. 14)
Fig. 14A illustrates that the programmable shader sends an intersect ray command to the RIA 190 (determining information for then providing to the ray tracing circuit). The RIA then traverses the acceleration data structure to generate intersection results. The RIA does not perform primitive tests once a leaf is reached, but forms primitive test SIMD groups to be executed by the programmable shader.
(“... the processor Is configured to group multiple leaves that share the same shader into the same clique-T so that they can be tested together. This may advantageously reduce the average latency of primitive testing.”; Rabbani, [0122])
When a leaf is reached, processor groups multiple leaves that share the same shader into the same clique-T so that they can be tested together. This reduces the average latency of primitive testing (improve its ray tracing acceleration data structure traversal operation based on the monitoring). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Bruce by adding the feature of the programmable processing unit, when executing the program: monitoring the performance of ray tracing acceleration data structure traversals by the ray tracing circuit; and determining information for then providing to the ray tracing circuit for trying to improve its ray tracing acceleration data structure traversal operation based on the monitoring, in order to reduce the average latency of primitive testing, as taught by Rabbani ([0122]).
Re: claims 9 and 18 (which are rejected under the same rationale), Bruce and Saeed are silent regarding the programmable processing unit is programmable to perform processing to generate a ray tracing acceleration data structure, however, Rabbani teaches
9. (Original) The graphics processor of claim 1, wherein: the programmable processing unit is programmable to perform processing to generate a ray tracing acceleration data structure. (“In the illustrated example, programmable shader 160 receives and executes an intersect ray instruction included in a graphics program. The intersect ray instruction may be a single-instruction multiple-data (SIMD) instruction, for example, and may specify multiple rays. In response, programmable shader 160 sends an intersect ray command to MA [sic] 190. The command may include a pointer to a data structure for the ray(s) being processed.”; Rabbani, [0056], Fig. 3A)
The programable shader receives an intersect ray instruction that specifies multiple rays. In response, the programmable shader sends an intersect ray command, which includes a pointer to a data structure for the rays being processed, to the RIA.
(“A common class of ADS is bounding volume hierarchy (BVH) in which surface primitives are enclosed in a hierarchy of geometric proxy volumes (e.g., boxes) that are cheaper to test for intersection. These volumes may be referred to as bounding regions... these structures are constructed once for each distinct mesh in a scene, in the local object space or model space of that object, and rays are transformed from world-space into the local space before traversing the BVH... The ADS build element 215 receives geometry data 210 for a graphics scene and produces an ADS 220. ADS build element 215 may build the ADS from scratch or update a prior ADS... Camera shading element 225 (which may also be referred to as a source shader) produces rays originating at the viewpoint... These rays are processed by ADS traversal element 230.”; Rabbani, [0050], [0052], Fig. 2)
An acceleration data structure is constructed for each mesh in a scene. The ADS build element, of the GPU, receives geometry data for a graphics scene and produces an ADS (the programmable processing unit is programmable to perform processing to generate a ray tracing acceleration data structure). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Bruce by adding the feature of the programmable processing unit is programmable to perform processing to generate a ray tracing acceleration data structure, in order to efficiently implement ray intersection queries by reducing the number of ray-surface intersection tests and thereby accelerate the query process, as taught by Rabbani ([0050]).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bruce in view of Saeed as applied to claim 11 above, and further in view of Ranganathan et al. U.S. Pub. No. 2025/0231769.
Re: clam 13, Bruce and Saeed are silent regarding comprising loading a program for performing processing relating to the operation of the ray tracing circuit into program storage of the programmable processing unit to replace an existing program stored in the program storage of the programmable processing unit;, however, Ranganathan
13. (Original) The method of claim 11, further comprising loading a program for performing processing relating to the operation of the ray tracing circuit into program storage of the programmable processing unit to replace an existing program stored in the program storage of the programmable processing unit; and the programmable processing unit then executing the new program to perform processing relating to the operation of the ray tracing circuit. (“... receiving a command to perform mid-thread preemption of a first group of threads that includes the first parent thread and the first child thread; saving thread state for the first parent thread and the first child thread to the memory device; and replacing the first group of threads with the second group of threads to be executed in place of the first group of threads.”; Ranganathan, [0494])
A first group of threads is preempted and the thread state is saved. The first group of threads is then replaced with the second group of threads (loading a program for performing processing relating to the operation of the ray tracing circuit into program storage of the programmable processing unit to replace an existing program stored in the program storage of the programmable processing unit). Then, the second set of threads is executed (programmable processing unit then executing the new program to perform processing relating to the operation of the ray tracing circuit). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Bruce by adding the feature of comprising loading a program for performing processing relating to the operation of the ray tracing circuit into program storage of the programmable processing unit to replace an existing program stored in the program storage of the programmable processing unit; and the programmable processing unit then executing the new program to perform processing relating to the operation of the ray tracing circuit, in order to save the thread state without requiring intervention by the graphics driver software, as taught by Ranganathan ([0063]).
Response to Arguments
Applicant’s arguments, see Amendment/Request for Reconsideration-After Non-Final Rejection, filed 3/03/2026, with respect to Objections to the Specification have been fully considered and are persuasive. The Objections to the Specification of the previous Office Action have been withdrawn.
Applicant's arguments filed 3/03/2026 have been fully considered but they are not persuasive. Applicant argues:
“It is advantageous not only that the programmable processing unit is provided in addition to the programmable execution unit, but moreover that each are therefore able to be configured as appropriate for their particular functions. The PPU may thus be specifically designed and configured for the particular operations it is intended to carry out, for example monitoring the operation of the ray tracing unit and/or generating acceleration data structures - it thus may, for example, have a tailored, specialized instruction set, as explained in paragraphs 0059 and 0060 of the application. Figure 6 of the present application shows the programmable processing unit (PPU) 77, in communication with the ray tracing unit 85. Figure 6 of Bruce similarly shows a Shader Core, including a number of the same components as are shown in Figure 6 of the present application, but notably, as is clearly visible by comparing the respective Figure 6 of each of the two applications, the Shader Core of Bruce does not contain any PPU. Thus, for at least this reason, independent claims 1, 11 and 20 are not anticipated by Bruce.”
Examiner disagrees. Regarding Applicant’s argument that Bruce does not contain any PPU (programmable processing unit), Bruce illustrates in Fig. 6, GPU shader cores that are programmable processing units that perform processing operation by running programs for rendering (execute processing programs). (Bruce, [0378], Fig. 6).
Applicant's arguments filed 3/03/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claims 1 and 11 as amended now recite that "the programmable processing unit is operable to, and configured to, execute programs using an instruction set different than an instruction set used by the programmable execution unit to execute graphics processing programs ". This captures the way in which the programmable processing unit is specialized for its own specific operations (which relate to operation of the ray tracing unit), in that it has its own, different instruction set compared to the instruction set of the programmable execution unit.
The Action considers a "Shader Core" as shown in Figure 6 of Bruce to provide the claimed "programmable processing unit". However, in Bruce, the Shader Core (which the Examiner considers as the claimed "programmable processing unit") comprises within it the "Execution engine" 65 (i.e. the programmable execution unit, as described in [0380]). Since the execution engine is within the shader core, the shader core cannot be configured to execute programs "using an instruction set different than an instruction set used by" the execution unit. Bruce therefore fails to provide a programmable processing unit which is "operable to, and configured to, execute programs using an instruction set different than an instruction set used by the programmable execution unit to execute graphics processing programs", as recited in claims 1 and 11. For this additional reason, it is respectfully submitted claims 1 and 11 are not anticipated by Bruce. It is further respectfully submitted that claims 2, 3, 7, and 16, dependent from claims 1 and 11, are likewise not anticipated. Reconsideration of this rejection is respectfully requested.
Examiner disagrees. Saeed teaches this amended limitation. Saeed teaches that the programmable processing circuit executes program instructions to determine the actual intersection of any geometry by a ray from the traversal of ray tracing acceleration data structure. (Saeed, [0052]). The programmable execution unit executes a graphics processing program to render a frame that represents a view of a scene, using a ray tracing process. Thus, the program instruction sets for the programmable processing circuit and the programmable execution unit are different. (Saeed, [0025], [0026]). Claims 1, 11 and claims 2, 3, 7 and 16 have been rejected. Please see the corresponding rejections.
Applicant's arguments filed 3/03/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claims 3, 5, 12, and 14 all depend from independent claims 1 or 11 and include all the features thereof. It is respectfully submitted that Saeed, asserted as teaching the various features of claims 3, 5, 12, and 14, does not lead one of average skill in the art to provide either a programmable processing unit associated with and in communication with the ray tracing circuit, and configured to execute processing programs to perform processing relating to the operation of the ray tracing circuit or a unit that is operable to, and configured to, execute programs using an instruction set different than an instruction set used by the programmable execution unit to execute graphics processing programs. Thus, one of average skill would not be led by the combined teachings of the references to find the claimed subject matter obvious. Reconsideration of this rejection is therefore respectfully requested.”
Examiner disagrees. Claims 1, 11 and claims 3, 5, 12, and 14 have been rejected. Please see the corresponding rejections.
Applicant's arguments filed 3/03/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claims 6 and 15 depend from independent claims 1 or 11 and include all the features thereof. It is respectfully asserted that these claims are patentable over the applied references for at least the reason that they depend from independent claims 1 or as well as for the features that they add. Howson, asserted as teaching the various features of claims 6 and 15 missing from Bruce, even when combined with Bruce, does not lead one of average skill in the art to the features discussed above with respect to claims 1 and 11. Thus, one of average skill would not be led by the combined teachings of the references to find the claimed subject matter obvious. Reconsideration of this rejection is therefore respectfully requested.”
Examiner disagrees. Claims 1, 11 and claims 6 and 15 have been rejected. Please see the corresponding rejections.
Applicant's arguments filed 3/03/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claims 8-9 and 17-18 all depend from independent claims 1 or 11 and include all the features thereof. It is respectfully asserted that these claims are patentable over the applied references for at least the reason that they depend from independent claims 1 or as well as for the features that they add. Rabbani, asserted as teaching the various features of claims 8-9 and 17-18 missing from Bruce, even when combined with Bruce, does not lead one of average skill in the art to the features discussed above with respect to claims 1 and 11, and thus by their dependency thereon, claims 8-9 and 17-18. Thus, one of average skill would not be led by the combined teachings of the references to find the claimed subject matter obvious. Reconsideration of this rejection is therefore respectfully requested.”
Examiner disagrees. Claims 1, 11 and claims 8-9, 17 and 18 have been rejected. Please see the corresponding rejections.
Applicant's arguments filed 3/03/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claim 13 depends from independent claim 11 and includes all the features thereof. It is respectfully asserted that claim 13 is patentable over the applied references for at least the reason that it depends from independent claim 1 as well as for the features that it adds add. Ranganathan, alone or in combination with Bruce, does not lead one of average skill in the art to the features discussed above with respect to claim 11. Thus, one of average skill would not be led by the combined teachings of the references to find the claimed subject matter obvious. Reconsideration of this rejection is therefore respectfully requested.”
Examiner disagrees. Claims 1, 11 and claim 13 have been rejected. Please see the corresponding rejections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONNA J RICKS whose telephone number is (571)270-7532. The examiner can normally be reached on M-F 7:30am-5pm EST (alternate Fridays off).
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/Donna J. Ricks/Examiner, Art Unit 2618
/DEVONA E FAULK/Supervisory Patent Examiner, Art Unit 2618
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