Prosecution Insights
Last updated: October 02, 2026
Application No. 18/609,742

PACKAGE STRUCTURE AND PACKAGING METHOD

Non-Final OA §103
Filed
Mar 19, 2024
Priority
Apr 17, 2023 — CN 202310414228.4
Examiner
BENTON, CHLOE ELAINE
Art Unit
Tech Center
Assignee
Jcet Group Co. Ltd.
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-60.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
Avg Prosecution
21 currently pending
Career history
13
Total Applications
across all art units
This examiner has no resolved cases yet (career too new); statute-level performance unavailable. The Grant Probability card shows Tech Center averages instead.

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-7 in the reply filed on 6/30/2026 is acknowledged. Claims 8-9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/30/2026. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Method for Reducing Contamination and Cracking in Cover Plates for Semiconductor Packages. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Tu et al. (US20110024861A1) in view of Huang et al. (CN101192545A). Regarding Claim 1: Tu discloses a packaging method (Figs. 1 and 4B), comprising: providing a substrate (element 11, paragraph 40), wherein a sensor chip (element 12) electrically connected to the substrate is arranged (paragraph 42) on a surface of the substrate (element 111), a light-receiving region (element 123) is arranged on a surface, facing away from the substrate, of the sensor chip (paragraph 42); arranging a transparent cover plate (element 13) on the sensor chip (element 12), wherein the transparent cover plate covers the light-receiving region (paragraph 43), and a separator film (element 20) is arranged on a side, facing away from the sensor chip, of the transparent cover plate (paragraph 44); performing molding (S40) to form a molding layer (element 40), wherein the molding layer wraps the sensor chip, the transparent cover plate, and the separator film (S50, paragraph 46); Tu, however, does not explicitly disclose where the molding layer is thinned to form a molding body nor where the separator film is removed to expose the transparent cover plate. Huang discloses an analogous packaging method (Figs. 5A-F), comprising thinning the molding layer (element 54) from a side, facing away from the substrate (element 51), of the molding layer to form a molding body, wherein the molding body exposes the separator film (element 56, paragraphs 81-83); and removing the separator film to expose the transparent cover plate (element 55, paragraph 83). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Tu further in view of Huang to explicitly include the thinning of the molding layer to form a molding body – wherein the separator is exposed – and removing the separator film to expose the transparent cover plate because both are directed to analogous packaging methods and doing so protects the cover plate and chip while also enhancing the reliability of the packages (Huang, paragraphs 5 and 11-12). Regarding Claim 2: The combination of Tu and Huang disclose a packaging method according to claim 1, but Tu does not explicitly disclose wherein prior to arranging the transparent cover plate on the sensor chip, the method comprises of forming the separator film on a surface of the transparent cover plate. Huang discloses an analogous packaging method (Figs. 6A-F), wherein prior to arranging the transparent cover (element 65) on the sensor chip (element 60), the separator film (element 66) is formed on a surface (element 651) of the transparent cover plate (paragraph 88), and wherein arranging the transparent cover plate on the sensor chip comprises attaching a surface, facing away from the separator film (element 652), of the transparent cover plate onto the sensor chip (paragraph 88). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Tu further in view of Huang to explicitly include where the separator film is formed on the surface of the transparent cover plate – prior to the arranging of the cover plate on the sensor chip – because both are directed to analogous packaging methods and doing so protects the cover plate while also enhancing the reliability of the packages (Huang, paragraphs 5 and 11-12). Regarding Claim 3: The combination of Tu and Huang disclose a packaging method according to claim 1, wherein Tu further discloses arranging the transparent cover plate on the sensor chip comprises: arranging the transparent cover plate (Fig. 3A element 13) on the sensor chip (element 12, paragraphs 42-43); and attaching the separator film (element 20) onto a surface, facing away from the sensor chip, of the transparent cover plate (S20, paragraph 44). Regarding Claim 4: The combination of Tu and Huang disclose a packaging method according to claim 1, wherein Tu further discloses arranging the transparent cover plate on the sensor chip comprises: securing the transparent cover plate (Fig. 3A, element 13) onto the sensor chip (element 12) by an adhesive layer (element 14), wherein the adhesive layer is a transparent layer (paragraph 43). Regarding Claim 6: The combination of Tu and Huang disclose a packaging method according to claim 1, but Tu does not explicitly disclose wherein the upper surface of the molding body is greater than a predetermined distance from the separator film. Huang, however, discloses an analogous packaging method (Figs. 5A-F), wherein when molding to form the molding body (paragraph 81), a distance from the separator film (element 56) to an upper surface of the molding layer (element 54) is greater than a predetermined value (paragraph 82). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Tu further in view of Huang to explicitly include when forming the molding body, a distance from the separator film to an upper surface of the molding layer is greater than a predetermined value because both are directed to analogous packaging methods and doing so further protects the cover plate while also enhancing the reliability of the packaging process (Huang, paragraphs 5 and 11-12). Regarding Claim 7: The combination of Tu and Huang disclose a packaging method according to claim 1, wherein Tu further discloses a conductive pad (Fig. 2 element 124) is further arranged on the surface, facing away from the substrate (element 122), of the sensor chip (element 12), and the sensor chip is arranged on the surface of the substrate (element 11) by: attaching the sensor chip onto the surface of the substrate (paragraph 42); and electrically connecting (paragraph 42) the conductive pad to the substrate by a conductive wire (element 15). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Tu et al. (US20110024861A1) in view of Huang et al. (CN101192545A) as applied to claim 1 above, and further in view of Yoshida et al. (CN101161411B). Regarding Claim 5: The combination of Tu and Huang disclose a packaging method according to claim 1, but Tu does not explicitly disclose thinning or grinding the molding layer during the molding process. Huang, however, discloses an analogous packaging method (Figs. 5A-F), wherein thinning the molding layer (element 54) from a side, facing away from the substrate (element 51), of the molding layer comprises grinding the molding layer to thin the molding layer having a predetermined thickness (paragraph 82). But Huang does not explicitly teach coarse or fine grinding. Yoshida, however, discloses an analogous grinding method for semiconductor packages (paragraphs 9-10), wherein the first step includes coarse grinding to thin the layer to a predetermined thickness; and then fine grinding the layer (paragraphs 7-9). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Tu and Huang further in view of Yoshida to explicitly include a thinning process – during the thinning of the molder layer – wherein the molding layer is coarse grinded to a predetermined thickness, then fine grinded until the separator film is exposed because both are directed to analogous thinning and packaging processes as doing so protects the integrity of the chip during the thinning process (Yoshida, paragraphs 2-3). Citation of Pertinent Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Xiao et al. (CN 117613107 A), . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chloë E Benton whose telephone number is (571)272-9976. The examiner can normally be reached Monday-Thursday: 8am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899 /Chloë E Benton/Examiner, Art Unit 2899
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Prosecution Timeline

Mar 19, 2024
Application Filed
Aug 11, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allowance rate.

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