Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-20 set forth in the amendment submitted 12/02/2025 form the basis of the present examination.
Response to Arguments
Applicant’s arguments, see remarks page 7-9, filed 12/02/2025, with respect to the rejection(s) of Claim(s) 1-3, 5-6, 10-17 and 20 under 35 U.S.C. 102 (a) (1) as being anticipated by Mitsuhashi in the US Patent Application Publication Number US 20080116899 A1 and the rejection of Claim(s) 4, 7-9 and 18-19 under 35 U.S.C. 103 as being unpatentable over Mitsuhashi ‘899 A1 in view of Webb et al. (Hereinafter, “Webb”) in the US Patent Application Publication Number US 20120176174 A1 have been fully considered as follows:
Applicant’s Argument:
Applicant argues on page 8, of the remarks, filed on 12/02/2025, regarding the rejection(s) of Claim(s) 1-3, 5-6, 10-17 and 20 under 35 U.S.C. 102 (a) (1) as being anticipated by Mitsuhashi in the US Patent Application Publication Number US 20080116899 A1, that “Mitsuhashi simply does not describe "a calculator that is configured to: calculate a final width value of the first pulse signal based on the first measurement value; determine whether an abnormality is present in one or more of the channels at least in part by comparing the final width value and an initial width value for the first pulse signal; and output a test result indicating whether the abnormality is present in the one or more of the channels", as recited by amended claim 1.
For at least this reason, amended independent claim 1 patentably distinguishes over Mitsuhashi and withdrawal of the rejections under 35 U.S.C. § 102 of independent claim 1, and each claim that depends therefrom, is respectfully requested. (Remarks-Page 8).”
Examiner Response:
Applicant’s arguments, see remarks page 8, of the remarks, filed on 12/02/2025, regarding the rejection(s) of Claim(s) 1-3, 5-6, 10-17 and 20 under 35 U.S.C. 102 (a) (1) as being anticipated by Mitsuhashi in the US Patent Application Publication Number US 20080116899 A1, as applied to the Non-Final office Action mailed on 10/01//2025 have been fully considered and is persuasive. Therefore, the rejection of independent claim 1 has been withdrawn. However, applicant has amended the claim 1, and added the limitation, “calculate a final width value of the first pulse signal based on the first measurement value; determine whether an abnormality is present in one or more of the channels at least in part by comparing the final width value and an initial width value for the first pulse signal; and output a test result indicating whether the abnormality is present in the one or more of the channels.” which necessitates a new ground of rejection. Therefore, the rejection of Claim(s) 1-3, 5-6, 10-17 and 20 under 35 U.S.C. 102 (a) (1) as being anticipated by Mitsuhashi in the US Patent Application Publication Number US 20080116899 A1, as applied to the Non-Final office Action mailed on 10/01//2025 has been withdrawn. TOMITAKA MAKOTO (Hereinafter, “Tomitaka”) in the Patent application Publication Number JP2011133454A (Publication Date 2011-07-07). is applied to meet at least the amended limitation of claim 1 and therefore Claim 1 is now rejected under 35 U.S.C. 103 as being unpatentable over Mitsuhashi in the US Patent Application Publication Number US 20080116899 A1 in view of TOMITAKA MAKOTO (Hereinafter, “Tomitaka”) in the Patent application Publication Number JP2011133454A (Publication Date 2011-07-07), as set forth below. Applicant’s argument is moot in view of newly applied combination of references. See the rejection set forth below.
Applicant’s Argument:
Applicant argues on page 9 of the remarks, filed on 12/02/2025, regarding the rejection(s) of Claim(s) 1-3, 5-6, 10-17 and 20 under 35 U.S.C. 102 (a) (1) as being anticipated by Mitsuhashi in the US Patent Application Publication Number US 20080116899 A1, as applied to the Non-Final office Action mailed on 10/01//2025 and the rejection of Claim(s) 4, 7-9 and 18-19 under 35 U.S.C. 103 as being unpatentable over Mitsuhashi ‘899 A1 in view of Webb et al. (Hereinafter, “Webb”) in the US Patent Application Publication Number US 20120176174 A1, that, “As amended, independent claim 13 recites, in part, "a calculator that is configured to: calculate a final width value of the first pulse signal based on the first measurement value; determine whether an abnormality is present in one or more of the plurality of channels at least in part by comparing the final width value and an initial width value for the first pulse signal; and output a test result indicating whether the abnormality is present in the one or more of the plurality of channels."
As amended, independent claim 20 recites, in part, "determine whether an abnormality is present in one or more of the channels at least in part by comparing the weighted average value of the values of the widths and an initial width value for the test signal; and output a test result indicating whether the abnormality is present in the one or more of the channels."
As should be appreciated from the foregoing discussion of independent claim 1, independent claims 13 and 20 also patentably distinguish over Mitsuhashi.
Furthermore, independent claim 20 recites determination and use of a weighted average. Because the weighted average value reflects the statistical frequency of the pulse-width distribution, it can output the test result with higher accuracy. Therefore, this feature cannot be readily derived from Mitsuhashi, which merely discloses maximum, minimum, and average values. For at least this second reason, independent claim 20 patentably distinguishes over Mitsuhashi.
Accordingly, withdrawal of the rejections under 35 U.S.C. § 102 of independent claims 13 and 20, and each claim that depends therefrom, is respectfully requested (Remarks-Page 9).”
Examiner Response:
Applicant’s arguments, see remarks page 9, of the remarks, filed on 12/02/2025, regarding the rejection of Claim(s) 1-3, 5-6, 10-17 and 20 under 35 U.S.C. 102 (a) (1) as being anticipated by Mitsuhashi in the US Patent Application Publication Number US 20080116899 A1, as applied to the Non-Final office Action mailed on 10/01//2025 have been fully considered and is persuasive. Therefore, the rejection of independent claim 13 and 20 has been withdrawn. However, applicant has amended the claim 13, and added the limitation, “calculate a final width value of the first pulse signal based on the first measurement value; determine whether an abnormality is present in one or more of the channels at least in part by comparing the final width value and an initial width value for the first pulse signal; and output a test result corresponding value indicating whether the abnormality is present in the one or more of the channels.” And applicant has amended the claim 20, and added the limitation, “determine whether an abnormality is present in one or more of the channels at least in part by comparing the weighted average value of the values of the widths and an initial width value for the test signal; and output a test result indicating whether the abnormality is present in the one or more of the channels.” which necessitates a new ground of rejection. Therefore, the rejection of Claim(s) 1-3, 5-6, 10-17 and 20 under 35 U.S.C. 102 (a) (1) as being anticipated by Mitsuhashi in the US Patent Application Publication Number US 20080116899 A1, as applied to the Non-Final office Action mailed on 10/01//2025 has been withdrawn. TOMITAKA MAKOTO (Hereinafter, “Tomitaka”) in the Patent application Publication Number JP2011133454A (Publication Date 2011-07-07). is applied to meet at least the amended limitation of claim 13 and 20 and therefore Claims 13 and 20 is now rejected under 35 U.S.C. 103 as being unpatentable over Mitsuhashi in the US Patent Application Publication Number US 20080116899 A1 in view of TOMITAKA MAKOTO (Hereinafter, “Tomitaka”) in the Patent application Publication Number JP2011133454A (Publication Date 2011-07-07), as set forth below. Dependent claims 2-3, 5-6, 10-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuhashi in the US Patent Application Publication Number US 20080116899 A1 in view of TOMITAKA MAKOTO (Hereinafter, “Tomitaka”) in the Patent application Publication Number JP2011133454A (Publication Date 2011-07-07) and dependent Claim(s) 4, 7-9 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuhashi ‘899 A1 in view of Tomitaka ‘454A, as applied to claims 1 and 13 above, and further in view of Webb et al. (Hereinafter, “Webb”) in the US Patent Application Publication Number US 20120176174 A1, as set forth below. Applicant’s argument is moot in view of newly applied combination of references. See the rejection set forth below. See the rejection set forth below.
For expedite prosecution Applicant is invited to call to discuss the present rejection also if any further clarification needed and to discuss any possible amendment to overcome the references to make the claims allowable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-6, 10-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuhashi in the US Patent Application Publication Number US 20080116899 A1 in view of TOMITAKA MAKOTO (Hereinafter, “Tomitaka”) in the Patent application Publication Number JP2011133454A (Publication Date 2011-07-07).
Regarding claim 1, Mitsuhashi teaches a test device for testing a semiconductor (A test apparatus that tests a device under test such as a semiconductor circuit and a test module that is provided in the test apparatus; Paragraph [0002] Line 2-5; FIG. 1 shows an example of configuration of a test apparatus 100; Paragraph [0011] Line 1-2; FIG. 2 shows an example of configuration of a circuit provided on a test head 120; Paragraph [0012] Line 1-2), the test device [100] in Figure 1 comprising:
a pulse signal generator [10] in Figure 2 (signal provision section 10 as the pulse signal generator) that is configured to generate a first pulse signal (signal-under-test as the first pulse signal) (The test head 120 includes a signal provision section 10, a measurement circuit 12 and an operation section 122. The signal provision section 10 generates a test signal to test the device under test 200 and provides the same to the device under test 200. For example, the signal provision section 10 may provide a test pattern signal having a predetermined logic pattern signal and a source power; Paragraph [0022] Line 1-7) and transmit the first pulse signal through channels (A measurement circuit 12 measures the output signal from the device under test 200. The measurement circuit 12 has a plurality of measurement channels. For example, the measurement circuit 12 may have a plurality of measurement channels each of which measures the output signal from the device under test 200; Paragraph [0023] Line 1-6; Each of the circuit for each channels 20 has an input section 26. The input section 26 receives output signals outputted from the corresponding device under test 200 or the output pins of the corresponding device under test 200. The input section 26 inputs the received output signal to the circuit for each channel 20 as a signal-under-test; Paragraph [0027] Line 1-8);
a sampler [40+84+50+22] that is configured to receive the first pulse signal [signal-under-test] through the channels [20] (The periodic pulse generating section 40 generates a periodic clock having a pulse width corresponding to one period of the signal-under-test in response to a sample clock which designates the timing at which the signal-under-test is sampled. An example of operation of the periodic pulse generating section 40 will be described later with reference to FIG. 4. That is, the periodic pulse generating section 40 outputs each period in a cycle of the signal-under-test designated by the sample clock, respectively as the amount of time indicated by the pulse width; Paragraph [0028] Line 1-10) and conduct a sampling process on the first pulse signal, based on a second pulse signal (a sample clock having a predetermined period as the second pulse signal) (The sample clock generating section 84 generates a sample clock having a predetermined period and provides the same to the periodic pulse generating section 40 and the AD converting section 22; Paragraph [0033] Line 6-10; The sample clock generating section 84 may generate a sample clock having the pulse width larger than three periods of the signal-under-test, for example; Paragraph [0069] Line 1-3);
a width analyzer [82] (the pulse width calculating section 82 as the width analyzer) (The data processing section 80 according to the present embodiment includes a pulse width calculating section 82; Paragraph [0033] Line 1-3) that is configured to measure a first width of the first pulse signal and generate a first measurement value (output from the width analyzer 82), based on a result of the sampling process (The pulse width calculating section 82 calculates a digital pulse width indicative of the width of the corresponding periodic pulse based on the digital voltage value outputted from each of the circuit for each channels 20; Paragraph [0034] Line 1-4; That is, the converting section 50 converts the value on the to axis to the value on the voltage axis and inputs the same to the AD converter 22 in order to detect the value for a period of a predetermined cycle of the signal-under-test by the AD converter 22. Then, the pulse width calculating section 82 converts the digital value on the voltage axis outputted by the AD converter 22 to the digital value (digital voltage value) on the time axis; Paragraph [0035] Line 1-8); and
a calculator [122] (the operation section as the calculator) (The test head 120 includes a signal provision section 10, a measurement circuit 12 and an operation section 122; Paragraph [0022] Line 1-2) that is configured to output a test result corresponding to each of the channels [20] of the test device, based on the first measurement value (The operation section 122 may calculate the maximum value and the minimum value of the digital pulse width calculated by the pulse width calculating section 82. Additionally, the operation section 122 may further calculate the average value of the digital pulse width calculated by the pulse width calculating section 82; Paragraph [0042] Line 1-6).
Mitsuhashi fails to teach that calculate a final width value of the first pulse signal based on the first measurement value; determine whether an abnormality is present in one or more of the channels at least in part by comparing the final width value and an initial width value for the first pulse signal; and output a test result indicating whether the abnormality is present in the one or more of the channels.
Tomitaka teaches an abnormality determination method for a semiconductor radiation detector and a semiconductor radiation detector using the same (Paragraph [0001] Line 1), wherein
calculate a final width value of the first pulse signal based on the first measurement value (Since the count value becomes smoother than normal due to an increase in background noise, when the parameter α is increased and the count rate Ncb between Vc and Vb becomes equal to or greater than the pulse width determination coefficient rate NW, the test pulse width Wx becomes the test pulse. The upper limit value WxH of the width variation allowable range is exceeded and it is determined as abnormal. Then, in the case of an abnormality caused by this background noise increase, if the bias monitoring voltage Vx is changed from Vini = 15v to V0 = 0V, a curve like abnormality 2 in FIG. 11 is drawn; Paragraph [0083] Line 1-6; test pulse width as the final width value);
determine whether an abnormality is present in one or more of the channels (a plurality of bias monitoring voltages Vx as the plurality of channels) (The abnormality determination starts from the bias monitoring voltage initial value Vini (for example, Vini = 15 V), the bias monitoring voltage Vx is lowered from the bias monitoring voltage initial value Vini, and the same abnormality determination is performed with a plurality of bias monitoring voltages Vx, and the bias The process ends with the final monitoring voltage value V0 (for example, V0 = 0V) (FIG. 10); paragraph [0077] Line 1-4) at least in part by comparing the final width value (test pulse width as the final width) and an initial width value (lower limit value as the initial value) for the first pulse signal ([0087] Although the abnormality determination is performed while the bias monitoring voltage Vx is decreased, the abnormality determination may be performed while the bias monitoring voltage Vx is increased from the bias monitoring voltage initial value Vini = 0V. Further, in the above abnormality determination, the abnormality determination of the test pulse width Wx is performed while increasing the parameter α. However, the parameter α is decreased and the count rate Ncb becomes less than or less than the reference coefficient rate NW for pulse width determination. In this case, the test pulse width Wx may be determined to determine abnormality; Paragraph [0087] Line 1-7; Here, information (2) of the test pulse width determination reference coefficient rate NW1 at the bias monitoring voltage Vx1 is read from the memory 44. In this state, the count rate Ncb1 between Vc and Vb is measured while increasing the parameter α from 0. When the count rate Ncb1 becomes equal to or greater than the pulse width determination reference coefficient rate NW1, the test pulse width Wx1 is set to Wx1 = It is determined as 2α (measurement voltage width). (For example, the parameter α when the count rate Ncb1 = 50 cps> NW1 = 48 cps when the maximum peak value voltage Erx1 = 6 V referred from the bias monitoring voltage Vx1 = 10 V and the initial value α = 0.01 is increased to α = 0. When the voltage is .2 V, the test pulse width Wx1 of the bias monitoring voltage Vx1 = 10 V is set to Wx1 = 0.4 V.) By using this test pulse width Wx1, the bias monitoring stored in the memory 44 as shown in FIG. Referring to information (3) of allowable pulse width allowable range lower limit value WxL1 and allowable pulse width allowable range value WxH1 at voltage Vx1, it is determined whether or not it is within the allowable range of test pulse width (WxL1 <Wx1 <WxH1). When it deviates, it determines with it being abnormal; Paragraph [0076] Line 1-12); and
output a test result indicating whether the abnormality is present in the one or more of the channels (The signal processing unit 18 includes a count rate calculation unit 1, an abnormality determination unit 2, and a test pulse signal control unit 3. The signal processing unit 18 displays and stores a memory 44 that stores a reference value for abnormality determination and an output instruction value. Connected to a monitor / external storage device 45; Paragraph [0021] Line 1-4; The signal processing unit 18 outputs the abnormality determination result of the semiconductor sensor 11 from the abnormality determination unit 2 and the count rate calculation result of the count rate calculation unit 1 to the monitor / external storage device 45 as output instruction values; Paragraph [0041] Line 1-4). The purpose of doing so is to isolate the abnormal state by monitoring the change in the test pulse width and to widen the test pulse width, to provide a function of removing noise transients, an abnormality determination function at the time of disconnection, a data bidirectional communication function, and the like as and to check the soundness in more detail, to provide a function of downscaling the output instruction value when determining abnormality, to allow data download at any time for the purpose of data analysis to have bidirectional communication that can reflect each abnormality determination result.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Mitsuhashi in view of Tomitaka, because Tomitaka teaches to calculate a final width value of the first pulse signal based on the first measurement value and to determine whether an abnormality is present isolates the abnormal state by monitoring the change in the test pulse width and to widen the test pulse width (Paragraph [0085]), provides a function of removing noise transients, an abnormality determination function at the time of disconnection, a data bidirectional communication function, and the like as (paragraph [0088]) and checks the soundness in more detail (Paragraph [0090]), provides a function of downscaling the output instruction value when determining abnormality (Paragraph [0041]), allows data download at any time for the purpose of data analysis to have bidirectional communication that can reflect each abnormality determination result (paragraph [0042]).
Regarding claim 2, Mitsuhashi teaches a test device,
wherein the test device is configured to generate the first pulse signal (signal-under-test as the first pulse signal) and the second pulse signal (a sample clock having a predetermined period as the second pulse signal) independently (Claim 1: A test apparatus that tests a device under test, comprising: a signal provision section that provides a test signal to a device under test; an input section that inputs the output signal outputted from the device under test in response to the test signal as a signal-under-test; a periodic pulse generating section that generates a periodic pulse having a pulse width corresponding to one cycle of the signal-under-test; signal provision section 10 generates first pulse signal and sample clock generating section 84 generates second pulse signal).
Regarding claim 3, Mitsuhashi teaches a test device,
wherein the width analyzer [82] is further configured to measure a plurality of widths of the first pulse signal and generate a plurality of measurement values, based on the result of the sampling process (The pulse width calculating section 82 calculates a digital pulse width indicative of the width of the corresponding periodic pulse based on the digital voltage value outputted from each of the circuit for each channels 20; Paragraph [0034] Line 1-4; The pulse width calculating section 82generates plurality of pulse width for each channel; the adjusting section 86 sets the conversion parameter to the plurality of adjusting clock in the pulse width calculating section 82 such that if the adjusting clocks are inputted to the input section 26, the digital voltage value measured by the AD converter 22 is converted to the digital pulse width corresponding to one period of the adjusting clock in the pulse width calculating section 82; Paragraph [0039] Line 1-7; Paragraph 35-37 explains the generation of a plurality of measurement values, based on the result of the sampling process); and
wherein the calculator [122] is further configured to calculate an average value of the plurality of widths of the first pulse signal, based on the plurality of measurement values, and output the average value as the test result (The operation section 122 may calculate the maximum value and the minimum value of the digital pulse width calculated by the pulse width calculating section 82. Additionally, the operation section 122 may further calculate the average value of the digital pulse width calculated by the pulse width calculating section 82; Paragraph [0042] Line 1-6).
Regarding claim 5, Mitsuhashi teaches a test device,
wherein the sampler is further configured to convert the first pulse signal into digital data based on the sampling process (The sample clock generating section 84 generates a sample clock having a predetermined period and provides the same to the periodic pulse generating section 40 and the AD converting section 22; Paragraph [0033] Line 6-10; The AD converter 22 converts the analog signal outputted by the converting section 50 to a digital voltage value. That is, the AD converter 22 outputs the digital voltage value corresponding to the value for each period in the cycle of the signal-under-test designated by the sample clock, respectively. The AD converter 22 may convert the analog voltage at the timing of the provided sample clock to a digital voltage value, and output the same; Paragraph [0030] Line 1-8).
Regarding claim 6, Mitsuhashi teaches a test device,
wherein the width analyzer [82] is further configured to measure a plurality of widths of the first pulse signal and generate a plurality of measurement values, based on the result of the sampling process (The pulse width calculating section 82 calculates a digital pulse width indicative of the width of the corresponding periodic pulse based on the digital voltage value outputted from each of the circuit for each channels 20; Paragraph [0034] Line 1-4; The pulse width calculating section 82generates plurality of pulse width for each channel; the adjusting section 86 sets the conversion parameter to the plurality of adjusting clock in the pulse width calculating section 82 such that if the adjusting clocks are inputted to the input section 26, the digital voltage value measured by the AD converter 22 is converted to the digital pulse width corresponding to one period of the adjusting clock in the pulse width calculating section 82; Paragraph [0039] Line 1-7; Paragraph 35-37 explains the generation of a plurality of measurement values, based on the result of the sampling process), and
wherein the width analyzer [82] comprises a detector that is configured to generate a detection signal when a corresponding measurement value to the detector among the plurality of measurement values is detected, based on the digital data (The pulse width calculating section 82 may use a conversion parameter to convert each digital value on the voltage axis (digital voltage value) to the digital value on the time axis (digital pulse width). For example, the conversion parameter may be a coefficient by which the digital value for each voltage value is multiplied to calculate the digital value on the time axis. Additionally, the conversion parameter may be a mathematical expression for which each digital value of the voltage axis is substituted to calculate the digital value on the time axis. Additionally, the conversion parameter may be a table indicating whether each digital value on the voltage axis should be converted to which digital value on the time axis; Paragraph [0036] Line 1-13; The adjusting section 86 adjusts the conversion parameter used to convert from the digital value on the voltage axis (digital voltage value) to the digital value of the time axis (digital pulse value) by the pulse width calculating section 82. For example, the adjusting section 86 may individually adjust the conversion parameter for each of the circuit for each channels 20. The adjusting section 86 may previously measure the characteristic for each measurement channel and adjust the conversion parameter based on the measurement result; Paragraph [0037] Line 1-13).
Regarding claim 10, Mitsuhashi teaches a test device,
wherein the pulse signal generator [10] is further configured to vary at least one of a width of the first pulse signal and a period of the first pulse signal (The sample clock generating section 84 generates a sample clock having a predetermined period and provides the same to the periodic pulse generating section 40 and the AD converting section 22; Paragraph [0033] Line 6-10; The sample clock generating section 84 may generate a sample clock having the pulse width larger than three periods of the signal-under-test, for example; Paragraph [0069] Line 1-3; The periodic pulse generating section 40 generates a periodic clock having a pulse width corresponding to one period of the signal-under-test in response to a sample clock which designates the timing at which the signal-under-test is sampled. An example of operation of the periodic pulse generating section 40 will be described later with reference to FIG. 4. That is, the periodic pulse generating section 40 outputs each period in a cycle of the signal-under-test designated by the sample clock, respectively as the amount of time indicated by the pulse width; Paragraph [0028] Line 1-10; therefore, the pulse signal is varying pulse generating section 40).
Regarding claim 11, Mitsuhashi teaches a test device,
wherein the test device further comprises a field programmable gate array (FPGA) that is configured to receive a signal (The data processing section 80 receives the digital voltage value outputted by each of the circuit for each channels 20 and performs a processing dependent on the digital voltage value. For example, the data processing section 80 may be a FPGA (Field Programmable Gate Array). In this case, the data processing section may perform a predetermined processing set in the FPGA; Paragraph [0032] Line 1-7), and
wherein at least one of the sampler [40+84+50+22] and the width analyzer [82] is included in the FPGA (The data processing section 80 according to the present embodiment includes a pulse width calculating section 82, an adjusting section 86 and a sample clock generating section 84. The operation of each of the pulse width calculating section 82, the adjusting section 86 and the sample clock generating section 84 may be previously set in the FPGA. The sample clock generating section 84 generates a sample clock having a predetermined period and provides the same to the periodic pulse generating section 40 and the AD converting section 22; Paragraph [0033] Line 1-10; The adjusting clock generating section 90 may be provided in the FPGA on which the data processing section 80 is provided; Paragraph [0038] Line 8-10).
Regarding claim 12, Mitsuhashi teaches a test device,
wherein the test device further comprises a printed circuit board (PCB) [110] (FIG. 1 shows an example of configuration of a test apparatus 100 according to an embodiment of the present invention. The test apparatus 100 having a mother board 110; Paragraph [0018] Line 1-3), a cable, and a connector (The mainframe 130 is connected to the test head 120 by such as an optical cable and a coaxial cable; Paragraph [0020] Line 1-2), and
wherein each of the channels [20] is included in at least one of the PCB, the cable, and the connector (FIG. 1 shows an example of configuration of a test apparatus 100 according to an embodiment of the present invention. The test apparatus 100 having a mother board 110, a test head 120 and a mainframe 130 that tests a device under test 200 such as a semiconductor circuit. The device under test 200 is placed on the mother board 110. The mother board 110 has a plurality of device side terminals which are electrically connected to each input/output pin of the device under test. The mother board 110 has a plurality of tester side terminals which are electrically connected to the test head 120; Paragraph [0018] Line 1-10; The mother board 110 is placed on the test head 120. A plurality of test modules 140 are also placed on the test head 120. Each of the test modules 140 is electrically connected to the tester side terminal of the mother board 110 and transmits/receives signals to/from the device under test 200; Paragraph [0019] Line 1-5).
Regarding claim 13, Mitsuhashi teaches a test device for testing a semiconductor (A test apparatus that tests a device under test such as a semiconductor circuit and a test module that is provided in the test apparatus; Paragraph [0002] Line 2-5; FIG. 1 shows an example of configuration of a test apparatus 100; Paragraph [0011] Line 1-2; FIG. 2 shows an example of configuration of a circuit provided on a test head 120; Paragraph [0012] Line 1-2), the test device [100] in Figure 1 comprising:
a pulse signal generator [10] in Figure 2 (signal provision section 10 as the pulse signal generator) that is configured to generate a test signal (signal-under-test as the test signal) (The test head 120 includes a signal provision section 10, a measurement circuit 12 and an operation section 122. The signal provision section 10 generates a test signal to test the device under test 200 and provides the same to the device under test 200. For example, the signal provision section 10 may provide a test pattern signal having a predetermined logic pattern signal and a source power; Paragraph [0022] Line 1-7);
a plurality of channels [20] that is configured to transmit the test signal (A measurement circuit 12 measures the output signal from the device under test 200. The measurement circuit 12 has a plurality of measurement channels. For example, the measurement circuit 12 may have a plurality of measurement channels each of which measures the output signal from the device under test 200; Paragraph [0023] Line 1-6; Each of the circuit for each channels 20 has an input section 26. The input section 26 receives output signals outputted from the corresponding device under test 200 or the output pins of the corresponding device under test 200. The input section 26 inputs the received output signal to the circuit for each channel 20 as a signal-under-test; Paragraph [0027] Line 1-8);
a sampler [40+84+50+22] that is configured to receive the test signal [signal-under-test] through at least one channel [20] of the plurality of channels (The periodic pulse generating section 40 generates a periodic clock having a pulse width corresponding to one period of the signal-under-test in response to a sample clock which designates the timing at which the signal-under-test is sampled. An example of operation of the periodic pulse generating section 40 will be described later with reference to FIG. 4. That is, the periodic pulse generating section 40 outputs each period in a cycle of the signal-under-test designated by the sample clock, respectively as the amount of time indicated by the pulse width; Paragraph [0028] Line 1-10) and conduct a sampling process on the test signal, based on a pulse signal (a sample clock having a predetermined period as the pulse signal) (The sample clock generating section 84 generates a sample clock having a predetermined period and provides the same to the periodic pulse generating section 40 and the AD converting section 22; Paragraph [0033] Line 6-10; The sample clock generating section 84 may generate a sample clock having the pulse width larger than three periods of the signal-under-test, for example; Paragraph [0069] Line 1-3);
a width analyzer [82] (the pulse width calculating section 82 as the width analyzer) (The data processing section 80 according to the present embodiment includes a pulse width calculating section 82; Paragraph [0033] Line 1-3) that is configured to generate a first measurement value (output from the width analyzer 82) by measuring a first width of the test signal based on a result of the sampling process (The pulse width calculating section 82 calculates a digital pulse width indicative of the width of the corresponding periodic pulse based on the digital voltage value outputted from each of the circuit for each channels 20; Paragraph [0034] Line 1-4; That is, the converting section 50 converts the value on the to axis to the value on the voltage axis and inputs the same to the AD converter 22 in order to detect the value for a period of a predetermined cycle of the signal-under-test by the AD converter 22. Then, the pulse width calculating section 82 converts the digital value on the voltage axis outputted by the AD converter 22 to the digital value (digital voltage value) on the time axis; Paragraph [0035] Line 1-8); and
a calculator [122] (the operation section as the calculator) (The test head 120 includes a signal provision section 10, a measurement circuit 12 and an operation section 122; Paragraph [0022] Line 1-2) that is configured to output a test result corresponding to each of the at least one channel [20] of the test device, based on the first measurement value (The operation section 122 may calculate the maximum value and the minimum value of the digital pulse width calculated by the pulse width calculating section 82. Additionally, the operation section 122 may further calculate the average value of the digital pulse width calculated by the pulse width calculating section 82; Paragraph [0042] Line 1-6).
Mitsuhashi fails to teach that calculate a final width value of the first pulse signal based on the first measurement value; determine whether an abnormality is present in one or more of the channels at least in part by comparing the final width value and an initial width value for the first pulse signal; and output a test result indicating whether the abnormality is present in the one or more of the channels.
Tomitaka teaches an abnormality determination method for a semiconductor radiation detector and a semiconductor radiation detector using the same (Paragraph [0001] Line 1), wherein
calculate a final width value of the first pulse signal based on the first measurement value (Since the count value becomes smoother than normal due to an increase in background noise, when the parameter α is increased and the count rate Ncb between Vc and Vb becomes equal to or greater than the pulse width determination coefficient rate NW, the test pulse width Wx becomes the test pulse. The upper limit value WxH of the width variation allowable range is exceeded and it is determined as abnormal. Then, in the case of an abnormality caused by this background noise increase, if the bias monitoring voltage Vx is changed from Vini = 15v to V0 = 0V, a curve like abnormality 2 in FIG. 11 is drawn; Paragraph [0083] Line 1-6; test pulse width as the final width value);
determine whether an abnormality is present in one or more of the channels (a plurality of bias monitoring voltages Vx as the plurality of channels) (The abnormality determination starts from the bias monitoring voltage initial value Vini (for example, Vini = 15 V), the bias monitoring voltage Vx is lowered from the bias monitoring voltage initial value Vini, and the same abnormality determination is performed with a plurality of bias monitoring voltages Vx, and the bias The process ends with the final monitoring voltage value V0 (for example, V0 = 0V) (FIG. 10); paragraph [0077] Line 1-4) at least in part by comparing the final width value (test pulse width as the final width) and an initial width value (lower limit value as the initial value) for the first pulse signal (Although the abnormality determination is performed while the bias monitoring voltage Vx is decreased, the abnormality determination may be performed while the bias monitoring voltage Vx is increased from the bias monitoring voltage initial value Vini = 0V. Further, in the above abnormality determination, the abnormality determination of the test pulse width Wx is performed while increasing the parameter α. However, the parameter α is decreased and the count rate Ncb becomes less than or less than the reference coefficient rate NW for pulse width determination. In this case, the test pulse width Wx may be determined to determine abnormality; Paragraph [0087] Line 1-7; Here, information (2) of the test pulse width determination reference coefficient rate NW1 at the bias monitoring voltage Vx1 is read from the memory 44. In this state, the count rate Ncb1 between Vc and Vb is measured while increasing the parameter α from 0. When the count rate Ncb1 becomes equal to or greater than the pulse width determination reference coefficient rate NW1, the test pulse width Wx1 is set to Wx1 = It is determined as 2α (measurement voltage width). (For example, the parameter α when the count rate Ncb1 = 50 cps> NW1 = 48 cps when the maximum peak value voltage Erx1 = 6 V referred from the bias monitoring voltage Vx1 = 10 V and the initial value α = 0.01 is increased to α = 0. When the voltage is .2 V, the test pulse width Wx1 of the bias monitoring voltage Vx1 = 10 V is set to Wx1 = 0.4 V.) By using this test pulse width Wx1, the bias monitoring stored in the memory 44 as shown in FIG. Referring to information (3) of allowable pulse width allowable range lower limit value WxL1 and allowable pulse width allowable range value WxH1 at voltage Vx1, it is determined whether or not it is within the allowable range of test pulse width (WxL1 <Wx1 <WxH1). When it deviates, it determines with it being abnormal; Paragraph [0076] Line 1-12); and
output a test result indicating whether the abnormality is present in the one or more of the channels (The signal processing unit 18 includes a count rate calculation unit 1, an abnormality determination unit 2, and a test pulse signal control unit 3. The signal processing unit 18 displays and stores a memory 44 that stores a reference value for abnormality determination and an output instruction value. Connected to a monitor / external storage device 45; Paragraph [0021] Line 1-4; The signal processing unit 18 outputs the abnormality determination result of the semiconductor sensor 11 from the abnormality determination unit 2 and the count rate calculation result of the count rate calculation unit 1 to the monitor / external storage device 45 as output instruction values; Paragraph [0041] Line 1-4). The purpose of doing so is to isolate the abnormal state by monitoring the change in the test pulse width and to widen the test pulse width, to provide a function of removing noise transients, an abnormality determination function at the time of disconnection, a data bidirectional communication function, and the like as and to check the soundness in more detail, to provide a function of downscaling the output instruction value when determining abnormality, to allow data download at any time for the purpose of data analysis to have bidirectional communication that can reflect each abnormality determination result.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Mitsuhashi in view of Tomitaka, because Tomitaka teaches to calculate a final width value of the first pulse signal based on the first measurement value and to determine whether an abnormality is present isolates the abnormal state by monitoring the change in the test pulse width and to widen the test pulse width (Paragraph [0085]) , provides a function of removing noise transients, an abnormality determination function at the time of disconnection, a data bidirectional communication function, and the like as (paragraph [0088] and to check the soundness in more detail (Paragraph [0090]), provides a function of downscaling the output instruction value when determining abnormality (Paragraph [0041]), allows data download at any time for the purpose of data analysis to have bidirectional communication that can reflect each abnormality determination result (paragraph [0042]).
Regarding claim 14, Mitsuhashi teaches a test device,
wherein the test device is configured to generate the test signal (signal-under-test as the test signal) and the pulse signal (a sample clock having a predetermined period as the pulse signal) independently (Claim 1: A test apparatus that tests a device under test, comprising: a signal provision section that provides a test signal to a device under test; an input section that inputs the output signal outputted from the device under test in response to the test signal as a signal-under-test; a periodic pulse generating section that generates a periodic pulse having a pulse width corresponding to one cycle of the signal-under-test; signal provision section 10 generates first pulse signal and sample clock generating section 84 generates second pulse signal).
Regarding claim 15, Mitsuhashi teaches a test device,
wherein the width analyzer [82] is further configured to measure a plurality of widths of the test signal and generate a plurality of measurement values, based on the result of the sampling process (The pulse width calculating section 82 calculates a digital pulse width indicative of the width of the corresponding periodic pulse based on the digital voltage value outputted from each of the circuit for each channels 20; Paragraph [0034] Line 1-4; The pulse width calculating section 82generates plurality of pulse width for each channel; the adjusting section 86 sets the conversion parameter to the plurality of adjusting clock in the pulse width calculating section 82 such that if the adjusting clocks are inputted to the input section 26, the digital voltage value measured by the AD converter 22 is converted to the digital pulse width corresponding to one period of the adjusting clock in the pulse width calculating section 82; Paragraph [0039] Line 1-7; Paragraph 35-37 explains the generation of a plurality of measurement values, based on the result of the sampling process); and
wherein the calculator [122] is further configured to calculate an average value of the plurality of widths of the test signal, based on the plurality of measurement values, and output the average value as the test result (The operation section 122 may calculate the maximum value and the minimum value of the digital pulse width calculated by the pulse width calculating section 82. Additionally, the operation section 122 may further calculate the average value of the digital pulse width calculated by the pulse width calculating section 82; Paragraph [0042] Line 1-6).
Regarding claim 16, Mitsuhashi teaches a test device,
wherein the sampler is further configured to convert the test signal into digital data based on the sampling process (The sample clock generating section 84 generates a sample clock having a predetermined period and provides the same to the periodic pulse generating section 40 and the AD converting section 22; Paragraph [0033] Line 6-10; The AD converter 22 converts the analog signal outputted by the converting section 50 to a digital voltage value. That is, the AD converter 22 outputs the digital voltage value corresponding to the value for each period in the cycle of the signal-under-test designated by the sample clock, respectively. The AD converter 22 may convert the analog voltage at the timing of the provided sample clock to a digital voltage value, and output the same; Paragraph [0030] Line 1-8).
Regarding claim 17, Mitsuhashi teaches a test device,
wherein the width analyzer [82] is further configured to measure a plurality of widths of the test signal and generate a plurality of measurement values, based on the result of the sampling process (The pulse width calculating section 82 calculates a digital pulse width indicative of the width of the corresponding periodic pulse based on the digital voltage value outputted from each of the circuit for each channels 20; Paragraph [0034] Line 1-4; The pulse width calculating section 82generates plurality of pulse width for each channel; the adjusting section 86 sets the conversion parameter to the plurality of adjusting clock in the pulse width calculating section 82 such that if the adjusting clocks are inputted to the input section 26, the digital voltage value measured by the AD converter 22 is converted to the digital pulse width corresponding to one period of the adjusting clock in the pulse width calculating section 82; Paragraph [0039] Line 1-7; Paragraph 35-37 explains the generation of a plurality of measurement values, based on the result of the sampling process), and
wherein the width analyzer [82] comprises a detector that is configured to generate a detection signal when a corresponding measurement value to the detector among the plurality of measurement values is detected, based on the digital data (The pulse width calculating section 82 may use a conversion parameter to convert each digital value on the voltage axis (digital voltage value) to the digital value on the time axis (digital pulse width). For example, the conversion parameter may be a coefficient by which the digital value for each voltage value is multiplied to calculate the digital value on the time axis. Additionally, the conversion parameter may be a mathematical expression for which each digital value of the voltage axis is substituted to calculate the digital value on the time axis. Additionally, the conversion parameter may be a table indicating whether each digital value on the voltage axis should be converted to which digital value on the time axis; Paragraph [0036] Line 1-13; The adjusting section 86 adjusts the conversion parameter used to convert from the digital value on the voltage axis (digital voltage value) to the digital value of the time axis (digital pulse value) by the pulse width calculating section 82. For example, the adjusting section 86 may individually adjust the conversion parameter for each of the circuit for each channels 20. The adjusting section 86 may previously measure the characteristic for each measurement channel and adjust the conversion parameter based on the measurement result; Paragraph [0037] Line 1-13).
Regarding claim 20, Mitsuhashi teaches a test device configured to test a semiconductor device (A test apparatus that tests a device under test such as a semiconductor circuit and a test module that is provided in the test apparatus; Paragraph [0002] Line 2-5; FIG. 1 shows an example of configuration of a test apparatus 100; Paragraph [0011] Line 1-2; FIG. 2 shows an example of configuration of a circuit provided on a test head 120; Paragraph [0012] Line 1-2), wherein the test device [100] in Figure 1 is further configured to:
generate a test signal (signal-under-test as the test signal) (The test head 120 includes a signal provision section 10, a measurement circuit 12 and an operation section 122. The signal provision section 10 generates a test signal to test the device under test 200 and provides the same to the device under test 200. For example, the signal provision section 10 may provide a test pattern signal having a predetermined logic pattern signal and a source power; Paragraph [0022] Line 1-7) and transmit the test signal through channels (A measurement circuit 12 measures the output signal from the device under test 200. The measurement circuit 12 has a plurality of measurement channels. For example, the measurement circuit 12 may have a plurality of measurement channels each of which measures the output signal from the device under test 200; Paragraph [0023] Line 1-6; Each of the circuit for each channels 20 has an input section 26. The input section 26 receives output signals outputted from the corresponding device under test 200 or the output pins of the corresponding device under test 200. The input section 26 inputs the received output signal to the circuit for each channel 20 as a signal-under-test; Paragraph [0027] Line 1-8);
convert the test signal into digital data by sampling the test signal (The sample clock generating section 84 may generate a sample clock having the pulse width larger than three periods of the signal-under-test, for example; Paragraph [0069] Line 1-3; The sample clock generating section 84 generates a sample clock having a predetermined period and provides the same to the periodic pulse generating section 40 and the AD converting section 22; Paragraph [0033] Line 6-10; The AD converter 22 converts the analog signal outputted by the converting section 50 to a digital voltage value. That is, the AD converter 22 outputs the digital voltage value corresponding to the value for each period in the cycle of the signal-under-test designated by the sample clock, respectively. The AD converter 22 may convert the analog voltage at the timing of the provided sample clock to a digital voltage value, and output the same; Paragraph [0030] Line 1-8);
measure values of widths of the test signal, based on the digital data (The data processing section 80 according to the present embodiment includes a pulse width calculating section 82; Paragraph [0033] Line 1-3;The pulse width calculating section 82 calculates a digital pulse width indicative of the width of the corresponding periodic pulse based on the digital voltage value outputted from each of the circuit for each channels 20; Paragraph [0034] Line 1-4; That is, the converting section 50 converts the value on the to axis to the value on the voltage axis and inputs the same to the AD converter 22 in order to detect the value for a period of a predetermined cycle of the signal-under-test by the AD converter 22. Then, the pulse width calculating section 82 converts the digital value on the voltage axis outputted by the AD converter 22 to the digital value (digital voltage value) on the time axis; Paragraph [0035] Line 1-8); and
generate a detection signal by detecting a corresponding value of a width of the test signal among the values of the widths of the test signal (The pulse width calculating section 82 may use a conversion parameter to convert each digital value on the voltage axis (digital voltage value) to the digital value on the time axis (digital pulse width). For example, the conversion parameter may be a coefficient by which the digital value for each voltage value is multiplied to calculate the digital value on the time axis. Additionally, the conversion parameter may be a mathematical expression for which each digital value of the voltage axis is substituted to calculate the digital value on the time axis. Additionally, the conversion parameter may be a table indicating whether each digital value on the voltage axis should be converted to which digital value on the time axis; Paragraph [0036] Line 1-13);
count in response to the detection signal to generate a counting result (The adjusting section 86 adjusts the conversion parameter used to convert from the digital value on the voltage axis (digital voltage value) to the digital value of the time axis (digital pulse value) by the pulse width calculating section 82. For example, the adjusting section 86 may individually adjust the conversion parameter for each of the circuit for each channels 20. The adjusting section 86 may previously measure the characteristic for each measurement channel and adjust the conversion parameter based on the measurement result; Paragraph [0037] Line 1-13; The adjusting clock generating section 90 may notify the adjusting section of the value of one period for each adjusting clock. Additionally, controlling the value of one period for the adjusting clock to be generated by the adjusting clock generating section 90, the adjusting section 86 may calculate the value of one period for each adjusting clock based on the control signal provided to the adjusting clock generating section 90. An example of operation of the adjusting section 86 will be described later with reference to FIG. 6; Paragraph [0040] Line 1-9; The adjusting clock generating section adjust the clock by counting the clock value); and
calculate a weighted average value of the values of the widths of the test signal, based on the counting result and the values of the widths of the test signal (The operation section 122 may calculate the maximum value and the minimum value of the digital pulse width calculated by the pulse width calculating section 82. Additionally, the operation section 122 may further calculate the average value of the digital pulse width calculated by the pulse width calculating section 82; Paragraph [0042] Line 1-6; By performing the above-described processing, the periodic variation of the device-under-signal can be easily evaluated by such as the mainframe 130 and an external electronic calculator. For example, the mainframe 130 may calculate the peak to peak value of the periodic jitter of the signal-under-test based on the difference between the maximum value and the minimum value of the digital pulse width calculated by the operation section 122. Additionally, the mainframe 130 may calculate the standard deviation of the periodic jitter of the signal-under-test based on the average value calculated by the operation section 122; Paragraph [0043] Line 1-11; Therefore, standard deviation is calculated and then average is calculated and therefore the average is weighted as the definition of weighted means A weighted average is a way to find an average where some values are more important or have a greater influence than others).
Mitsuhashi fails to teach that determine whether an abnormality is present in one or more of the channels at least in part by comparing the weighted average value of the values of the widths and an initial width value for the test signal; and output a test result indicating whether the abnormality is present in the one or more of the channels.
Tomitaka teaches an abnormality determination method for a semiconductor radiation detector and a semiconductor radiation detector using the same (Paragraph [0001] Line 1), wherein
determine whether an abnormality is present in one or more of the channels at least in part by comparing the weighted average value of the values of the widths and an initial width value for the test signal (Since the count value becomes smoother than normal due to an increase in background noise, when the parameter α is increased and the count rate Ncb between Vc and Vb becomes equal to or greater than the pulse width determination coefficient rate NW, the test pulse width Wx becomes the test pulse. The upper limit value WxH of the width variation allowable range is exceeded and it is determined as abnormal. Then, in the case of an abnormality caused by this background noise increase, if the bias monitoring voltage Vx is changed from Vini = 15v to V0 = 0V, a curve like abnormality 2 in FIG. 11 is drawn; Paragraph [0083] Line 1-6; a plurality of bias monitoring voltages Vx as the plurality of channels) (The abnormality determination starts from the bias monitoring voltage initial value Vini (for example, Vini = 15 V), the bias monitoring voltage Vx is lowered from the bias monitoring voltage initial value Vini, and the same abnormality determination is performed with a plurality of bias monitoring voltages Vx, and the bias The process ends with the final monitoring voltage value V0 (for example, V0 = 0V) (FIG. 10); paragraph [0077] Line 1-4) at least in part by comparing the final width value (test pulse width as the final width) and an initial width value (lower limit value as the initial value) for the first pulse signal ([0087] Although the abnormality determination is performed while the bias monitoring voltage Vx is decreased, the abnormality determination may be performed while the bias monitoring voltage Vx is increased from the bias monitoring voltage initial value Vini = 0V. Further, in the above abnormality determination, the abnormality determination of the test pulse width Wx is performed while increasing the parameter α. However, the parameter α is decreased and the count rate Ncb becomes less than or less than the reference coefficient rate NW for pulse width determination. In this case, the test pulse width Wx may be determined to determine abnormality; Paragraph [0087] Line 1-7; Here, information (2) of the test pulse width determination reference coefficient rate NW1 at the bias monitoring voltage Vx1 is read from the memory 44. In this state, the count rate Ncb1 between Vc and Vb is measured while increasing the parameter α from 0. When the count rate Ncb1 becomes equal to or greater than the pulse width determination reference coefficient rate NW1, the test pulse width Wx1 is set to Wx1 = It is determined as 2α (measurement voltage width). (For example, the parameter α when the count rate Ncb1 = 50 cps> NW1 = 48 cps when the maximum peak value voltage Erx1 = 6 V referred from the bias monitoring voltage Vx1 = 10 V and the initial value α = 0.01 is increased to α = 0. When the voltage is .2 V, the test pulse width Wx1 of the bias monitoring voltage Vx1 = 10 V is set to Wx1 = 0.4 V.) By using this test pulse width Wx1, the bias monitoring stored in the memory 44 as shown in FIG. Referring to information (3) of allowable pulse width allowable range lower limit value WxL1 and allowable pulse width allowable range value WxH1 at voltage Vx1, it is determined whether or not it is within the allowable range of test pulse width (WxL1 <Wx1 <WxH1). When it deviates, it determines with it being abnormal; Paragraph [0076] Line 1-12); and
output a test result indicating whether the abnormality is present in the one or more of the channels (The signal processing unit 18 includes a count rate calculation unit 1, an abnormality determination unit 2, and a test pulse signal control unit 3. The signal processing unit 18 displays and stores a memory 44 that stores a reference value for abnormality determination and an output instruction value. Connected to a monitor / external storage device 45; Paragraph [0021] Line 1-4; The signal processing unit 18 outputs the abnormality determination result of the semiconductor sensor 11 from the abnormality determination unit 2 and the count rate calculation result of the count rate calculation unit 1 to the monitor / external storage device 45 as output instruction values; Paragraph [0041] Line 1-4). The purpose of doing so is to isolate the abnormal state by monitoring the change in the test pulse width and to widen the test pulse width, to provide a function of removing noise transients, an abnormality determination function at the time of disconnection, a data bidirectional communication function, and the like as and to check the soundness in more detail, to provide a function of downscaling the output instruction value when determining abnormality, to allow data download at any time for the purpose of data analysis to have bidirectional communication that can reflect each abnormality determination result.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Mitsuhashi in view of Tomitaka, because Tomitaka teaches to output a test result indicating whether the abnormality is present in the one or more of the channels provides a function of removing noise transients, an abnormality determination function at the time of disconnection, a data bidirectional communication function, and the like as (paragraph [0088] and to check the soundness in more detail (Paragraph [0090]), provides a function of downscaling the output instruction value when determining abnormality (Paragraph [0041]), allows data download at any time for the purpose of data analysis to have bidirectional communication that can reflect each abnormality determination result (paragraph [0042]).
Claim(s) 4, 7-9 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuhashi ‘899 A1 in view of Tomitaka ‘454A, as applied to claims 1 and 13 above, and further in view of Webb et al. (Hereinafter, “Webb”) in the US Patent Application Publication Number US 20120176174 A1.
Regarding claim 4, the combination of Mitsuhashi and Tomitaka fails to teach a test device, wherein the sampler comprises a de-serializer that is configured to de-serialize the first pulse signal.
Webb teaches systems and methods for precise generation of phase variation, such as jitter and/or wander, in digital signals (Paragraph [0002] 2-4),
wherein the sampler comprises a de-serializer [116] in Figure 1A that is configured to de-serialize the first pulse signal (FIGS. 6A-6C are block diagrams of embodiments for providing event occurrence signals directly to deserializers and then generating event timing data; Paragraph [0043] Line 21-24; The deserializer circuitry 116 deserializes this modified bit stream 115 and produces an output 113 to the event timing detector circuitry 120. The output 113 is multi-bit parallel data words (e.g., M-bit data words) that represents a modified digital signal pattern based upon the modified bit stream 115. These multi-bit parallel data words 113 are then received and processed by event timing detector circuitry 120; Paragraph [0047] Line 11-18). The purpose of doing so is to achieve precision based upon the bit period of the high speed digital signals processed by these circuit devices and elements, to receive event occurrence signals and to provide a precision based upon the input bit periods of the deserializer circuitry.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Mitsuhashi and Tomitaka in view of Webb, because Webb teaches to include a de-serializer that is configured to de-serialize the first pulse signal achieves precision based upon the bit period of the high speed digital signals processed by these circuit devices and elements, receives event occurrence signals and to provide a precision based upon the input bit periods of the deserializer circuitry (Paragraph [0038]).
Regarding claim 7, the combination of Mitsuhashi and Tomitaka fails to teach a test device, wherein the width analyzer further comprises a counter corresponding to the detector, and the counter is configured to count in response to the detection signal and generate a counting value.
Webb teaches systems and methods for precise generation of phase variation, such as jitter and/or wander, in digital signals (Paragraph [0002] 2-4),
wherein the width analyzer further comprises a counter [210] corresponding to the detector (FIG. 2B is a block diagram of an embodiment for event detector and timestamp circuitry 120 that can be utilized to provide precise timestamps associated with detected events. As depicted, the event detector and timestamp circuitry 120 includes pattern predictor circuitry 202, bitwise comparison logic circuitry 204, priority encoder 206, timestamp circuitry 208 and time counter 210; Paragraph [0077] Line 1-7), and
the counter is configured to count in response to the detection signal and generate a counting value (The time counter circuitry 210 can be implemented as a conventional binary counter operated by the reference clock signal 118. For example, a binary counter that is 32-bits or 48-bits wide could be utilized depending on the desired range of time values for measurement. Other resolutions could also be utilized, as desired. The time counter circuitry 210 is utilized to keep a time count. For example, the time counter circuitry 210 can be configured to count up by one time unit at each rising edge of the reference clock signal 118. In one embodiment, the time counter 210 can be 48-bits wide and operate at about 156.25 MHz based upon a reference clock signal 118 operating at that rate. The value of the time counter 210 is then provided as an input to the timestamp circuitry 208; Paragraph [0083] Line 1-14). The purpose of doing so is to provide desired information relating to the transmission time of the packet or other desired timing related analysis, to generate desired phase variation, such as wander and/or jitter, in resulting signals, it is desirable to be able to achieve improved resolution in generating desired phase variation in digital signals.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Mitsuhashi and Tomitaka in view of Webb, because Webb teaches to include a counter to count in response to the detection signal and to generate a counting value provides desired information relating to the transmission time of the packet or other desired timing related analysis (Paragraph [0085]), generates desired phase variation, such as wander and/or jitter, in resulting signals, it is desirable to be able to achieve improved resolution in generating desired phase variation in digital signals (Paragraph [0005]).
Regarding claim 8, Mitsuhashi teaches a test device,
wherein the calculator [122] is further configured to calculate a weighted average value of the plurality of widths of the first pulse signal, based on the counting value and the plurality of measurement values (The operation section 122 may calculate the maximum value and the minimum value of the digital pulse width calculated by the pulse width calculating section 82. Additionally, the operation section 122 may further calculate the average value of the digital pulse width calculated by the pulse width calculating section 82; Paragraph [0042] Line 1-6; By performing the above-described processing, the periodic variation of the device-under-signal can be easily evaluated by such as the mainframe 130 and an external electronic calculator. For example, the mainframe 130 may calculate the peak to peak value of the periodic jitter of the signal-under-test based on the difference between the maximum value and the minimum value of the digital pulse width calculated by the operation section 122. Additionally, the mainframe 130 may calculate the standard deviation of the periodic jitter of the signal-under-test based on the average value calculated by the operation section 122; Paragraph [0043] Line 1-11; Therefore, standard deviation is calculated and then average is calculated and therefore the average is weighted as the definition of weighted means A weighted average is a way to find an average where some values are more important or have a greater influence than others).
Regarding claim 9, Mitsuhashi teaches a test device,
wherein the calculator is further configured to output the test result by comparing an initial width value of the first pulse signal with the weighted average value (The operation section 122 may calculate the maximum value and the minimum value of the digital pulse width calculated by the pulse width calculating section 82. Additionally, the operation section 122 may further calculate the average value of the digital pulse width calculated by the pulse width calculating section 82; Paragraph [0042] Line 1-6; By performing the above-described processing, the periodic variation of the device-under-signal can be easily evaluated by such as the mainframe 130 and an external electronic calculator. For example, the mainframe 130 may calculate the peak to peak value of the periodic jitter of the signal-under-test based on the difference between the maximum value and the minimum value of the digital pulse width calculated by the operation section 122. Additionally, the mainframe 130 may calculate the standard deviation of the periodic jitter of the signal-under-test based on the average value calculated by the operation section 122; Paragraph [0043] Line 1-11; Paragraph 0051).
Regarding claim 18, the combination of Mitsuhashi and Tomitaka fails to teach a test device, wherein the width analyzer further comprises a counter corresponding to the detector, and the counter is configured to count in response to the detection signal and generate a counting value.
Webb teaches systems and methods for precise generation of phase variation, such as jitter and/or wander, in digital signals (Paragraph [0002] 2-4),
wherein the width analyzer further comprises a counter [210] corresponding to the detector (FIG. 2B is a block diagram of an embodiment for event detector and timestamp circuitry 120 that can be utilized to provide precise timestamps associated with detected events. As depicted, the event detector and timestamp circuitry 120 includes pattern predictor circuitry 202, bitwise comparison logic circuitry 204, priority encoder 206, timestamp circuitry 208 and time counter 210; Paragraph [0077] Line 1-7), and
the counter is configured to count in response to the detection signal and generate a counting value (The time counter circuitry 210 can be implemented as a conventional binary counter operated by the reference clock signal 118. For example, a binary counter that is 32-bits or 48-bits wide could be utilized depending on the desired range of time values for measurement. Other resolutions could also be utilized, as desired. The time counter circuitry 210 is utilized to keep a time count. For example, the time counter circuitry 210 can be configured to count up by one time unit at each rising edge of the reference clock signal 118. In one embodiment, the time counter 210 can be 48-bits wide and operate at about 156.25 MHz based upon a reference clock signal 118 operating at that rate. The value of the time counter 210 is then provided as an input to the timestamp circuitry 208; Paragraph [0083] Line 1-14). The purpose of doing so is to provide desired information relating to the transmission time of the packet or other desired timing related analysis, to generate desired phase variation, such as wander and/or jitter, in resulting signals, it is desirable to be able to achieve improved resolution in generating desired phase variation in digital signals.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Mitsuhashi and Tomitaka in view of Webb, because Webb teaches to include a counter to count in response to the detection signal and to generate a counting value provides desired information relating to the transmission time of the packet or other desired timing related analysis (Paragraph [0085]), generates desired phase variation, such as wander and/or jitter, in resulting signals, it is desirable to be able to achieve improved resolution in generating desired phase variation in digital signals (Paragraph [0005]).
Regarding claim 19, Mitsuhashi teaches a test device,
wherein the calculator [122] is further configured to calculate a weighted average value of the plurality of widths of the test signal, based on the counting value and the plurality of measurement values (The operation section 122 may calculate the maximum value and the minimum value of the digital pulse width calculated by the pulse width calculating section 82. Additionally, the operation section 122 may further calculate the average value of the digital pulse width calculated by the pulse width calculating section 82; Paragraph [0042] Line 1-6; By performing the above-described processing, the periodic variation of the device-under-signal can be easily evaluated by such as the mainframe 130 and an external electronic calculator. For example, the mainframe 130 may calculate the peak to peak value of the periodic jitter of the signal-under-test based on the difference between the maximum value and the minimum value of the digital pulse width calculated by the operation section 122. Additionally, the mainframe 130 may calculate the standard deviation of the periodic jitter of the signal-under-test based on the average value calculated by the operation section 122; Paragraph [0043] Line 1-11; Therefore, standard deviation is calculated and then average is calculated and therefore the average is weighted as the definition of weighted means A weighted average is a way to find an average where some values are more important or have a greater influence than others), and
output the test result by comparing an initial width value of the test signal with the weighted average value (The operation section 122 may calculate the maximum value and the minimum value of the digital pulse width calculated by the pulse width calculating section 82. Additionally, the operation section 122 may further calculate the average value of the digital pulse width calculated by the pulse width calculating section 82; Paragraph [0042] Line 1-6; By performing the above-described processing, the periodic variation of the device-under-signal can be easily evaluated by such as the mainframe 130 and an external electronic calculator. For example, the mainframe 130 may calculate the peak to peak value of the periodic jitter of the signal-under-test based on the difference between the maximum value and the minimum value of the digital pulse width calculated by the operation section 122. Additionally, the mainframe 130 may calculate the standard deviation of the periodic jitter of the signal-under-test based on the average value calculated by the operation section 122; Paragraph [0043] Line 1-11; Paragraph 0051).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lim et al. (US 20210156904 A1) discloses, “SEMICONDUCTOR TEST DEVICE AND SYSTEM AND TEST METHOD USING THE SAME- [0002] The present inventive concept relates to a semiconductor test device and a test method using the same. [0021] In FIG. 1, each of the semiconductor chips assembled into one package in the semiconductor device 10 may correspond to a semiconductor package. Though not shown, the semiconductor device 10, which may be a semiconductor package, may be covered to include an encapsulating layer, or mold layer, formed thereon to cover the first semiconductor package 100, second semiconductor package 200, wiring circuit board 300, and lower substrate 400. [0022] The first semiconductor package 100 may be a memory package. For example, the first semiconductor package 100 may be a high bandwidth memory (HBM) package. The first semiconductor package 100 may include a plurality of microbumps 110, a base die 120, and memory dies 130-160. Each of the base die 120 and the memory dies 130-160 may be a semiconductor chip, for example, formed from a semiconductor substrate to have an integrated circuit formed thereon. [0023] The base die 120 may be disposed in a lowermost portion of the first semiconductor package 100. For example, the first memory die 130 may be stacked on the base die 120, and a second memory die 140 may be stacked on the first memory die 130. A third memory die 150 may be stacked on the second memory die 140, and a fourth memory die 160 may be stacked on the third memory die 150. The stacked memory dies 130-160 may be positioned above the base die 120 (e.g., to overlap from a top-down view). [0024] The base die 120 may include a plurality of through-substrate vias (TSVs) 122, which may be through-silicon vias, a circuit region 123, a wiring layer 124, and a test circuit TC-However Lim does not disclose calculate a final width value of the first pulse signal based on the first measurement value; determine whether an abnormality is present in one or more of the channels at least in part by comparing the final width value and an initial width value for the first pulse signal; and output a test result indicating whether the abnormality is present in the one or more of the channels.”
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NASIMA MONSUR whose telephone number is (571)272-8497. The examiner can normally be reached 10:00 am-6:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NASIMA MONSUR/Primary Examiner, Art Unit 2858