DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on June 23, 2026 is acknowledged.
Claims 13-15 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 23, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
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Claims 1, 3-5, and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210043675 A1), hereinafter referred to as "Wang", in view of McTeer (US 20040207030 A1), hereinafter referred to as "McTeer".
Regarding claim 1, Wang discloses a method of forming a light sensitive semiconductor structure, the method comprising: providing a semiconductor wafer comprising a semiconductor layer (substrate 102 in Wang figure 5) comprising a light sensitive region (heavily-doped region 114 in figure 5 is in the active region of the device (paragraph 0041), which is where the light is directed to generate a signal; it is thus sensitive to light); providing a gate structure comprising an insulation layer (126L in figure 5) on said semiconductor layer and a polysilicon layer (128L in figure 5) on said insulation layer; providing a contact stop layer (contact etch stop layer 134 in Wang figure 8B) on said gate structure, wherein said contact stop layer covers said light sensitive region (the CESL 134 covers the entire region 114 in figure 8B); and providing a plurality of metal layers (metallization layers 152 in figure 8B) comprising a first metal layer electrically connected to said semiconductor layer (lowest layer of 152 are connected to the semiconductor layer by contact plug 142) and a plurality of dielectric layers between metal layers of said plurality of metal layers (layers of IMD 150 in figure 8B).
Wang further discloses etching through the contact stop layer and the polysilicon layer to form an opening over said light sensitive region (the etches form opening 170 in figure 9B, which is above the region 114), and that it can be done using multiple etches (paragraph 0057).
However, Wang does not explicitly disclose providing an etch mask to define this opening, nor does Wang explicitly disclose that the multiple etch steps include using the polysilicon layer as an etch stop, then using the insulation layer as an etch stop.
McTeer teaches an etching process that includes providing an etch mask, said etch mask determining a position and a width of an opening to be formed (32 in McTeer figure 2, see McTeer paragraph 0021. These define the gate stacks, which will not be etched, and thus define the areas between the gate stacks, which will be etched. As applied to Wang, the masks would be formed over the areas not etched and define the opening to be etched, 170 in Wang); etching said contact stop layer using said etch mask (McTeer etches through capping layer 22, which is made of silicon nitride like the CESL of Wang, see McTeer paragraph 0021, and McTeer figure 3), wherein said polysilicon layer is used as a first etch stopping layer (McTeer paragraph 0021); and etching said polysilicon layer (McTeer paragraph 0023), wherein said insulation layer is used as a second etch stopping layer (McTeer paragraph 0023);
It would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take the known technique of etching using a photoresist mask, as taught by McTeer where it was used as part of a multiple part etch process, and apply it to the method of Wang in order to carry out the multiple step etch process mentioned there.
McTeer does not explicitly disclose that the polysilicon etch is carried out using a mask. However, Wang discloses using a mask for an etch step for other parts of the polysilicon layer (see Wang paragraph 0051). McTeer removes the photoresist 32 so that different processing can be done to the gate stack before the polysilicon is removed. However, in the simpler etching process required in Wang, it would be obvious to leave the photoresist mask on for the polysilicon etch, since there is no other processing needed between those steps, and it doesn’t necessitate using a separate material as a mask, simplifying the process.
Regarding claim 3, Wang in view of McTeer teaches all of the limitations of claim 1. Wang further discloses that said providing said contact stop layer comprises depositing one of a silicon nitride layer and a silicon oxynitride layer (Wang paragraph 0035).
Regarding claim 4, Wang in view of McTeer teaches all of the limitations of claim 1. Wang further discloses that said etching said contact stop layer comprises a dry etch (Wang paragraph 0057).
Regarding claim 5, Wang in view of McTeer teaches all of the limitations of claim 1. Wang further discloses that said etching said polysilicon layer comprises a dry etch (Wang paragraph 0057).
Regarding claim 6, Wang in view of McTeer teaches all of the limitations of claim 1. Wang further discloses forming metal contacts to connect to said light sensitive region (metal plugs 142/144/146 in Wang figure 8B, paragraph 0054) in order to apply a voltage across said light sensitive region (“During operation, the SPAD 110 is reverse biased above a breakdown voltage”, Wang paragraph 0027. As the contact plugs are what connect the active part of the SPAD to the rest of the metallization, it is obvious that they are what are applying the reverse bias voltage), wherein said contact stop layer is used as an etch stopping layer when forming said metal contacts (Wang paragraph 0035. The CESL is “for controlling an end point during etch processes for formation of contact plugs”).
Regarding claim 7, Wang in view of McTeer teaches all of the limitations of claim 1. Wang further discloses providing an anti- reflective coating, ARC, layer over said light sensitive region (Cap layer 172 is made of silicon nitride, see Wang paragraph 0042, which has a high refractive index of about 2 and low absorption in blue/UV range, making it have good anti-reflective properties).
Regarding claim 8, Wang in view of McTeer teaches all of the limitations of claim 1. Wang further discloses providing insulation around said light sensitive region by shallow trench isolation, STI (108 in Wang figure 5).
Regarding claim 9, Wang in view of McTeer teaches all of the limitations of claim 1. Wang further discloses providing a layer of an effective medium having a refractive index between a refractive index of silicon oxide and a refractive index of silicon (STI 108 can be made of silicon nitride, see Wang paragraph 0032, which has a refractive index between silicon oxide and silicon in various ranges of wavelength in visible light).
Regarding claim 10, Wang in view of McTeer teaches all of the limitations of claim 9. Wang further discloses that said providing said layer of said effective medium comprises shallow trench isolation, STI, in said semiconductor layer (108 are STI, and are in the semiconductor layer substrate 102, see Wang paragraph 0032).
Regarding claim 11, Wang in view of McTeer teaches all of the limitations of claim 1. Wang further teaches that the insulating layer and polysilicon gate layers can be deposited in a peripheral circuit area. Wang does not explicitly disclose patterning the polysilicon in that area to form a gate.
McTeer teaches patterning a polysilicon layer to form a gate in a transistor region of a semiconductor structure (see figure McTeer figure 6). McTeer also teaches that the gate is for a transistor (McTeer abstract and title).
It would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take the known process of patterning a gate, as taught by McTeer, in order to form a transistor in the peripheral circuit area of Wang, such as for the active quench circuit described in Wang (Wang paragraph 0032), since transistors are an integral part of most circuits in modern electronic devices.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of McTeer as applied to claim 1 above, and further in view of Cousins et al. (US 20130164878 A1), hereinafter referred to as "Cousins".
Regarding claim 2,Wang in view of McTeer teaches all of the limitations of claim 1. Wang further discloses depositing said polysilicon layer on said oxide layer (Wang paragraph 0050).
Neither Wang nor McTeer teach that the insulation layer is thermally grown.
Cousins teaches thermally growing an oxide layer being an insulation layer (Cousins paragraph 0018). Cousins also teaches that this creates a high-quality oxide, which provide improved passivation (paragraph 0018).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to thermally grow the oxide layer as in Cousins in order to gain improved passivation.
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Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of McTeer as applied to claim 11 above, and further in view of Fan et al. (US 8765585 B2), hereinafter referred to as "Fan".
Regarding claim 12, Wang in view of McTeer teaches all of the limitations of claim 11. Neither Wang nor McTeer explicitly discloses forming a metal contact to the gate.
Fan also teaches patterning a polysilicon layer to form a gate in a transistor region of a semiconductor structure (Fan column 5, lines 42-48), and further teaches forming a metal contact to connect to a gate (90A in Fan figure 12), wherein a contact stop layer is used to as an etch stopping layer when forming said metal contact (Fan uses etch stop layer 54 in the process of forming the metal contact to the gate (Fan column 11, lines 31-40, see figure 10), which can also be made of silicon nitride (Fan column 4, lines 65-67), just as the CESL can be in Wang).
It would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take a known technique of adding a gate contact, as taught by Fan, and add it to the combined device of Wang and McTeer in order to access the gate from above dielectric layers, such as the ILD of Wang, and thus connect the transistor to a wider circuit, such as the active quench circuit in Wang.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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